KR20040000702A - Method of forming a copper wiring in a semiconductor device - Google Patents

Method of forming a copper wiring in a semiconductor device Download PDF

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Publication number
KR20040000702A
KR20040000702A KR1020020035619A KR20020035619A KR20040000702A KR 20040000702 A KR20040000702 A KR 20040000702A KR 1020020035619 A KR1020020035619 A KR 1020020035619A KR 20020035619 A KR20020035619 A KR 20020035619A KR 20040000702 A KR20040000702 A KR 20040000702A
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South Korea
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film
layer
forming
interlayer insulating
damascene pattern
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KR1020020035619A
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Korean (ko)
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김경호
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주식회사 하이닉스반도체
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Priority to KR1020020035619A priority Critical patent/KR20040000702A/en
Publication of KR20040000702A publication Critical patent/KR20040000702A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a copper interconnection of a semiconductor device is provided to improve operation speed and reliability of device by forming a capping layer on a copper film. CONSTITUTION: The first interlayer dielectric(22) is formed on a semiconductor substrate(21). Damascene pattern is formed by selectively etching the first interlayer dielectric. After forming a diffusion barrier layer(23) and a seed layer(24) on the resultant structure, a copper film(25) is filled into the damascene pattern. By polishing the resultant structure using CMP, portions of the copper film(25) located in the damascene pattern are removed due to topology. A capping layer(26) is formed on the copper film(25). Then, the second interlayer dielectric(27) is formed on the resultant structure.

Description

반도체 소자의 구리 배선 형성 방법{Method of forming a copper wiring in a semiconductor device}Method of forming a copper wiring in a semiconductor device

본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 특히 다마신 패턴에 형성된 구리층 상부에만 Ta계 화합물, W계 화합물 또는 Ti계 화합물을 이용하여 캐핑층을 형성함으로써 고유전율의 캐핑층을 형성하여 발생되는 소자의 동작 속도 저하 및 신뢰성 저하를 방지할 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a copper wiring formation method of a semiconductor device. In particular, a capping layer having a high dielectric constant is formed by forming a capping layer using a Ta-based compound, a W-based compound, or a Ti-based compound only on a copper layer formed on a damascene pattern. The present invention relates to a method for forming a copper wiring of a semiconductor device which can prevent a decrease in operating speed and a decrease in reliability of a device.

종래의 반도체 소자의 구리 배선 형성 방법을 도 1을 이용하여 설명하면 다음과 같다.The copper wiring forming method of the conventional semiconductor device will be described with reference to FIG. 1 as follows.

소정의 구조가 형성된 반도체 기판(11) 상부에 저유전율막, SiO2막등으로 제 1 층간 절연막(12)을 형성한다. 제 1 층간 절연막(12)의 소정 영역에 다마신 공정을 실시하여 다마신 패턴을 형성한다. 다마신 패턴을 포함한 전체 구조 상부에 확산 방지막(13)을 형성한 후 그 상부에 시드층(14)을 형성한다. 다마신 패턴이 매립되도록 전체 구조 상부에 구리층(15)을 형성한 후 CMP 공정을 실시하여 제 1 층간 절연막(12) 상부에 형성된 구리층(15), 시드층(14) 및 확산 방지막(13)을 제거한다. 이에 의해 다마신 패턴 내부에만 구리층(15)이 매립되어 구리 배선이 형성된다. 전체 구조 상부에 SiN막등으로 캐핑층(16)을 형성한 후 저유전율막, SiO2막등으로 제 2 층간 절연막(17)을 형성한다.The first interlayer insulating film 12 is formed of a low dielectric constant film, a SiO 2 film, or the like on the semiconductor substrate 11 having a predetermined structure. A damascene process is performed on a predetermined region of the first interlayer insulating film 12 to form a damascene pattern. The diffusion barrier layer 13 is formed on the entire structure including the damascene pattern, and then the seed layer 14 is formed thereon. The copper layer 15 is formed on the entire structure to fill the damascene pattern, and then a CMP process is performed to form the copper layer 15, the seed layer 14, and the diffusion barrier layer 13 formed on the first interlayer insulating layer 12. ). As a result, the copper layer 15 is embedded only in the damascene pattern to form a copper wiring. After the capping layer 16 is formed of an SiN film or the like on the entire structure, a second interlayer insulating film 17 is formed of a low dielectric constant film, a SiO 2 film, or the like.

상기와 같은 구리 배선 형성 공정에서 SiN막을 캐핑층으로 사용하는데, SiN막은 층간 절연막으로 사용되는 저유전율막 또는 SiO2막보다 유전율이 높기 때문에 소자의 캐패시턴스(capacitance)를 증가시켜 소자의 동작 속도를 저하시키게 된다. 또한, 구리층과 캐핑층 사이의 계면은 구리 원자의 일렉트로마이그레이션 활성화 에너지(electromigration activation energy)가 구리층과 확산 방지막의 계면 또는 구리 그레인 바운더리보다 낮기 때문에 소자의 신뢰성을 저하시키게 된다.In the copper wiring forming process as described above, the SiN film is used as the capping layer, and since the SiN film has a higher dielectric constant than the low dielectric constant film or SiO 2 film used as the interlayer insulating film, the capacitance of the device is increased to decrease the operation speed of the device. Let's go. In addition, the interface between the copper layer and the capping layer lowers the reliability of the device because the electromigration activation energy of the copper atoms is lower than the interface or copper grain boundary of the copper layer and the diffusion barrier.

본 발명의 목적은 소자의 구리층의 상부에만 확산 방지막을 형성함으로써 캐핑층을 형성하여 발생하는 소자의 동작 속도 및 신뢰성의 저하를 방지할 수 있는 반도체 소자의 구리 배선 형성 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a copper wiring of a semiconductor device, which can prevent the deterioration of the operation speed and the reliability of the device caused by forming a capping layer by forming a diffusion barrier only on the copper layer of the device.

본 발명에 따른 반도체 소자의 구리 배선 형성 방법은 소정의 구조가 형성된 반도체 기판 제 1 층간 절연막을 형성한 후 상기 제 1 층간 절연막의 소정 영역에 다마신 패턴을 형성하는 단계와, 상기 다마신 패턴을 포함한 전체 구조 상부에 확산 방지막 및 시드층을 형성한 후 상기 다마신 패턴이 매립되도록 구리층을 형성하는 단계와, CMP 공정을 실시하여 상기 제 1 층간 절연막 상부에 형성된 상기 구리층, 시드층 및 확산 방지막을 제거하고, 상기 다마신 패턴과 상기 제 1 층간 절연막의 단차에 의해 상기 구리층의 일부가 제거되는 단계와, 전체 구조 상부에 캐핑층을 형성한 후 CMP 공정을 실시하여 상기 구리층 상부에만 상기 캐핑층을 잔류시키는 단계와, 전체 구조 상부에 제 2 층간 절연막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The method for forming a copper wiring of a semiconductor device according to the present invention includes forming a damascene pattern in a predetermined region of the first interlayer insulating film after forming a first interlayer insulating film of a semiconductor substrate having a predetermined structure; Forming a diffusion barrier layer and a seed layer over the entire structure including a copper layer to fill the damascene pattern, and performing a CMP process, wherein the copper layer, seed layer, and diffusion are formed on the first interlayer insulating layer. Removing the barrier layer, removing a portion of the copper layer by the step between the damascene pattern and the first interlayer insulating layer, and forming a capping layer on the entire structure, and then performing a CMP process to perform the CMP process only on the copper layer. And retaining the capping layer and forming a second interlayer insulating film over the entire structure.

도 1은 종래의 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 도시한 소자의 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a device shown for explaining a copper wiring formation method of a conventional semiconductor device.

도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown in order to explain a method for forming a copper wiring of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11 및 21 : 반도체 기판12 및 22 : 제 1 층간 절연막11 and 21: semiconductor substrate 12 and 22: first interlayer insulating film

13 및 23 : 확산 방지막14 및 24 : 시드층13 and 23: diffusion barrier films 14 and 24: seed layer

15 및 25 : 구리층16 : 캐핑층(SiN막)15 and 25: copper layer 16: capping layer (SiN film)

26 : 캐핑층(Ta계 화합물, W계 화합물 또는 Ti계 화합물)26: capping layer (Ta-based compound, W-based compound or Ti-based compound)

17 및 27 : 제 2 층간 절연막17 and 27: second interlayer insulating film

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써 본 발명을 상세히 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예는 본 발명의 개시가 완전하도록 하며, 이 기술 분야에서 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 또한, 도면상에서 동일 부호는 동일 요소를 지칭한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.

도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method for forming a copper wiring of a semiconductor device according to the present invention.

도 2(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(21) 상부에 저유전율막, SiO2막등으로 제 1 층간 절연막(22)을 형성한다. 제 1 층간 절연막(22)의 소정 영역에 다마신 공정을 실시하여 다마신 패턴을 형성한다. 다마신 패턴을 포함한 전체 구조 상부에 확산 방지막(23)을 형성한 후 그 상부에 시드층(24)을 형성한다. 다마신 패턴이 매립되도록 전체 구조 상부에 구리층(25)을 형성한다. CMP 공정을 실시하여 제 1 층간 절연막(22) 상부에 형성된 구리층(25), 시드층(24) 및 확산 방지막(23)을 제거한다. 이때, 다마신 패턴과 제 1 층간 절연막(22)의 단차에 의해제 1 층간 절연막(22) 상부의 구리층(25), 시드층(24) 및 확산 방지막(23)이 제거될 때 다마신 패턴에 매립된 구리층(25)도 일부 식각된다.Referring to FIG. 2A, a first interlayer insulating film 22 is formed of a low dielectric constant film, a SiO 2 film, or the like on the semiconductor substrate 21 having a predetermined structure. A damascene pattern is formed on a predetermined region of the first interlayer insulating film 22 to form a damascene pattern. After forming the diffusion barrier 23 over the entire structure including the damascene pattern, the seed layer 24 is formed thereon. A copper layer 25 is formed on the entire structure so that the damascene pattern is embedded. The CMP process is performed to remove the copper layer 25, the seed layer 24, and the diffusion barrier layer 23 formed on the first interlayer insulating layer 22. At this time, when the copper layer 25, the seed layer 24, and the diffusion barrier layer 23 on the first interlayer insulating layer 22 are removed by the step between the damascene pattern and the first interlayer insulating layer 22, the damascene pattern. The copper layer 25 embedded in is also partially etched.

도 2(b)를 참조하면, 전체 구조 상부에 캐핑층(26)을 형성하는데, 바람직하게는 다마신 패턴의 일부 식각된 구리층(25)의 두께보다 두껍게 형성한다. 여기서, 캐핑층(26)은 Ta계 화합물, W계 화합물, Ti계 화합물을 이용하여 형성한다. Ta계 화합물은 Ta막, TaN막, TaSiN막 및 Ta막과 TaN막의 적층막을 포함하고, W계 화합물은 W막, WN막 및 WSiN막을 포함한다. 또한, Ti계 화합물은 Ti막, TiN막, TiSiN막 및 Ti막과 TiN막의 적층막을 포함한다.Referring to FIG. 2 (b), the capping layer 26 is formed on the entire structure, preferably thicker than the thickness of the partially etched copper layer 25 of the damascene pattern. Here, the capping layer 26 is formed using a Ta-based compound, a W-based compound, or a Ti-based compound. The Ta-based compound includes a Ta film, a TaN film, a TaSiN film, and a laminated film of a Ta film and a TaN film, and the W-based compound includes a W film, a WN film, and a WSiN film. The Ti compound includes a Ti film, a TiN film, a TiSiN film, and a laminated film of a Ti film and a TiN film.

도 2(c)를 참조하면, CMP 공정을 실시하여 제 1 층간 절연막(22) 상부에 형성된 캐핑층(26)을 제거한다. 이때, 제 1 층간 절연막(22) 상부에 형성된 캐핑층(26)과 구리층(25) 상부에 형성된 캐핑층(26)의 제거 속도의 차이에 의해 제 1 층간 절연막(22) 상부의 캐핑층(26)이 완전히 제거되더라도 구리층(25) 상부에는 캐핑층(26)이 일부 잔류된다. 이후 전체 구조 상부에 저유전율막, SiO2막등으로 제 2 층간 절연막(27)을 형성한다.Referring to FIG. 2C, a CMP process is performed to remove the capping layer 26 formed on the first interlayer insulating layer 22. In this case, the capping layer on the first interlayer insulating layer 22 may be formed due to a difference in the removal rate between the capping layer 26 formed on the first interlayer insulating layer 22 and the capping layer 26 formed on the copper layer 25. Even if 26 is completely removed, a part of the capping layer 26 remains on the copper layer 25. Thereafter, a second interlayer insulating film 27 is formed of a low dielectric constant film, a SiO 2 film, or the like on the entire structure.

상술한 바와 같이 본 발명에 의하면 구리층 상부에만 캐핑층을 형성함으로써 SiN막과 같은 고유전율막을 전체적으로 형성하기 때문에 발생하는 소자의 동작 속도 및 신뢰성의 저하를 방지할 수 있다.As described above, according to the present invention, the capping layer is formed only on the copper layer, thereby forming a high-k dielectric film such as a SiN film as a whole, thereby preventing a decrease in operating speed and reliability of the device.

Claims (5)

소정의 구조가 형성된 반도체 기판 제 1 층간 절연막을 형성한 후 상기 제 1 층간 절연막의 소정 영역에 다마신 패턴을 형성하는 단계;Forming a first interlayer insulating film having a predetermined structure and then forming a damascene pattern in a predetermined region of the first interlayer insulating film; 상기 다마신 패턴을 포함한 전체 구조 상부에 확산 방지막 및 시드층을 형성한 후 상기 다마신 패턴이 매립되도록 구리층을 형성하는 단계;Forming a diffusion barrier layer and a seed layer on the entire structure including the damascene pattern, and then forming a copper layer to embed the damascene pattern; CMP 공정을 실시하여 상기 제 1 층간 절연막 상부에 형성된 상기 구리층, 시드층 및 확산 방지막을 제거하고, 상기 다마신 패턴과 상기 제 1 층간 절연막의 단차에 의해 상기 구리층의 일부가 제거되는 단계;Performing a CMP process to remove the copper layer, the seed layer, and the diffusion barrier formed on the first interlayer insulating film, and removing a portion of the copper layer by a step between the damascene pattern and the first interlayer insulating film; 전체 구조 상부에 캐핑층을 형성한 후 CMP 공정을 실시하여 상기 구리층 상부에만 상기 캐핑층을 잔류시키는 단계; 및Forming a capping layer over the entire structure and then performing a CMP process to leave the capping layer only on the copper layer; And 전체 구조 상부에 제 2 층간 절연막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.Forming a second interlayer insulating film over the entire structure. 제 1 항에 있어서, 상기 캐핑층은 Ta계 화합물, W계 화합물 및 Ti계 화합물을 포함하는 물질로 형성하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 1, wherein the capping layer is formed of a material including a Ta-based compound, a W-based compound, and a Ti-based compound. 제 2 항에 있어서, 상기 Ta계 화합물은 Ta막, TaN막, TaSiN막 및 Ta막과 TaN막의 적층막을 포함하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 2, wherein the Ta-based compound comprises a Ta film, a TaN film, a TaSiN film, and a laminated film of a Ta film and a TaN film. 제 2 항에 있어서, 상기 W계 화합물은 W막, WN막 및 WSiN막을 포함하는 것을 특징으로 하는 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 2, wherein the W-based compound comprises a W film, a WN film and a WSiN film. 제 2 항에 있어서, 상기 Ti계 화합물은 Ti막, TiN막, TiSiN막 및 Ti막과 TiN막의 적층막을 포함하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 2, wherein the Ti-based compound comprises a Ti film, a TiN film, a TiSiN film, and a laminated film of a Ti film and a TiN film.
KR1020020035619A 2002-06-25 2002-06-25 Method of forming a copper wiring in a semiconductor device KR20040000702A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100778855B1 (en) * 2005-12-29 2007-11-22 동부일렉트로닉스 주식회사 Method for preventing hillock on copper metallization layer
US7470612B2 (en) 2005-09-13 2008-12-30 Samsung Electronics Co, Ltd. Method of forming metal wiring layer of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7470612B2 (en) 2005-09-13 2008-12-30 Samsung Electronics Co, Ltd. Method of forming metal wiring layer of semiconductor device
KR100778855B1 (en) * 2005-12-29 2007-11-22 동부일렉트로닉스 주식회사 Method for preventing hillock on copper metallization layer

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