KR20030069407A - Method of manufacturing a heterojunction CMOS transistor in a semiconductor device - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 72
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 70
- 239000010703 silicon Substances 0.000 claims abstract description 70
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 3
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 3
- 230000012010 growth Effects 0.000 claims description 22
- 229910052732 germanium Inorganic materials 0.000 claims description 14
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 4
- 230000004888 barrier function Effects 0.000 claims 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims 2
- 239000010409 thin film Substances 0.000 claims 2
- 229910052697 platinum Inorganic materials 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 230000000295 complement effect Effects 0.000 abstract 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 16
- 238000005468 ion implantation Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 229910021480 group 4 element Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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Abstract
Description
본 발명은 이종접합 구조를 갖는 반도체 소자의 시모스 트랜지스터 제조 방법에 관한 것으로, 특히 CVD(Chemical Vapor Deposition)으로 실리콘-게르마늄층을 형성하는 이종접합 구조를 갖는 반도체 소자의 시모스 트랜지스터 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure, and more particularly, to a method of manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure in which a silicon-germanium layer is formed by CVD (Chemical Vapor Deposition).
일반적으로, 대부분의 반도체 집적회로는 CMOS 회로로 이루어진다. CMOS 회로는 실리콘 기판 상에 제조되며, 실리콘은 저렴한 생산비와 고밀도-고집적이 가능하다는 장점이 있다.In general, most semiconductor integrated circuits consist of CMOS circuits. CMOS circuits are fabricated on silicon substrates, and silicon has the advantages of low production cost and high density-high integration.
그러나, 최근에 데이터 전송량 및 그에 따른 데이터 처리속도가 크게 증가되면서 고밀도, 고집적 능력과 함께 빠른 동작속도가 절실히 필요해짐에 따라 실리콘이 가지고 있는 특성상의 한계를 극복하려는 연구가 계속 진행되고 있다.However, in recent years, as the data transfer amount and the data processing speed thereof are greatly increased, researches to overcome the limitations of the characteristics of silicon have been continuously conducted as the high-density, high-density capability and fast operation speed are urgently needed.
도 1은 CMOS 회로에서 일반적으로 사용되는 PMOS 트랜지스터와 NMOS 트랜지스터가 형성된 상태의 단면도이다.1 is a cross-sectional view of a state in which a PMOS transistor and an NMOS transistor generally used in a CMOS circuit are formed.
도 1을 참조하면, 실리콘 기판(11)의 소자 분리 영역에는 소자 분리막(12)이 형성되고, 소자가 형성되는 활성 영역에는 웰이 형성되어 활성 영역은 P웰 영역(13a)과 n웰 영역(13b)으로 나뉘어 진다. P웰 영역(13a)과 n웰 영역(13b)에는 게이트 산화막(14), 게이트 전극(15), 게이트 스페이서(16), LDD 구조를 갖는 소오스/드레인(17a 및 17b) 및 실리사이드층(18)으로 이루어진 NMOS 트랜지스터(110)와 PMOS 트랜지스터(120)가 각각 제조된다.Referring to FIG. 1, an isolation layer 12 is formed in an isolation region of a silicon substrate 11, a well is formed in an active region in which an element is formed, and the active regions include a P well region 13a and an n well region ( 13b). In the P well region 13a and the n well region 13b, the gate oxide layer 14, the gate electrode 15, the gate spacer 16, the source / drain 17a and 17b having the LDD structure, and the silicide layer 18 are formed. NMOS transistor 110 and PMOS transistor 120 made of each is manufactured.
상기와 같이, NMOS 트랜지스터(110)와 PMOS 트랜지스터(120)는 순수한 실리콘으로 이루어진 실리콘 기판 상에 제조되는데, 실리콘은 이동도가 낮은 단점이 있기 때문에 고밀도 및 초고속의 동작 속도가 요구되는 회로를 구현하기에는 적합치 않다.As described above, the NMOS transistor 110 and the PMOS transistor 120 are manufactured on a silicon substrate made of pure silicon. Since silicon has a disadvantage of low mobility, it is difficult to implement a circuit requiring high density and ultra-high speed of operation. Not suitable
이를 극복하기 위한 대안으로 가장 기대를 모으는 기술은 실리콘에 게르마늄을 첨가하여 이종접합구조로 트랜지스터를 제조하는 기술로써, 기존의 다른 화합물 반도체 소자들과 대등한 수준의 동작속도를 확보할 수 있다. 이 기술은 기본적으로 실리콘과 게르마늄이 같은 4족 원소이면서도 밴드갭 에너지가 다르다는 것(예를 들면, 실리콘은 1.12eV, 게르마늄은 0.68eV)과 원자간의 거리가 다르다는 것(예를 들면, 실리콘은 0.5431nm, 게르마늄은 0.5646nm)을 이용한 기술이다. 즉, NMOS 트랜지스터의 경우 응력이 가해진 실리콘을 채널층으로 사용하면, 실리콘과 실리콘-게르마늄(SiGe)간의 밴드갭 에너지 차이와 응력에 의하여 캐리어의 이동도가 증가하게 된다. 캐리어의 이동도가 증가하는 것은 소자의 동작 속도가 증가하는 것이므로 초고속의 동작 특성을 갖는 트랜지스터를 제조할 수 있다. PMOS 트랜지스터의 경우는 실리콘대신 실리콘-게르마늄을 채널층으로 사용하면 초고속의 동작 특성을 얻을 수 있다.As an alternative to overcome this problem, the most anticipated technology is a technique of manufacturing a transistor in a heterojunction structure by adding germanium to silicon, and it is possible to obtain an operation speed comparable to other compound semiconductor devices. This technique basically states that silicon and germanium have the same group 4 elements but different bandgap energies (e.g., 1.12 eV for silicon, 0.68 eV for germanium) and different distances between atoms (e.g., 0.5431 for silicon). nm, germanium is 0.5646nm). That is, in the case of an NMOS transistor, when stressed silicon is used as a channel layer, carrier mobility increases due to a band gap energy difference and stress between silicon and silicon-germanium (SiGe). Increasing the mobility of the carrier is to increase the operating speed of the device can manufacture a transistor having an ultra-fast operating characteristics. In the case of PMOS transistors, silicon-germanium is used as the channel layer instead of silicon to obtain ultra-fast operating characteristics.
실리콘-게르마늄/실리콘의 이종접합을 이용한 금속-산화막-반도체 전계효과 트랜지스터(MOSFET)는 일반적인 실리콘 트랜지스터보다 이득이나 캐리어이동도 측면에서 우수한 특성을 보이지만, NMOS 트랜지스터와 PMOS 트랜지스터의 채널구조가 다를 뿐만 아니라 열적으로 매우 불안정하기 때문에 동일한 기판 상에 함께 제작하는 것은 매우 어렵다.Metal-oxide-semiconductor field effect transistors (MOSFETs) using heterojunctions of silicon-germanium / silicon show superior characteristics in terms of gain and carrier mobility than conventional silicon transistors, but the channel structures of NMOS transistors and PMOS transistors are different. It is very difficult to fabricate together on the same substrate because it is very unstable thermally.
또한, 실리콘에 게르마늄을 첨가할 경우 공정상에서 여러 가지 문제점이 발생되는데, 이 중 중요한 몇 가지만 설명하면 다음과 같다.In addition, when germanium is added to silicon, various problems occur in the process, and only a few of them are described as follows.
첫째, 게르마늄과 실리콘는 원자간 거리가 서로 다르기 때문에 응력이 발생되는 장점이 있지만, 에피성장법으로 실리콘 기판 상부에 실리콘-게르마늄층을 형성하기가 매우 힘들다. 실리콘으로 이루어진 기판 상부에 실리콘과 원자간거리가 다른 물질을 에피성장시킨 구조를 이종접합구조라고 하며, 실리콘-게르마늄층은 주로 MBE(Molecular Beam Epitaxial) 와 CVD법으로 형성되는데, 특성상 실리콘에 게르마늄을 많이 첨가할수록 응력이 유지된 상태로 결함없이 성장시킬 수 있는 에피층 두께는 줄어든다.First, germanium and silicon have an advantage that stress is generated because the distance between atoms is different, but it is very difficult to form a silicon-germanium layer on the silicon substrate by the epitaxial growth method. The structure that epitaxially grows a material having a different atomic distance from silicon on a substrate made of silicon is called a heterojunction structure, and a silicon-germanium layer is mainly formed by a molecular beam epitaxial (MBE) and CVD method. As it is added, the thickness of the epilayer that can be grown without defects while maintaining stress is reduced.
둘째, 실리콘-게르마늄층은 순수한 Si과는 달리 좋은 특성의 산화막을 성장시킬 수 없기 때문에 트랜지스터의 게이트 산화막을 형성하는데 어려움이 있다. 실제로, 트랜지스터의 성능은 게이트 산화막에 따라 결정될 만큼 게이트 산화막은 절대적으로 중요한데, 게르마늄 산화막은 실리콘 산화막과는 달리 특성면에서 열악하여 좋은 소자를 만들기에 적합치 않다. 즉, 게이트 산화막을 형성하기 위하여 산화 공정을 실시하는 과정에서 게르마늄의 편석이 발생되어 산화막과 반도체 기판의 계면에 결함이 발생되고, 이로 인하여 소자의 특성이 저하된다. 그러므로, 실리콘-게르마늄의 이종접합구조를 이용하여 트랜지스터를 형성하더라도 게이트 산화막을 형성하기 전의 최상부층이 실리콘-게르마늄층 대신에 실리콘층으로 이루어져야 우수한 막질의 게이트 산화막을 얻을 수 있다. 또한, 게이트 산화막을 형성하는 공정뿐만 아니라 필드 산화막을 형성하는 공정에도 동일한 문제가 발생되므로, 실리콘 기판 상에서 오랜 시간에 걸쳐 900℃이하의 고온으로 필드 산화막을 형성하는 공정을 그대로 적용하는데 어려움이 있다. 이러한 이유로 저온 산화막(LTO)이 주로 이용되는데, 저온 산화막은 고밀도 구조에 적합치 못한 단점이 있다.Second, since the silicon-germanium layer cannot grow an oxide film having good properties unlike pure Si, it is difficult to form a gate oxide film of a transistor. In fact, the gate oxide film is absolutely important so that the performance of the transistor is determined by the gate oxide film. Unlike the silicon oxide film, the germanium oxide is poor in characteristics and is not suitable for making a good device. That is, segregation of germanium occurs in the process of performing the oxidation process to form the gate oxide film, and defects occur at the interface between the oxide film and the semiconductor substrate, thereby degrading the characteristics of the device. Therefore, even when a transistor is formed by using a heterojunction structure of silicon-germanium, the top layer before forming the gate oxide film should be made of a silicon layer instead of the silicon-germanium layer to obtain a good gate oxide film. In addition, since the same problem occurs not only in the process of forming the gate oxide film but also in the process of forming the field oxide film, it is difficult to apply the process of forming the field oxide film at a high temperature of 900 ° C. or less over a long time on the silicon substrate as it is. For this reason, the low temperature oxide film (LTO) is mainly used, but the low temperature oxide film has a disadvantage in that it is not suitable for a high density structure.
셋째, 실리콘-게르마늄/실리콘으로 이루어진 CMOS 트랜지스터를 동일한 실리콘 기판 상부에 구현하기가 쉽지 않다. 가장 큰 장애물은 PMOS 트랜지스터와 NMOS 트랜지스터의 에피구조가 다르다는 것이다. PMOS 트랜지스터의 채널층은 실리콘-게르마늄층이고 NMOS 트랜지스터의 채널층은 실리콘층으로 서로 다를 뿐 아니라, 채널층 바로 아래의 응력완화된 버퍼층도 각각 실리콘층 및 실리콘-게르마늄층으로 서로 반대이다. 이 이유 때문에 아직까지 실리콘-게르마늄 이종접합을 이용한 CMOS 트랜지스터는 보고된 바가 없고, 현재 PMOS 트랜지스터와 NMOS 트랜지스터가 독립적으로 개발되고 있는 실정이다.Third, it is difficult to implement a CMOS transistor made of silicon-germanium / silicon on the same silicon substrate. The biggest obstacle is that the epistructures of PMOS transistors and NMOS transistors are different. The channel layer of the PMOS transistor is a silicon-germanium layer and the channel layer of the NMOS transistor is not only different from each other as the silicon layer, but also the stress relaxation buffer layer immediately below the channel layer is opposite to the silicon layer and the silicon-germanium layer, respectively. For this reason, a CMOS transistor using a silicon-germanium heterojunction has not been reported so far, and PMOS transistors and NMOS transistors are currently being developed independently.
상기에서 서술한 바와 같이, 실리콘-게르마늄 구조는 실리콘 구조에 비해 공정이 복잡하고 공정 진행 속도가 느릴 뿐 아니라, 실제적으로 NMOS 트랜지스터와 PMOS 트랜지스터를 동일 기판 상에 제조하는데 어려움이 있다.As described above, the silicon-germanium structure is not only complicated in the process and slow in progress compared to the silicon structure, but also has difficulty in manufacturing the NMOS transistor and the PMOS transistor on the same substrate.
따라서, 본 발명은 고온에서 CVD법으로 기판 상부에 실리콘-게르마늄 에피층을 형성하고, 선택적 에피 성장법으로 PMOS 트랜지스터가 형성될 n웰에만 실리콘-게르마늄으로 이루어진 채널층을 형성한 후 실리콘층을 형성하여 PMOS 트랜지스터 영역에서는 게이트 산화막을 형성하기 위한 희생층으로 사용하고, NMOS 트랜지스터영역에서는 채널층으로도 사용함으로써, 상기의 문제점들을 해결할 수 있는 이종접합 구조를 갖는 반도체 소자의 시모스 트랜지스터 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention forms a silicon-germanium epi layer on the substrate by CVD at a high temperature, and forms a silicon layer after forming a channel layer made of silicon-germanium only on the n well where the PMOS transistor is to be formed by the selective epitaxial growth method. By using the sacrificial layer for forming the gate oxide film in the PMOS transistor region, and also as the channel layer in the NMOS transistor region, to provide a method for manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure that can solve the above problems. The purpose is.
도 1은 CMOS 회로에서 일반적으로 사용되는 PMOS 트랜지스터와 NMOS 트랜지스터가 형성된 상태의 단면도이다.1 is a cross-sectional view of a state in which a PMOS transistor and an NMOS transistor generally used in a CMOS circuit are formed.
도 2a 내지 도 2g는 본 발명에 따른 이종접합 구조를 갖는 반도체 소자의 시모스 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도이다.2A to 2G are cross-sectional views of devices for describing a method of manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 21 : 반도체 기판22 : 제1 SiGe층11 and 21: semiconductor substrate 22: first SiGe layer
12, 24 : 소자 분리막13a, 23a : p웰12, 24: device isolation layer 13a, 23a: p well
13b, 23b ; n웰14, 28 : 게이트 산화막13b, 23b; n well 14, 28: gate oxide film
25 : 성장 방지막26 : 제2 SiGe층25 growth preventing film 26 second SiGe layer
27 : 실리콘층15, 29 : 게이트 전극27 silicon layer 15, 29 gate electrode
16, 31 : 게이트 스페이서30a : 저농도 이온주입층16, 31: gate spacer 30a: low concentration ion implantation layer
30b : 고농도 이온주입층17a, 17b, 30 : 소오스/드레인30b: high concentration ion implantation layer 17a, 17b, 30: source / drain
18, 32 : 실리사이드층110, 210 : NMOS 트랜지스터18, 32: silicide layer 110, 210: NMOS transistor
120, 220 : PMOS 트랜지스터120, 220: PMOS transistor
본 발명에 따른 이종접합 구조를 갖는 반도체 소자의 시모스 트랜지스터 제조 방법은 실리콘 기판 상에 제1 SiGe층을 형성하는 단계와, 제1 SiGe층에 p웰, n웰 및 소자 분리막을 형성하는 단계와, n웰 상부에 제2 SiGe층을 형성하는 단계와, 제2 SiGe층 및 p웰 상에 실리콘층을 형성하는 단계와, 열산화 공정으로 실리콘층의 상부를 소정의 두께만큼 산화시켜 게이트 산화막을 형성하는 단계와, n웰 및 p웰 상에 게이트 전극, 게이트 스페이서, 소오스/드레인 및 실리사이드층을 형성하는 단계로 이루어진 것을 특징으로 한다.The method for manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure according to the present invention includes the steps of forming a first SiGe layer on a silicon substrate, forming a p well, an n well, and an isolation layer on the first SiGe layer; forming a second oxide layer on the n well, forming a silicon layer on the second SiGe layer and the p well, and oxidizing the upper portion of the silicon layer by a predetermined thickness to form a gate oxide layer. And forming a gate electrode, a gate spacer, a source / drain, and a silicide layer on the n well and the p well.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 보다 더 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 2a 내지 도 2g는 본 발명에 따른 이종접합 구조를 갖는 반도체 소자의 시모스 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도이다.2A to 2G are cross-sectional views of devices for describing a method of manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure according to the present invention.
도 2a를 참조하면, 실리콘 기판(21) 상에 응력이 완화되도록 고온에서 RPCVD법으로 버퍼층 역할을 하는 제1 SiGe층(22)을 형성한 후, 제1 SiGe층(22)에 p웰(23a), n웰(23b) 및 소자 분리막(24)을 형성하여 소자 형성 영역을 정의한다. 이후, p웰(23a) 영역만을 노출시키는 포토레지스트 패턴(도시되지 않음)을 형성한 후 p웰(23a) 상부에 성장 방지막(25)을 형성한다. 성장 방지막(25)은 n웰(23b) 상부에 제2 SiGe층을 성장시키는 후속 공정에서 n웰(23b) 상부에 제2 SiGe층이 성장되는 것을 방지하고, p웰(23a) 상부에서만 제2 SiGe층이 성장되도록 하기 위하여 형성되며, SiNx막으로 형성할 수 있다.Referring to FIG. 2A, after forming a first SiGe layer 22 serving as a buffer layer by RPCVD at a high temperature to relieve stress on the silicon substrate 21, the p well 23a may be formed in the first SiGe layer 22. ), the n well 23b and the device isolation film 24 are formed to define the device formation region. Thereafter, after forming a photoresist pattern (not shown) exposing only the p well 23a region, a growth prevention layer 25 is formed on the p well 23a. The growth prevention layer 25 prevents the growth of the second SiGe layer on the n well 23b in a subsequent process of growing the second SiGe layer on the n well 23b and prevents the growth of the second SiGe layer only on the p well 23a. The SiGe layer is formed to be grown, and may be formed of a SiNx film.
이때, 버퍼층 역할을 하는 제1 SiGe층(22)은 게르마늄 농도가 10% 내지 30%가 되도록 형성하며, 응력이 충분히 완화된 상태로 형성되어야할 뿐만 아니라 표면에서의 결함밀도도 매우 낮아야 하며 웰 드라이브-인(Well drive-in)이나 소자 분리막을 형성한 후에도 안정된 상태를 유지해야만 한다. 한편, 소자 분리막(24)은 LOCOS(Local oxidation isolation) 방식으로 형성하며, 트렌치 공정을 이용한 소자 분리 공정으로도 형성할 수 있다. 실제로, 소자 분리막(24)을 습식 산화 공정(Wet oxidation)으로 형성할 경우, SiGe은 Si보다 산화막 성장속도가 수배이상 빠르므로 산화막 성장시간을 상당히 줄일 수 있다.In this case, the first SiGe layer 22 serving as the buffer layer is formed to have a germanium concentration of 10% to 30%, and the stress must be sufficiently relaxed, and the density of defects on the surface must be very low. A stable state must be maintained even after forming a well drive-in or device isolation layer. On the other hand, the device isolation layer 24 is formed by a local oxidation isolation (LOCOS) method, it may be formed by a device isolation process using a trench process. In fact, when the device isolation film 24 is formed by wet oxidation, SiGe can significantly reduce the oxide film growth time since the oxide film growth rate is several times faster than Si.
도 2b를 참조하면, 선택적 에피성장법(Selective Epitaxial Growth; SEG)으로 n웰(23b) 상부에 PMOS 트랜지스터의 채널층이 될 제2 SiGe층(26)을 형성한다.Referring to FIG. 2B, a second SiGe layer 26 to be a channel layer of the PMOS transistor is formed on the n well 23b by the selective epitaxial growth (SEG).
SiGe으로 이루어진 이종접합 구조를 갖는 반도체 소자의 제조 공정의 핵심은 채널층 에피성장이다. 즉, 일반적인 실리콘 구조의 CMOS 트랜지스터와는 달리 NMOS 트랜지스터와 PMOS 트랜지스터의 채널층 구조가 다르므로, 좀더 복잡한 공정이 요구된다. PMOS 트랜지스터의 경우에는 밸런스 밴드(Valence band)의 오프셋(Offset)을 위해 기판보다 Ge 조성이 높은 SiGe 에피층의 증착이 필요하며, NMOS 트랜지스터의 경우에는 반대로 기판보다 Ge조성이 낮은 SiGe 에피층이나 순수한 Si층의 증착이 요구된다.The core of the manufacturing process of a semiconductor device having a heterojunction structure composed of SiGe is channel layer epitaxial growth. That is, the channel layer structure of the NMOS transistor and the PMOS transistor is different from that of the CMOS transistor of the general silicon structure, and thus a more complicated process is required. In case of PMOS transistor, deposition of SiGe epi layer with Ge composition higher than that of substrate is required for offset of balance band, whereas in case of NMOS transistor, SiGe epi layer or lower pure Ge composition than substrate is required. Deposition of the Si layer is required.
따라서, 제2 SiGe층(26)은 게르마늄 농도가 버퍼층인 제1 SiGe층(22)보다 30% 내지 50%가 되도록 형성하며, 게르마늄 농도에 따라 밸런스 밴드(Valence band)에 양자우물이 형성된다. 이로 인하여, n웰(23b) 상에 형성될 PMOS 트랜지스터의 캐리어인 정공이 이 양자우물을 통하여 흐르게 될 때 비로소 정공은 높은 이동도를 갖게되고, PMOS 트랜지스터는 초고속의 동작 특성을 갖게된다.Accordingly, the second SiGe layer 26 is formed to have a germanium concentration of 30% to 50% of the first SiGe layer 22 as a buffer layer, and a quantum well is formed in a balance band according to the germanium concentration. As a result, when holes, which are carriers of the PMOS transistors to be formed on the n well 23b, flow through the quantum wells, the holes have high mobility, and the PMOS transistors have ultrafast operating characteristics.
또한, 한편, 웰 형성 공정과 LOCOS 공정 이후에 제2 SiGe층(26)을 선택적 에피성장법으로 형성하면 채널층의 응력완화를 막아줄 수 있고, 채널층 형성 시 선택적 에피성장법을 적용하면 소자 분리막(24) 상부에는 SiGe층이 성장되지 않으므로 소자 분리막(22) 상부의 SiGe층을 제거할 필요가 없게되어 공정을 단순화할 수 있다.In addition, if the second SiGe layer 26 is formed by selective epitaxial growth after the well forming process and the LOCOS process, stress relaxation of the channel layer can be prevented, and when the epitaxial epitaxial growth method is applied when forming the channel layer, Since the SiGe layer is not grown on the separator 24, there is no need to remove the SiGe layer on the device separator 22, thereby simplifying the process.
도 2c를 참조하면, p웰(23a) 상부의 성장 방지막(25)을 제거한 후, n웰(23b)에 형성된 제2 SiGe층(26) 및 p웰(23a) 상부에 실리콘층(27)을 형성한다.Referring to FIG. 2C, after removing the growth prevention layer 25 on the p well 23a, the silicon layer 27 is disposed on the second SiGe layer 26 and the p well 23a formed on the n well 23b. Form.
PMOS 트랜지스터의 경우 우수한 막질의 게이트 산화막을 형성하기 위해서는 게이트 산화막을 실리콘층상에 형성하여야 한다. 따라서, 게이트 산화막을 형성하기 전 최상부층은 순수한 실리콘층이어야 한다.In the case of a PMOS transistor, in order to form a gate oxide film of excellent film quality, a gate oxide film must be formed on the silicon layer. Therefore, the top layer must be a pure silicon layer before forming the gate oxide film.
실리콘층(27)은 50 내지 200Å의 두께로 형성하며, 선택적 에피성장법으로 형성하여 공정을 단순화할 수 있다. 이때, p웰(23a)에 형성된 실리콘층(27)은 p웰(23a)에 제조될 NMOS 트랜지스터의 채널층 역할을 하며, n웰(23b) 상부의 제2 SiGe층(26) 상부에 형성된 실리콘층(27)은 게이트 산화막을 형성하기 위한 희생 실리콘층의 역할을 한다. 이때 각층의 두께는 50 내지 200Å 정도로 소자 분리막(24)보다 충분히 얇으므로 소자격리에는 문제가 없다.The silicon layer 27 is formed to a thickness of 50 to 200Å, it can be formed by the selective epitaxial growth method to simplify the process. At this time, the silicon layer 27 formed in the p well 23a serves as a channel layer of the NMOS transistor to be manufactured in the p well 23a, and the silicon formed on the second SiGe layer 26 on the n well 23b. The layer 27 serves as a sacrificial silicon layer for forming a gate oxide film. At this time, since the thickness of each layer is sufficiently thinner than the device isolation layer 24 at about 50 to 200Å, there is no problem in device isolation.
상기에서, p웰(23a)에 형성된 실리콘층(27)은 응력에 의해 전도대역의 분리(Offset)를 유발하여 전자의 이동도를 높여주는데 기여하게 된다. 즉, PMOS 트랜지스터는 n웰(23b) 상에 형성된 제2 SiGe층(26)을 채널층으로 사용하고, NMOS 트랜지스터는 p웰(23a) 상에 형성된 실리콘층(27)을 채널층으로 사용하여 동일한 실리콘 기판(21) 상에 제조된다. 따라서, 버퍼층으로써 기판 역할을 하는 제1 SiGe층(22)의 게르마늄 조성을 기준으로 할 때, PMOS 트랜지스터는 보다 높은 게르마늄 조성을 가진 상태로 제1 SiGe층(22)의 n웰(23b)에 제조되며, NMOS 트랜지스터는 보다 낮은 게르마늄 조성을 가진 상태로 제1 SiGe층(22)의 p웰(23a)에 제조된다.In the above, the silicon layer 27 formed in the p-well 23a causes offset of the conduction band by stress, thereby contributing to increase the mobility of electrons. That is, the PMOS transistor uses the second SiGe layer 26 formed on the n well 23b as the channel layer, and the NMOS transistor uses the silicon layer 27 formed on the p well 23a as the channel layer. It is manufactured on the silicon substrate 21. Therefore, based on the germanium composition of the first SiGe layer 22 serving as a substrate as a buffer layer, the PMOS transistor is manufactured in the n well 23b of the first SiGe layer 22 with a higher germanium composition, The NMOS transistor is fabricated in the p well 23a of the first SiGe layer 22 with a lower germanium composition.
여기서 주의할 점은 실리콘층(27)이 NMOS 트랜지스터의 채널층으로 사용됨과 동시에 PMOS 트랜지스터의 게이트-열산화막을 형성하기 위한 희생 실리콘층으로 사용되므로 두께를 적절하게 조절해야 한다. 즉, n웰(23b) 상부에 실리콘층(27)이 너무 두껍게 형성되면 PMOS 트랜지스터의 게이트 산화막의 두께가 너무 두꺼워져 이득을 감소시키므로 산화막 성장에 필요한 이상의 두께는 바람직하지 않다. 그러나, NMOS 트랜지스터의 경우에는 채널층의 두께가 50Å이상 확보되어야 하므로, p웰(23a) 상부에 형성되는 실리콘층(27)의 두께는 어느 정도 확보되어야 한다.Note that the silicon layer 27 is used as the channel layer of the NMOS transistor and at the same time as the sacrificial silicon layer for forming the gate-thermal oxide film of the PMOS transistor, the thickness must be properly adjusted. That is, if the silicon layer 27 is formed too thick on the n well 23b, the thickness of the gate oxide film of the PMOS transistor becomes too thick, thereby reducing the gain, and thus the thickness more than necessary for the oxide film growth is undesirable. However, in the case of the NMOS transistor, the thickness of the channel layer must be secured to 50 mV or more, and thus the thickness of the silicon layer 27 formed on the p well 23a must be secured to some extent.
도 2d를 참조하면, 열산화 공정으로 실리콘층(27)을 산화시켜 n웰(23b) 및 p웰(23a) 영역 상에 게이트 산화막(28)을 형성한다.Referring to FIG. 2D, the silicon layer 27 is oxidized by a thermal oxidation process to form a gate oxide film 28 on the n well 23b and p well 23a regions.
상기에서, 게이트 산화막(28)을 일반적인 열산화 방법으로 형성함으로써 양산에 손쉽게 적용할 수 있으며, 금속산화막으로 게이트 산화막을 형성해도 무방하다.In the above, the gate oxide film 28 is formed by a general thermal oxidation method, so that it can be easily applied to mass production, and the gate oxide film may be formed of a metal oxide film.
이때, p웰(23a) 영역에서는 실리콘층(27)의 상부가 소정의 두께만큼 산화되면서 실리콘층(27) 상부에 게이트 산화막(28)이 형성되고, 잔류하는 실리콘층(27)은 채널층으로 사용된다. 한편, n웰(23b) 영역에서도 실리콘층(27)의 상부가 소정의 두께만큼 산화되어 실리콘층(27) 상부에 게이트 산화막(28)이 형성되고 게이트 산화막(28)의 하부에는 실리콘층(27)이 잔류되는데, 실리콘층(27)과 제2 SiGe층(26)의 밴드갭 에너지 차이로 인하여 실리콘층(27)에는 채널이 형성되지 않고 제2 SiGe층(26)에 채널이 형성된다. 따라서, n웰(23b) 영역에도 p웰(23a) 영역에서와 같이 게이트 산화막(28) 하부에 실리콘층(27)이 잔류되지만, 채널층은 제2 SiGe층(26)이 된다.In this case, the gate oxide layer 28 is formed on the silicon layer 27 while the upper portion of the silicon layer 27 is oxidized to a predetermined thickness in the p well 23a region, and the remaining silicon layer 27 is a channel layer. Used. Meanwhile, in the n well 23b region, the upper portion of the silicon layer 27 is oxidized to a predetermined thickness so that the gate oxide film 28 is formed on the silicon layer 27, and the silicon layer 27 is disposed below the gate oxide film 28. ) Is left, but due to the difference in the band gap energy between the silicon layer 27 and the second SiGe layer 26, no channel is formed in the silicon layer 27, but a channel is formed in the second SiGe layer 26. Therefore, the silicon layer 27 remains under the gate oxide film 28 in the n well 23b region as in the p well 23a region, but the channel layer becomes the second SiGe layer 26.
도 2e를 참조하면, 전도성 물질을 증착한 후 식각 공정으로 전도성 물질과 게이트 산화막(28)을 패터닝하여 n웰(23b) 및 p웰(23a) 상에 각각 게이트 전극(29)을 형성한다. 이때, 전도성 물질로는 금속 물질을 사용할 수도 있으며, 바람직하게는 폴리실리콘층을 사용한다.Referring to FIG. 2E, after the conductive material is deposited, the gate electrode 29 is formed on the n well 23b and the p well 23a by patterning the conductive material and the gate oxide layer 28 by an etching process. In this case, a metal material may be used as the conductive material, and preferably, a polysilicon layer is used.
도 2f를 참조하면, 저농도 이온주입 공정을 실시하여 게이트 전극 양측에 저농도 이온주입층(30a)을 형성하고, 게이트 전극(29)의 측벽에 게이트 스페이서(31)를 형성한 후 고농도 이온주입 공정을 실시하여 고농도 이온주입층(30b)을 형성한다. 이로써, 게이트 전극(29)의 양측벽에는 게이트 스페이서(31)가 형성되고, 게이트 전극(29)의 양측에는 LDD 구조의 소오스/드레인(30)이 각각 형성된다.Referring to FIG. 2F, the low concentration ion implantation process is performed to form the low concentration ion implantation layer 30a on both sides of the gate electrode, the gate spacer 31 is formed on the sidewall of the gate electrode 29, and the high concentration ion implantation process is performed. The high concentration ion implantation layer 30b is formed. As a result, gate spacers 31 are formed on both side walls of the gate electrode 29, and source / drain 30 having an LDD structure is formed on both sides of the gate electrode 29, respectively.
상기의 저농도 이온주입 공정, 스페이서 형성 공정 및 고농도 이온주입 공정은 실리콘 기판 상에 트랜지스터를 형성할 때 실시되는 공정과 동일한 통상의 공정으로 진행된다.The low concentration ion implantation process, the spacer formation process, and the high concentration ion implantation process proceed in the same general steps as those performed when the transistor is formed on the silicon substrate.
도 2g를 참조하면, 접촉 저항을 낮추기 위하여 게이트 전극(29) 및 소오스/드레인(30) 상에 실리사이드층(32)을 형성한다.Referring to FIG. 2G, the silicide layer 32 is formed on the gate electrode 29 and the source / drain 30 to lower the contact resistance.
이로써, p웰(23a)에는 실리콘층(27)을 채널층으로 하는 NMOS 트랜지스터(210)가 제조되며, n웰(23b)에는 제2 SiGe층(26)을 채널층으로 하는 PMOS 트랜지스터(220)가 제조된다.As a result, an NMOS transistor 210 having a silicon layer 27 as a channel layer is manufactured in the p well 23a, and a PMOS transistor 220 having a second SiGe layer 26 as a channel layer in the n well 23b. Is prepared.
상술한 바와 같이, 본 발명은 일반적으로 실시되는 반도체 제조 공정을 적용하여 SiGe/Si으로 이루어진 이종접합 구조를 갖는 PMOS 트랜지스터와 NMOS 트랜지스터를 동일한 기판 상에 제조한다. 즉, MOSFET 공정의 핵심이라고 할 수 있는 소자격리 및 게이트 산화막 성장과 같은 대부분의 공정을 일반적인 실리콘 구조의 CMOS 트랜지스터 제조 공정으로 실시함으로써, 기존의 CMOS 생산 셋-업(Set-up)을 그대로 사용할 수 있다. 뿐만 아니라, 추가되는 공정은 3회의 에피성장 및 1회의 포토리소그라피(Photo-lithography), 1회의 식각공정에 불과하며, 이 방법을 이용하게 되면 기존의 CMOS 트랜지스터보다 집적밀도와 동작 속도를 수배 향상시킬 수 있다.As described above, the present invention applies a semiconductor manufacturing process, which is generally performed, to manufacture a PMOS transistor and an NMOS transistor having a heterojunction structure composed of SiGe / Si on the same substrate. In other words, most of the processes such as device isolation and gate oxide growth, which are the core of the MOSFET process, can be performed using a conventional silicon transistor CMOS transistor manufacturing process. have. In addition, the additional process is only three epi growths, one photo-lithography, and one etching process, which can improve integration density and operation speed several times over conventional CMOS transistors. Can be.
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