KR20030054683A - A method for forming a transistor of a semiconductor device - Google Patents
A method for forming a transistor of a semiconductor device Download PDFInfo
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- KR20030054683A KR20030054683A KR1020010084896A KR20010084896A KR20030054683A KR 20030054683 A KR20030054683 A KR 20030054683A KR 1020010084896 A KR1020010084896 A KR 1020010084896A KR 20010084896 A KR20010084896 A KR 20010084896A KR 20030054683 A KR20030054683 A KR 20030054683A
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- 238000000034 method Methods 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims description 66
- 238000005468 ion implantation Methods 0.000 claims description 57
- 125000001475 halogen functional group Chemical group 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 239000007943 implant Substances 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 3
- -1 halo ion Chemical class 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 abstract description 7
- 230000001965 increasing effect Effects 0.000 abstract description 3
- 239000002019 doping agent Substances 0.000 abstract 2
- 238000002955 isolation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 트랜지스터 형성 방법에 관한 것으로, 특히 반도체소자의 고집적화에 따라 게이트전극의 측벽에 구비되는 절연막 스페이서의 형성공정없이 트랜지스터를 형성하되, 효과적인 채널 길이 ( effect channel length )를증가시켜 소자의 동작 특성을 향상시킬 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device. In particular, a transistor is formed without forming an insulating layer spacer provided on sidewalls of a gate electrode according to high integration of a semiconductor device, but the effective channel length is increased to increase the device. It is a technique that can improve the operating characteristics.
디램 메모리 소자는 하나의 트랜지스터와 하나의 캐패시터로 단위 셀이 구비된다.The DRAM memory device includes a unit cell with one transistor and one capacitor.
따라서, 트랜지스터의 특성은 소자의 특성을 좌우하는 중요한 요소이다.Therefore, the characteristics of the transistor are important factors that influence the characteristics of the device.
반도체소자가 고집적화됨에 따라 트랜지스터를 집적화시켜 형성하면서 특성을 향상시키고 그에 따른 공정을 단순화시킴으로써 소자의 제조단가를 낮추었다.As semiconductor devices are highly integrated, transistors are integrated and formed to improve characteristics and simplify the process, thereby lowering the manufacturing cost of the devices.
도시되진않았으나, 일반적인 트랜지스터 형성공정을 설명하면 다음과 같다.Although not shown, a general transistor forming process will be described below.
먼저, 반도체기판에 활성영역을 정의하는 소자분리막을 형성한다.First, an isolation layer defining an active region is formed on a semiconductor substrate.
그리고, 상기 활성영역을 포함한 전체표면상부에 게이트산화막을 형성하고, 그 상부에 게이트전극용 도전층, 예를들어 폴리실리콘막을 형성한 다음, 그 상부에 하드마스크층을 형성한다. 이때, 상기 하드마스크층은 산화막이나 질화막으로 형성한다.A gate oxide film is formed over the entire surface including the active region, a conductive layer for the gate electrode, for example, a polysilicon film is formed on the upper surface, and a hard mask layer is formed thereon. In this case, the hard mask layer is formed of an oxide film or a nitride film.
그 다음, 게이트전극 마스크를 이용한 사진식각공정으로 상기 하드마스크층, 폴리실리콘막 및 게이트산화막을 식각하여 게이트전극을 형성한다.Next, the hard mask layer, the polysilicon layer, and the gate oxide layer are etched by a photolithography process using a gate electrode mask to form a gate electrode.
그리고, 상기 게이트전극을 마스크로 하여 상기 반도체기판에 저농도의 불순물을 주입하여 저농도의 불순물 접합영역을 형성한다.A low concentration of impurity junction regions are formed by implanting low concentrations of impurities into the semiconductor substrate using the gate electrode as a mask.
그리고, 상기 게이트전극 측벽에 질화막으로 절연막 스페이서를 형성하고 상기 게이트전극과 절연막 스페이서를 마스크로 하여 상기 반도체기판에 고농도의 불순물을 이온주입하여 고농도의 불순물 접합영역을 형성함으로써 LDD 구조를 트랜지스터를 형성한다.An LDD structure is formed by forming an insulating film spacer on the sidewall of the gate electrode using a nitride film and implanting a high concentration of impurities into the semiconductor substrate using the gate electrode and the insulating film spacer as a mask to form a high concentration impurity junction region. .
상기한 바와같이 종래기술에 따른 반도체소자의 트랜지스터 형성방법은, 공정이 복잡하고 그에 따른 생산단가도 높아 반도체소자의 수율 및 생산성을 저하시키는 문제점이 있다.As described above, the method of forming a transistor of a semiconductor device according to the prior art has a problem in that the process is complicated and the production cost is high, thereby lowering the yield and productivity of the semiconductor device.
본 발명은 이러한 종래기술의 문제점을 해결하기 위하여, 스페이서 형성공정없이 버퍼절연막을 게이트전극 및 반도체기판에 표면에 형성하고 경사입사함으로써 소자의 특성을 향상시키며 공정을 단순화시켜 소자의 생산성 및 수율을 향상시키는 반도체소자의 트랜지스터 형성 방법을 제공하는 것을 그 목적으로 한다.In order to solve the problems of the prior art, a buffer insulating film is formed on a surface of a gate electrode and a semiconductor substrate and is inclinedly incident on the surface without a spacer forming process, thereby improving device characteristics and simplifying processes, thereby improving device productivity and yield. It is an object of the present invention to provide a method for forming a transistor of a semiconductor device.
도 1a 내지 도 1e 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성 방법을 도시한 단면도.1A to 1E are cross-sectional views illustrating a transistor forming method of a semiconductor device in accordance with an embodiment of the present invention.
도 2 내지 도 5 는 본 발명과 종래기술에 의해 형성된 트랜지스터의 특성 차이를 도시한 그래프도.2 to 5 are graphs showing the difference in characteristics of transistors formed by the present invention and the prior art;
< 도면의 주요부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>
11 : 반도체기판13 : 소자분리막11: semiconductor substrate 13: device isolation film
15 : 웰 임플란트 17 : 게이트산화막15 well implant 17 gate oxide film
19 : 폴리실리콘막21 : 하드마스크층19 polysilicon film 21 hard mask layer
23 : 버퍼절연막25 : 불순물 접합영역 임플란트23 buffer insulating film 25 impurity junction region implant
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은,In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,
반도체기판 상에 게이트전극을 형성하는 공정과,Forming a gate electrode on the semiconductor substrate;
상기 게이트전극을 포함한 전체표면상부에 버퍼절연막을 형성하는 공정과,Forming a buffer insulating film over the entire surface including the gate electrode;
상기 반도체기판에 고농도 및 저농도의 불순물을 이온주입하되, 회전시키며 경사주입하여 LDD 구조의 트랜지스터를 형성하는 공정을 포함하는 것과,Implanting impurities of high concentration and low concentration into the semiconductor substrate, rotating and incliningly implanting the transistor to form an LDD structure transistor;
상기 버퍼절연막은 산화막이나 질화막을 50 ∼ 500 Å 두께로 형성하는 것과,The buffer insulating film is formed by forming an oxide film or a nitride film with a thickness of 50 to 500 GPa,
상기 고농도의 불순물 이온주입공정은 1 ∼ 50 KeV 의 이온주입에너지로 As 불순물을 1E15 / ㎠ 이상의 도즈량 만큼 고농도로 주입하되, 0 ∼ 30°의 경사로 90°씩 4의 배수만큼 회전시키며 실시하는 것과,The high concentration impurity ion implantation process is carried out by injecting As impurities at a high concentration of 1E15 / cm 2 or more with an ion implantation energy of 1 to 50 KeV, and rotating them by multiples of 4 at 90 ° with a gradient of 0 to 30 °. ,
상기 저농도의 불순물 이온주입공정은 10 ∼ 100 KeV 의 이온주입에너지로 P 불순물을 5E13 / ㎠ 이하의 도즈량 만큼 저농도로 이온주입하되, 0 ∼ 30°의 경사로 90°씩 4의 배수만큼 회전시키며 실시하는 것을 제1특징으로 한다.The low concentration impurity ion implantation process is performed by ion implantation of P impurity at a low concentration of 5E13 / cm 2 or less with ion implantation energy of 10 to 100 KeV, while rotating by multiples of 4 at 90 ° with a gradient of 0 to 30 °. Let it be a 1st characteristic to do.
또한, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은,In addition, in order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,
반도체기판 상에 게이트전극을 형성하는 공정과,Forming a gate electrode on the semiconductor substrate;
상기 게이트전극을 포함한 전체표면상부에 버퍼절연막을 형성하는 공정과,Forming a buffer insulating film over the entire surface including the gate electrode;
상기 반도체기판에 고농도, 중(中)농도 및 저농도의 불순물을 이온주입하되, 회전시키며 경사주입하여 LDD 구조의 트랜지스터를 형성하는 공정을 포함하는 것과,A step of forming an LDD structure transistor by ion implanting, rotating and obliquely implanting impurities of high concentration, medium concentration and low concentration into the semiconductor substrate;
상기 버퍼절연막은 산화막이나 질화막을 50 ∼ 500 Å 두께로 형성하는 것과,The buffer insulating film is formed by forming an oxide film or a nitride film with a thickness of 50 to 500 GPa,
상기 고농도의 불순물 이온주입공정은 1 ∼ 50 KeV 의 이온주입에너지로 As 불순물을 1E15 / ㎠ 이상의 도즈량 만큼 고농도로 주입하되, 0 ∼ 30°의 경사로 90°씩 4의 배수만큼 회전시키며 실시하는 것과,The high concentration impurity ion implantation process is carried out by injecting As impurities at a high concentration of 1E15 / cm 2 or more with an ion implantation energy of 1 to 50 KeV, and rotating them by multiples of 4 at 90 ° with a gradient of 0 to 30 °. ,
상기 중농도의 불순물 이온주입공정은 1 ∼ 60 KeV 의 이온주입에너지로 As 불순물을 5E13 ∼ 3E14 / ㎠ 의 도즈량 만큼 중(中)농도로 주입하되, 0 ∼ 30°의 경사로 90°씩 4의 배수만큼 회전시키며 실시하는 것과,In the medium concentration impurity ion implantation process, as impurities are injected at a medium concentration by 5E13 to 3E14 / cm 2, with an ion implantation energy of 1 to 60 KeV, and each of 4 at 90 ° with a gradient of 0 to 30 °. To rotate by multiples,
상기 저농도의 불순물 이온주입공정은 10 ∼ 100 KeV 의 이온주입에너지로 P 불순물을 5E13 / ㎠ 이하의 도즈량 만큼 저농도로 이온주입하되, 0 ∼ 30°의 경사로 90°씩 4의 배수만큼 회전시키며 실시하는 것과,The low concentration impurity ion implantation process is performed by ion implantation of P impurity at a low concentration of 5E13 / cm 2 or less with ion implantation energy of 10 to 100 KeV, while rotating by multiples of 4 at 90 ° with a gradient of 0 to 30 °. To do that,
상기 저농도의 불순물 이온주입공정 후 20 ∼ 50 KeV 의 이온주입에너지로 B 불순물을 5E13 / ㎠ 이하의 도즈량 만큼 할로 주입 ( halo implant ) 하여 저농도의 피형 불순물 접합영역(도시안됨)을 형성하되, 10 ∼ 45°의 경사로 90°씩 4의 배수만큼 회전시키며 할로 주입 공정을 실시하는 것을 제2특징으로 한다.After the low concentration impurity ion implantation process, halo implant of B impurity by the dose amount of 5E13 / cm 2 or less is performed using ion implantation energy of 20-50 KeV to form a low concentration impurity junction region (not shown). A second feature is to perform a halo injection step while rotating by a multiple of 4 at 90 ° with a slope of 45 °.
그리고, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은,In order to achieve the above object, the transistor forming method of a semiconductor device according to the present invention,
반도체기판 상에 게이트전극을 형성하는 공정과,Forming a gate electrode on the semiconductor substrate;
상기 게이트전극을 포함한 전체표면상부에 버퍼절연막을 형성하는 공정과,Forming a buffer insulating film over the entire surface including the gate electrode;
상기 반도체기판에 고농도의 불순물 이온주입, 할로 이온주입 및 저농도의 불순물 이온주입 공정을 실시하되, 회전시키며 경사주입하여 LDD 구조의 트랜지스터를 형성하는 공정을 포함하는 것과,Performing a high concentration of impurity ion implantation, a halo ion implantation, and a low concentration of impurity ion implantation on the semiconductor substrate, and rotating and incliningly implanting the transistor to form an LDD structure transistor;
상기 버퍼절연막은 산화막이나 질화막을 50 ∼ 500 Å 두께로 형성하는 것과,The buffer insulating film is formed by forming an oxide film or a nitride film with a thickness of 50 to 500 GPa,
상기 고농도의 불순물 이온주입공정은 1 ∼ 50 KeV 의 이온주입에너지로 As 불순물을 1E15 / ㎠ 이상의 도즈량 만큼 고농도로 주입하되, 0 ∼ 30°의 경사로 90°씩 4의 배수만큼 회전시키며 실시하는 것과,The high concentration impurity ion implantation process is carried out by injecting As impurities at a high concentration of 1E15 / cm 2 or more with an ion implantation energy of 1 to 50 KeV, and rotating them by multiples of 4 at 90 ° with a gradient of 0 to 30 °. ,
상기 할로 이온 주입공정은, 20 ∼ 50 KeV 의 이온주입에너지로 B 불순물을 5E13 / ㎠ 이하의 도즈량 만큼 할로 주입 ( halo implant ) 하여 저농도의 피형 불순물 접합영역(도시안됨)을 형성하되, 10 ∼ 45°의 경사로 90°씩 4의 배수만큼회전시키며 실시하는 것과,In the halo ion implantation process, a low concentration of the impurity junction region (not shown) is formed by halo implanting B impurities with a dose of 5E13 / cm 2 or less at a ion implantation energy of 20 to 50 KeV. With a 45 ° incline, rotated in multiples of 4 by 90 °,
상기 저농도의 불순물 이온주입공정은 10 ∼ 100 KeV 의 이온주입에너지로 P 불순물을 5E13 / ㎠ 이하의 도즈량 만큼 저농도로 이온주입하되, 0 ∼ 30°의 경사로 90°씩 4의 배수만큼 회전시키며 실시하는 것과,The low concentration impurity ion implantation process is performed by ion implantation of P impurity at a low concentration of 5E13 / cm 2 or less with ion implantation energy of 10 to 100 KeV, while rotating by multiples of 4 at 90 ° with a gradient of 0 to 30 °. To do that,
상기 저농도의 불순물 이온주입 공정후 1 ∼ 60 KeV 의 이온주입에너지로 As 불순물을 5E13 ∼ 3E14 / ㎠ 의 도즈량 만큼 중(中)농도로 주입하되, 0 ∼ 30°의 경사로 90°씩 4의 배수만큼 회전시키며 실시하는 것을 제3특징으로 한다.After the low concentration impurity ion implantation process, as impurities are injected at a medium concentration by a dose amount of 5E13 to 3E14 / cm 2 with an ion implantation energy of 1 to 60 KeV, and drained 4 by 90 ° at a slope of 0 to 30 °. The third feature is to carry out by rotating as much as possible.
한편, 본 발명의 원리는,On the other hand, the principle of the present invention,
절연막 스페이서 형성공정 없이 게이트전극을 포함한 전체표면상부에 버퍼절연막을 형성하고 마스크 없이 고농도의 불순물과 저농도의 불순물을 순차적으로 주입하여 트랜지스터를 형성함으로써 공정을 단순화시키고 특성을 향상시켜 소자의 생산성 및 수율을 향상시키는 것이다.A buffer insulating film is formed on the entire surface including the gate electrode without an insulating film spacer forming process, and a transistor is formed by sequentially injecting a high concentration of impurities and a low concentration of impurities without a mask to simplify the process and improve characteristics, thereby improving device productivity and yield. To improve.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성 방법을 도시한 단면도로서, CMOS 의 NMOS 트랜지스터를 예로들어 형성한 것이다.1A to 1F are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to an embodiment of the present invention, and are formed by taking an NMOS transistor of CMOS as an example.
도 1a를 참조하면, 반도체기판(11) 상에 패드산화막(도시안됨) 및 패드질화막(도시안됨)의 적층구조로 구비되는 패드절연막을 형성한다.Referring to FIG. 1A, a pad insulating layer having a stacked structure of a pad oxide film (not shown) and a pad nitride film (not shown) is formed on a semiconductor substrate 11.
그리고, 소자분리마스크(도시안됨)를 이용한 사진식각공정으로 상기 패드절연막 및 일정두께의 반도체기판(11)을 식각하여 트렌치를 형성한다.A trench is formed by etching the pad insulating layer and the semiconductor substrate 11 having a predetermined thickness by a photolithography process using a device isolation mask (not shown).
상기 트렌치를 매립하는 소자분리막(13)을 형성한다.An isolation layer 13 may be formed to fill the trench.
도 1b를 참조하면, 상기 반도체기판(11)에 웰 형성용 임플란트 공정을 실시한다.Referring to FIG. 1B, a well forming implant process is performed on the semiconductor substrate 11.
도 1c를 참조하면, 상기 반도체기판(11)의 활성영역에 게이트산화막(17), 게이트전극용 폴리실리콘막(19) 및 하드마스크층(21)을 순차적으로 적층하여 형성한다.Referring to FIG. 1C, a gate oxide film 17, a gate silicon polysilicon film 19, and a hard mask layer 21 are sequentially stacked in an active region of the semiconductor substrate 11.
이때, 상기 하드마스크층(21)은 산화막이나 질화막으로 형성한다.In this case, the hard mask layer 21 is formed of an oxide film or a nitride film.
그 다음, 게이트전극 마스크(도시안됨)를 이용한 사진식각공정으로 상기 적층구조를 식각하여 게이트전극을 형성한다.Next, the stacked structure is etched by a photolithography process using a gate electrode mask (not shown) to form a gate electrode.
도 1d를 참조하면, 상기 게이트전극(17,19,21)을 포함한 전체표면상부에 버퍼절연막(23)을 일정두께 형성한다.Referring to FIG. 1D, a buffer insulating film 23 is formed on the entire surface including the gate electrodes 17, 19, and 21.
이때, 상기 버퍼절연막은 산화막이나 질화막을 50 ∼ 500 Å 두께로 형성한다.In this case, the buffer insulating film is formed to an oxide film or a nitride film 50 to 500 Å thickness.
도 1e를 참조하면, 상기 반도체기판(11)의 활성영역에 1 ∼ 50 KeV 의 이온주입에너지로 As 불순물을 1E15 / ㎠ 이상의 도즈량 만큼 고농도로 주입하여 고농도의 엔형 불순물 접합영역(도시안됨)을 형성하되, 상기 이온주입공정은 0 ∼ 30°의 경사로 90°씩 회전시키면서 실시한다.Referring to FIG. 1E, a high concentration of Y-type impurity junction region (not shown) is injected into the active region of the semiconductor substrate 11 at a high concentration by 1 to 15 KeV of ion implantation energy at a dose of 1E15 / cm 2 or more. The ion implantation step is carried out while being rotated by 90 ° at an inclination of 0 to 30 °.
그리고, 상기 활성영역에 1 ∼ 60 KeV 의 이온주입에너지로 As 불순물을 5E13 ∼ 3E14 / ㎠ 의 도즈량 만큼 중(中)농도로 주입하여 중(中)농도의 불순물 엔형 접합영역(도시안됨)을 형성하되, 상기 이온주입공정은 0 ∼ 30°의 경사로 90°씩 회전시키면서 실시한다. 여기서, 상기 중(中)농도는 상기 고농도와 저농도의 중간 정도를 말하는 것이다.In addition, as impurities are injected into the active region at a concentration of 5E13 to 3E14 / cm 2 with an ion implantation energy of 1 to 60 KeV, an impurity en-type junction region (not shown) of medium concentration is shown. The ion implantation step is carried out while being rotated by 90 ° at an inclination of 0 to 30 °. Here, the medium concentration refers to a middle level between the high concentration and the low concentration.
그리고, 상기 활성영역에 10 ∼ 100 KeV 의 이온주입에너지로 P 불순물을 5E13 / ㎠ 이하의 도즈량 만큼 저농도로 할로 주입 ( halo implant ) 하여 저농도의 엔형 불순물 접합영역(도시안됨)을 형성하되, 상기 이온주입공정은 0 ∼ 30°의 경사로 90°씩 회전시키면서 실시한다.In addition, a low concentration of Y-type impurity junction region (not shown) is formed by halo implanting P impurities at a low concentration by a dose of 5E13 / cm 2 or less with ion implantation energy of 10 to 100 KeV in the active region. The ion implantation step is performed while rotating at 90 ° with an inclination of 0 to 30 °.
그 다음, 상기 활성영역에 20 ∼ 50 KeV 의 이온주입에너지로 B 불순물을 5E13 / ㎠ 이하의 도즈량 만큼 저농도로 주입하여 저농도의 피형 불순물 접합영역(도시안됨)을 형성하되, 상기 이온주입공정은 10 ∼ 45°의 경사로 90°씩 회전시키면서 실시함으로써 트랜지스터를 형성한다.Then, B impurities are injected into the active region at a low concentration of 5E13 / cm 2 or less with an ion implantation energy of 20 to 50 KeV to form a low concentration of the impurity junction region (not shown). The transistor is formed by rotating in 90 ° increments at an inclination of 10 to 45 °.
여기서, "25" 는 불순물의 임플란트, 즉 이온주입을 도시한다.Here, "25" shows an implant of impurities, i.e., ion implantation.
도 2 내지 도 5 는 본 발명에 따라 형성된 트랜지스터의 특성과 종래기술에 따른 트랜지스터의 특성 변화를 도시한 시뮬레이션을 도시한 그래프도로서, 도 2 및 도 3 은 콘스턴스 커랜트 방법 ( constant current method ) 방법을 이용하여 도시한 것이고 도 4 는 GM 방법을 이용하여 도시한 것이다.2 to 5 are graphs showing simulations showing characteristics of transistors formed in accordance with the present invention and characteristics of transistors according to the prior art, and FIGS. 2 and 3 are a constant current method. It is shown using the method and FIG. 4 is shown using the GM method.
도 2 및 도 4 는 드레인 전압이 1.8 V 일 때, 드레인 전류가 5 ㎁ 로 될 때의 종래기술과 본 발명에 따른 게이트전극 전압의 변화를 채널 길이에 따라 도시한 것이다.2 and 4 show the change in the gate electrode voltage according to the prior art and the present invention according to the channel length when the drain current becomes 5 때 when the drain voltage is 1.8 V. FIG.
도 3 은 드레인 전압과 게이트전극 전압이 1.8 V 일 때, 종래기술과 본 발명에 따른 드레인의 전류 변화를 채널 길이에 따라 도시한 것이다.Figure 3 shows the current change of the drain according to the prior art and the present invention according to the channel length when the drain voltage and the gate electrode voltage is 1.8V.
도 5 는 채널길이에 따른 효과적인 채널 길이 변화를 종래기술과 본 발명으로 대비하여 도시한 것이다.Figure 5 shows the effective channel length change according to the channel length in contrast to the prior art and the present invention.
본 발명의 다른 실시예는 상기 도 1f 의 공정 중에서 중(中)농도의 불순물 접합영역 형성공정과 할로 주입공정을 생략하거나, 이들 중 한가지만을 생략하거나, 이들의 공정 순서를 바꾸던가, 바꿔진 이들중 한가지만을 생략하여 실시하는 것이다.According to another embodiment of the present invention, the intermediate concentration impurity junction region forming process and halo implantation process may be omitted in the process of FIG. 1F, or only one of them may be omitted, or the order of these processes may be changed or changed. Only one is omitted.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 트랜지스터 형성방법은, 스페이서의 형성공정없이 LDD 구조를 갖는 트랜지스터를 용이하게 형성하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, the method for forming a transistor of a semiconductor device according to the present invention can easily form a transistor having an LDD structure without forming a spacer, thereby improving the characteristics and reliability of the semiconductor device and thereby increasing the integration of the semiconductor device. To provide the effect.
Claims (16)
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|---|---|---|---|---|
| JPH06163572A (en) * | 1992-11-26 | 1994-06-10 | Sanyo Electric Co Ltd | Manufacture of mos field effect transistor |
| KR960002898A (en) * | 1994-06-27 | 1996-01-26 | 김주용 | Transistor of semiconductor device and forming method thereof |
| JPH0832080A (en) * | 1994-07-14 | 1996-02-02 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
| KR970003837A (en) * | 1995-06-16 | 1997-01-29 | 김주용 | Tungsten Metal Wiring Formation Method |
| KR0151194B1 (en) * | 1994-11-23 | 1998-10-01 | 문정환 | Thin film transistor |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06163572A (en) * | 1992-11-26 | 1994-06-10 | Sanyo Electric Co Ltd | Manufacture of mos field effect transistor |
| KR960002898A (en) * | 1994-06-27 | 1996-01-26 | 김주용 | Transistor of semiconductor device and forming method thereof |
| JPH0832080A (en) * | 1994-07-14 | 1996-02-02 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
| KR0151194B1 (en) * | 1994-11-23 | 1998-10-01 | 문정환 | Thin film transistor |
| KR970003837A (en) * | 1995-06-16 | 1997-01-29 | 김주용 | Tungsten Metal Wiring Formation Method |
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