KR20030050597A - Method for forming contact in semiconductor device - Google Patents
Method for forming contact in semiconductor device Download PDFInfo
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- KR20030050597A KR20030050597A KR1020010081081A KR20010081081A KR20030050597A KR 20030050597 A KR20030050597 A KR 20030050597A KR 1020010081081 A KR1020010081081 A KR 1020010081081A KR 20010081081 A KR20010081081 A KR 20010081081A KR 20030050597 A KR20030050597 A KR 20030050597A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 박막의 선택적 성장 방법을 이용한 콘택(Contact) 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact using a method of selectively growing thin films.
최근에 0.16㎛급 초고집적소자의 미세 콘택 형성 공정에서 마스크 공정의 오정렬 여유도를 개선하기 위하여 질화막(Nitride)을 배리어막으로 한 자기정렬콘택(Nitride barrier Self Aligned Contact; NBSAC) 공정이 주로 이용되고 있다.Recently, in order to improve the misalignment margin of the mask process in the fine contact formation process of the 0.16㎛ class ultra-high integration device, a Nitride barrier Self Aligned Contact (NBSAC) process using a nitride film as a barrier is mainly used. have.
그러나, 자기정렬콘택(NBSAC) 공정은 산화막 식각시 질화막에 대한 고선택비, 즉 질화막에 대한 손실을 최소화 하기 위해 다량의 카본폴리머(Carbon polymer)를 발생시키는 C4F8계 플라즈마를 식각가스로 사용한다. 이러한 카본폴리머는 후속 세정 공정에서 완전히 제거되지 않고 레시듀(Residues)로 남아 높은 콘택저항을 유발하는 문제가 있다.However, the self-aligned contact (NBSAC) process uses a C 4 F 8 -based plasma, which generates a large amount of carbon polymer, to minimize the high selectivity for the nitride film, that is, the loss of the nitride film. use. These carbon polymers are not completely removed in a subsequent cleaning process and remain as residues, causing a high contact resistance.
이러한 문제를 해결하기 위해 폴리실리콘플러그를 화학기상증착(CVD) 방식이 아닌 선택적 에피택셜 성장(Selective Epitaxial Growth; SEG) 방식을 이용하여 미세 배선의 전기적인 저항을 낮게 조절하는 방법이 제안되었다(도 1 참조).In order to solve this problem, a method of controlling the electrical resistance of the microwires by using a selective epitaxial growth (SEG) method instead of the chemical vapor deposition (CVD) method has been proposed. 1).
도 1은 종래기술에 따른 선택적 에피택셜 성장법에 의한 콘택 형성 방법을 간략히 도시한 도면이다.1 is a view briefly illustrating a method for forming a contact by a selective epitaxial growth method according to the prior art.
도 1을 참조하면, 반도체기판(11)상에 층간절연막(12)을 형성한 후, 층간절연막상에 콘택마스크(도시 생략)를 형성한다.Referring to FIG. 1, after forming the interlayer insulating film 12 on the semiconductor substrate 11, a contact mask (not shown) is formed on the interlayer insulating film.
다음으로, 콘택마스크에 의해 노출된 층간절연막(12)을 식각하여반도체기판(11)의 소정 표면을 노출시키는 콘택홀을 형성한 후, 콘택홀내 노출된 반도체기판(11) 표면상에 선택적으로 실리콘막(13)을 성장시킨다.Next, the interlayer insulating film 12 exposed by the contact mask is etched to form a contact hole exposing a predetermined surface of the semiconductor substrate 11, and then selectively silicon on the surface of the semiconductor substrate 11 exposed in the contact hole. The film 13 is grown.
그러나, 이 공정은 증착전 콘택홀의 표면 상태에 민감하게 반응하며, 콘택홀내 노출된 반도체기판 표면은 물론 층간절연막상에도 실리콘이 추가로 성장하는 경향이 있어 증착 공정을 미세하게 조절하기 힘들고, 또한 추가 성장된 막을 제거해야하는 후속 식각공정이 필요하므로 그 적용에 문제점이 잇다.However, this process is sensitive to the surface state of the contact hole before deposition, and silicon tends to grow on the interlayer insulating film as well as the exposed semiconductor substrate surface in the contact hole, making it difficult to finely control the deposition process. There is a problem in the application because a subsequent etching process is required to remove the grown film.
이를 해결하기 위해 콘택홀을 형성하기 전에 폴리실리콘콘택패드를 미리 형성하므로써 미세 콘택의 전기적 저항을 낮추는 방법이 제안되었다.In order to solve this problem, a method of lowering the electrical resistance of the fine contact by forming the polysilicon contact pad in advance before forming the contact hole has been proposed.
그러나, 이 방법에서도 마스크 오정렬 여유도에 의한 문제, 폴리머 형성 공정의 어려움, 그리고 미세 콘택 주위로 폴리실리콘 레시듀가 여전히 발생하여 0.16㎛급 이하 반도체소자에는 적용할 수 없는 문제가 있다.However, even in this method, there is a problem due to mask misalignment margin, difficulty in polymer formation process, and polysilicon recipe still occurring around the micro contact, which is not applicable to a semiconductor device of 0.16 탆 or less.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 마스크 오정렬 여유도를 확보하고, 잔류하는 레시듀에 의한 콘택저항의 증가를 방지하며 증착공정을 단순화시키는데 적합한 반도체소자의 콘택 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and provides a method for forming a contact of a semiconductor device suitable for securing a mask misalignment margin, preventing an increase in contact resistance due to residual recipes, and simplifying a deposition process. The purpose is to provide.
도 1은 종래기술의 선택적에피택셜성장법에 의한 콘택을 도시한 도면,1 is a view showing a contact by the selective epitaxial growth method of the prior art,
도 2는 본 발명의 제1실시예에 따른 반도체소자의 콘택 형성 방법을 도시한 공정 흐름도,2 is a process flowchart showing a contact forming method of a semiconductor device according to a first embodiment of the present invention;
도 3a 내지 도 3d는 도 2에 따른 공정 단면도,3a to 3d are cross-sectional views of the process according to FIG.
도 4a 내지 도 4d는 본 발명의 제2실시예에 따른 반도체소자의 콘택 형성 방법을 도시한 공정 단면도.4A to 4D are cross-sectional views illustrating a method for forming a contact for a semiconductor device according to a second exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 층간절연막21 semiconductor substrate 22 interlayer insulating film
24 : 팔라듐 입자 25 : 실리콘막24 palladium particle 25 silicon film
상기의 목적을 달성하기 위한 본 발명의 콘택 형성 방법은 제1도전막 표면을세정하는 단계, 상기 세정된 제1도전막을 금속촉매를 함유한 용액을 이용하여 전처리하는 단계, 상기 전처리된 제1도전막상에 상기 금속촉매의 입자만을 잔류시키는 단계, 상기 금속촉매의 입자상에 무전해도금법을 이용하여 제2도전막을 선택적으로 성장시키는 단계를 포함하여 이루어짐을 특징으로 한다.The contact forming method of the present invention for achieving the above object comprises the steps of cleaning the surface of the first conductive film, pre-treating the cleaned first conductive film using a solution containing a metal catalyst, the first conductive Leaving only the particles of the metal catalyst on the film, and selectively growing the second conductive film on the particles of the metal catalyst by using an electroless plating method.
또한, 본 발명의 콘택 형성 방법은 제1도전막상에 층간절연막을 형성하는 단계, 상기 층간절연막을 관통하여 상기 제1도전막 표면을 노출시키는 콘택홀을 형성하는 단계, 상기 콘택홀이 형성된 상기 제1도전막을 세정하는 단계, 상기 세정된 제1도전막을 팔라듐촉매가 함유된 용액으로 전처리하는 단계, 상기 콘택홀내 노출된 상기 제1도전막 표면에만 상기 팔라듐촉매의 입자를 잔류시키는 단계, 및 상기 팔라듐촉매의 입자상에 무전해도금법으로 제2도전막을 선택적으로 성장시키는 단계를 포함하여 이루어짐을 특징으로 한다.The method of forming a contact may include forming an interlayer insulating film on a first conductive film, forming a contact hole through the interlayer insulating film to expose a surface of the first conductive film, wherein the contact hole is formed. (1) cleaning the conductive film, pretreating the cleaned first conductive film with a solution containing a palladium catalyst, leaving particles of the palladium catalyst only on the exposed surface of the first conductive film in the contact hole, and the palladium And selectively growing the second conductive film on the particles of the catalyst by an electroless plating method.
바람직하게, 상기 금속촉매는 팔라듐(Pd), 금(Au), 은(Ag), 주석(Sn), 니켈(Ni), 철(Fe), 구리(Cu) 및 백금(Pt)중에서 선택된 어느 하나인 것을 특징으로 하고, 상기 제1 및 제2도전막은 실리콘, 구리, 텅스텐, 알루미늄, 탄탈륨, 티타늄, 몰리브데늄, 티타늄나이트라이드, 텅스텐나이트라이드 및 탄탈륨나이트라이드중에서 선택된 하나인 것을 특징으로 한다.Preferably, the metal catalyst is any one selected from palladium (Pd), gold (Au), silver (Ag), tin (Sn), nickel (Ni), iron (Fe), copper (Cu) and platinum (Pt). The first and second conductive films may be one selected from silicon, copper, tungsten, aluminum, tantalum, titanium, molybdenum, titanium nitride, tungsten nitride, and tantalum nitride.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2는 본 발명의 제1실시예에 따른 반도체소자의 콘택 형성 방법을 도시한 공정 흐름도이고, 도 3a 내지 도 3d는 도 2에 따른 각 단계에서의 결과물을 도시하고 있다.FIG. 2 is a process flowchart illustrating a method of forming a contact for a semiconductor device according to a first embodiment of the present invention, and FIGS. 3A to 3D show results at each step according to FIG. 2.
도 2 및 도 3a를 참조하면, 먼저 콘택홀을 형성하는데, 콘택홀 형성 방법은 반도체기판(21)상에 층간절연막(22)을 증착한 후, 층간절연막(22)상에 감광막을 이용한 콘택마스크(도시 생략)를 형성하고, 콘택마스크로 층간절연막(22)을 식각하여 반도체기판(21)의 소정 표면을 노출시키는 콘택홀(23)을 형성한다(S1).Referring to FIGS. 2 and 3A, first, a contact hole is formed. In the contact hole forming method, a contact mask using a photoresist film on the interlayer insulating film 22 is deposited after the interlayer insulating film 22 is deposited on the semiconductor substrate 21. (Not shown), and the interlayer insulating film 22 is etched with a contact mask to form a contact hole 23 exposing a predetermined surface of the semiconductor substrate 21 (S1).
다음으로, 콘택홀(23) 형성시 발생된 오염원(유기물, 금속불순물 및 금속산화물)을 제거함과 동시에 콘택홀(23)내에 노출된 반도체기판(21)에 실리콘막을 균일하게 증착하기 위한 표면을 제공하기 위해 전세정 공정을 진행한다(S2).Next, a surface for uniformly depositing a silicon film on the semiconductor substrate 21 exposed in the contact hole 23 while removing contaminants (organic, metal impurities, and metal oxides) generated when the contact hole 23 is formed. In order to proceed the pre-cleaning process (S2).
여기서, 전세정 공정은, 반도체기판(21) 표면에 형성된 유기물과 금속불순물을 제거하기 위한 제1세정공정과 금속산화물을 제거하기 위한 제2세정공정으로 이루어진다.Here, the pre-cleaning step includes a first washing step for removing organic substances and metal impurities formed on the surface of the semiconductor substrate 21 and a second washing step for removing metal oxides.
먼저 제1세정공정은, 반도체기판(21) 표면에 형성된 유기물과 금속불순물을 제거하기 위해 황산과 과산화수소(H2SO4:H2O2)를 3:1로 혼합하고, 세정시간은 1분∼10분으로 한다.First, in the first cleaning process, sulfuric acid and hydrogen peroxide (H 2 SO 4 : H 2 O 2 ) are mixed at 3: 1 to remove organic substances and metal impurities formed on the surface of the semiconductor substrate 21, and the cleaning time is 1 minute. Let it be 10 minutes.
그리고, 제2세정공정은, 반도체기판(21) 표면에 형성된 금속산화물을 제거하기 위해 불산과 물(HF:H2O)을 1:10으로 혼합하고, 세정시간은 10초∼60초로 진행한다.In the second cleaning step, hydrofluoric acid and water (HF: H 2 O) are mixed at 1:10 to remove metal oxides formed on the surface of the semiconductor substrate 21, and the cleaning time is 10 seconds to 60 seconds. .
다음으로, 도 2 및 도 3b를 참조하면, 상술한 전세정공정이 완료된 후, 선택적으로 실리콘막을 증착하기 전에 전처리 공정을 실시한다(S3).Next, referring to FIG. 2 and FIG. 3B, after the above-described pre-cleaning process is completed, the pre-treatment process is performed before selectively depositing the silicon film (S3).
전처리 공정은, 금속촉매를 이용한 전처리 용액을 이용하는데, 이러한 전처리 용액에 사용되는 금속 촉매는 팔라듐(Pd), 금(Au), 은(Ag), 주석(Sn), 니켈(Ni), 철(Fe), 구리(Cu) 및 백금(Pt)중에서 선택된 어느 하나를 사용한다.The pretreatment process uses a pretreatment solution using a metal catalyst, and the metal catalysts used in the pretreatment solution are palladium (Pd), gold (Au), silver (Ag), tin (Sn), nickel (Ni), iron ( Fe), copper (Cu) and platinum (Pt) are used.
이하, 팔라듐을 금속촉매로 이용한 팔라듐 전처리 공정에 대해서 설명하기로 한다.Hereinafter, a palladium pretreatment process using palladium as a metal catalyst will be described.
먼저 팔라듐을 금속촉매로 이용한 전처리용액은, 팔라듐 클로라이드(PdCl2, 0.01∼0.1g/l), 암모니아(NH4OH, 5∼20ml), 염산(HCl, 1∼20ml), 불산(HF, 1∼10ml)을 혼합하고, 이때 팔라듐 전처리 용액에 표면 산화제로 질산(HNO3, 1∼20ml)과 팔라듐전처리용액의 안정성을 위한 계면활성제로서 폴리에틸렌글리콘 (PolyEethelyeneGlycol; PEG) 또는 트리톤(Triton)을 미량(0.001∼1mol/l) 첨가한다.First, the pretreatment solution using palladium as a metal catalyst is palladium chloride (PdCl 2 , 0.01 to 0.1 g / l), ammonia (NH 4 OH, 5 to 20 ml), hydrochloric acid (HCl, 1 to 20 ml), hydrofluoric acid (HF, 1 10 ml), and a small amount of polyethylene glycol (PolyEethelyeneGlycol (PEG) or Triton) is used as a surfactant for the stability of the nitric acid (HNO 3 , 1-20 ml) and the palladium pretreatment solution as a surface oxidant. (0.001-1 mol / l) is added.
상술한 바와 같은 팔라듐 전처리용액을 이용하는 이유는, 실리콘막이 증착될 반도체기판(21)의 표면에서 자발적인 촉매 활성화 경향을 갖도록 하기 위함이다.The reason for using the palladium pretreatment solution as described above is to have a tendency for spontaneous catalyst activation on the surface of the semiconductor substrate 21 on which the silicon film is to be deposited.
다음으로, 팔라듐 전처리 용액을 이용한 전처리의 공정 온도를 변화시켜 층간절연막(22) 표면과 콘택홀(23)내 반도체기판 표면(21)에서 서로 다른 결합력과 크기를 갖는 전처리 용액내 팔라듐(Pd) 입자(24)만을 성장시킨다.Next, palladium (Pd) particles in the pretreatment solution having different bonding strengths and sizes on the surface of the interlayer insulating film 22 and the semiconductor substrate surface 21 in the contact hole 23 by changing the process temperature of the pretreatment using the palladium pretreatment solution. Only grow (24).
예컨대, 팔라듐 전처리용액의 공정온도를 50℃에서 80℃로 증가시키면,Pd(NH3)2Cl2에서 팔라듐(Pd) 금속 입자만이 층간절연막(22) 및 콘택홀(23)내 반도체기판(21) 표면에만 성장하게 된다. 이때, 증착된 팔라듐(Pd) 입자의 크기는 수십 나노(nano)에서 수백 나노까지를 갖는다.For example, when the process temperature of the palladium pretreatment solution is increased from 50 ° C. to 80 ° C., only the palladium (Pd) metal particles in Pd (NH 3 ) 2 Cl 2 are used in the interlayer insulating film 22 and the contact hole 23. 21) It grows only on the surface. At this time, the deposited palladium (Pd) particles have a size of several tens (nano) to several hundred nano.
이처럼, 팔라듐 전처리용액에 의한 전처리 공정 조건 중에서 온도를 변화시킴으로서 콘택홀(23)내 반도체기판(21) 표면 및 층간절연막(22)의 표면에 증착되는 팔라듐 입자(24)들의 형태가 다르도록 할 수 있다.As such, by changing the temperature in the pretreatment process conditions using the palladium pretreatment solution, the shape of the palladium particles 24 deposited on the surface of the semiconductor substrate 21 and the surface of the interlayer insulating film 22 in the contact hole 23 may be different. have.
만약, 상온에서 팔라듐전처리용액을 이용한 전처리 공정을 진행하였을 경우에는, 팔라듐전처리 용액내에서 콘택홀(23)내 반도체기판(21) 표면에 흡착되어 있는 환원된 팔라듐(Pd) 입자(24)들과 함께 상당량의 팔라듐화합물[Pd(NH3)2Cl2]이 층간절연막(2)의 표면에 존재하게 된다.If the pretreatment process using the palladium pretreatment solution is performed at room temperature, the reduced palladium (Pd) particles 24 adsorbed to the surface of the semiconductor substrate 21 in the contact hole 23 in the palladium pretreatment solution and A considerable amount of palladium compound [Pd (NH 3 ) 2 Cl 2 ] is also present on the surface of the interlayer insulating film 2.
이와 같이 팔라듐 전처리용액의 전처리 공정 온도를 조절하여 Pd(NH3)2Cl2에서 순수한 금속의 팔라듐 입자(24)만을 성장시킬 수 있다.As such, only the palladium particles 24 of pure metal may be grown in Pd (NH 3 ) 2 Cl 2 by adjusting the pretreatment process temperature of the palladium pretreatment solution.
다음으로, 도 2 및 도 3c에 도시된 바와 같이, 콘택홀(23)내 반도체기판(21) 표면에만 팔라듐입자(24)들이 잔류하도록 물(H2O)를 이용한 후세정 공정을 진행한다(S4).Next, as shown in FIGS. 2 and 3C, a post-cleaning process using water (H 2 O) is performed such that the palladium particles 24 remain only on the surface of the semiconductor substrate 21 in the contact hole 23 ( S4).
후세정 공정은 콘택홀(23)내 반도체기판(21) 표면에만 팔라듐 입자(24)들을 잔류시키기 위해서, 팔라듐화합물이 물(H2O)에 쉽게 용해가 되는 특성을 이용한 세정을 실시한다.In the post-cleaning process, the palladium compound 24 is easily dissolved in water (H 2 O) in order to retain the palladium particles 24 only on the surface of the semiconductor substrate 21 in the contact hole 23.
한편, 팔라듐 전처리용액을 이용한 전처리 공정 온도가 80℃까지 상승함에 따라 증착된 팔라듐 입자(24)들의 형태는 유기 화합물 형태가 아닌 주로 순수 금속 팔라듐 상태로 존재한다.Meanwhile, as the pretreatment process temperature using the palladium pretreatment solution rises to 80 ° C., the forms of the deposited palladium particles 24 exist mainly in the form of pure metal palladium rather than an organic compound.
이러한 순수 금속 팔라듐 입자(24)들이 콘택홀(23) 내에서 성장할 경우에는 표면에 흡착력이 매우 강하기 때문에, 후세정 공정시 층간절연막(22) 표면에 형성된 팔라듐입자들은 쉽게 탈착이 되나, 콘택홀(23)내 반도체기판(21) 표면에 성장한 팔라듐입자(24)들은 계속 잔류한다.When the pure metal palladium particles 24 are grown in the contact hole 23, since the adsorption force is very strong on the surface, the palladium particles formed on the surface of the interlayer insulating layer 22 are easily desorbed during the post-cleaning process. The palladium particles 24 grown on the surface of the semiconductor substrate 21 in 23 continue to remain.
즉, 층간절연막(22) 표면에 증착된 팔라듐 입자(24)들은 하이드로다이내믹(Hydro-dynamic)의 힘에 의해서 완전히 제거되지만, 콘택홀(23)내 반도체기판(21) 표면에 증착된 팔라듐 입자(24)들은 고착된 상태를 유지한다.That is, the palladium particles 24 deposited on the surface of the interlayer insulating film 22 are completely removed by the force of hydro-dynamic, but the palladium particles deposited on the surface of the semiconductor substrate 21 in the contact hole 23 ( 24) they remain stuck.
다음으로, 도 2 및 도 3d에 도시된 바와같이, 콘택홀(24)내 반도체기판(21) 표면상에 잔류하는 팔라듐입자(24)들상에 무전해도금용액을 이용하여 실리콘막(25)을 선택적으로 성장시킨다(S5).Next, as shown in FIGS. 2 and 3D, the silicon film 25 is formed by using an electroless plating solution on the palladium particles 24 remaining on the surface of the semiconductor substrate 21 in the contact hole 24. Selectively grown (S5).
여기서, 실리콘막(25)을 선택적으로 증착하기 위한 무전해도금용액은 수산화 규소[Si(OH)4]와 EDTA를 첨가하여 교반시키고, TMAH로 용액의 pH를 알칼리상태(pH=2∼13)로 만든 후, 용액에 HCHO를 혼합한다.Here, the electroless plating solution for selectively depositing the silicon film 25 is stirred by addition of silicon hydroxide [Si (OH) 4 ] and EDTA, and the pH of the solution is adjusted with TMAH in an alkaline state (pH = 2 to 13). After making, mix HCHO into the solution.
여기서, HCHO를 혼합하기 전에 용액의 pH를 알칼리상태로 만드는 이유는, 전자를 공급하는 HCHO가 산의 상태에서는 메탄올로 급변하기 때문에 이러한 부반을 막기 위하여 TMAH로 pH를 알칼리 상태로 만드는 것이다.The reason why the pH of the solution is made alkaline before mixing HCHO is that the pH is made alkaline with TMAH in order to prevent such breakdown since HCHO supplying electrons suddenly changes to methanol in the acid state.
한편, 이때 무전해도금용액을 이용한 실리콘막(24)의 선택적 증착은 25℃∼90℃에서 진행하는 것이 바람직하다.In this case, the selective deposition of the silicon film 24 using the electroless plating solution is preferably performed at 25 ° C to 90 ° C.
전술한 실시예에서는 팔라듐을 이용한 전처리공정 및 실리콘막의 선택적 증착법을 설명하였으나, 금속촉매로서 팔라듐(Pd)외에 금(Au), 은(Ag), 주석(Sn), 니켈(Ni), 철(Fe), 구리(Cu) 및 백금(Pt)중에서 선택된 어느 하나를 이용하는 경우에도 동일한 효과를 구현할 수 있다.In the above embodiment, the pretreatment process using palladium and the selective deposition method of the silicon film have been described, but gold (Au), silver (Ag), tin (Sn), nickel (Ni), iron (Fe) in addition to palladium (Pd) as a metal catalyst ), The same effect can be realized when using any one selected from copper (Cu) and platinum (Pt).
그리고, 실리콘막을 반도체기판을 노출시키는 콘택홀에 성장시켰으나, 본 발명에 따른 실리콘막의 선택적 증착은 랜딩플러그, 비트라인콘택, 스토리지노드콘택, 스토리지노드로 이용될 실리콘막의 증착에도 적용 가능하다.In addition, although the silicon film is grown in a contact hole exposing the semiconductor substrate, the selective deposition of the silicon film according to the present invention is applicable to the deposition of a silicon film to be used as a landing plug, a bit line contact, a storage node contact, or a storage node.
도 4a 내지 도 4d는 본 발명의 제2실시예에 따른 콘택 형성 방법을 도시한 공정 단면도이다.4A to 4D are cross-sectional views illustrating a method for forming a contact according to a second embodiment of the present invention.
도 4a에 도시된 바와 같이, 반도체기판(31)상에 층간절연막(32)을 증착한 후, 층간절연막(32)상에 감광막을 이용한 콘택마스크(도시 생략)를 형성하고, 콘택마스크로 층간절연막(32)을 식각하여 반도체기판(31)의 소정 표면을 노출시키는 콘택홀(도시 생략)을 형성한다.As shown in FIG. 4A, after the interlayer insulating film 32 is deposited on the semiconductor substrate 31, a contact mask (not shown) using a photosensitive film is formed on the interlayer insulating film 32, and the interlayer insulating film is formed as a contact mask. The 32 is etched to form a contact hole (not shown) for exposing a predetermined surface of the semiconductor substrate 31.
다음으로, 콘택홀 형성시 발생된 오염원(유기물, 금속불순물 및 금속산화물)을 제거함과 동시에 콘택홀내에 노출된 반도체기판(31)에 후속 배리어막을 균일하게 증착하기 위한 표면을 제공하기 위해 전세정 공정을 진행한다.Next, a pre-cleaning process is performed to remove contaminants (organic, metal impurities and metal oxides) generated during the formation of the contact hole and to provide a surface for uniformly depositing the subsequent barrier film on the semiconductor substrate 31 exposed in the contact hole. Proceed.
여기서, 전세정 공정은, 반도체기판(31) 표면에 형성된 유기물과 금속불순물을 제거하기 위해 먼저 황산과 과산화수소(H2SO4:H2O2)를 3:1로 혼합한 1분∼10분 정도의 비교적 긴 시간의 제1세정을 실시하고, 반도체기판(31) 표면에 형성된 금속산화물을 제거하기 위해 불산과 물(HF:H2O)을 1:10으로 혼합한 10초∼60초의 짧은 시간의 제2세정을 실시한다.Here, in the pre-cleaning step, in order to remove organic matter and metal impurities formed on the surface of the semiconductor substrate 31, first, a sulfuric acid and hydrogen peroxide (H 2 SO 4 : H 2 O 2 ) 3: 1 to 10 minutes 10 seconds to 60 seconds of a mixture of hydrofluoric acid and water (HF: H 2 O) in a 1:10 ratio to remove the metal oxide formed on the surface of the semiconductor substrate 31 by performing the first cleaning for a relatively long time. Perform a second wash of time.
다음으로, 상술한 전세정공정이 완료된 후, 콘택홀을 포함한 층간절연막(32)상에 후속 구리막과 반도체기판(31)간의 상호확산을 방지하기 위한 배리어메탈로서 TiN(33)을 증착한다. 그리고, TiN(33)을 화학적기계적연마 또는 에치백하여 콘택홀내에만 잔류시킨다.Next, after the above-described pre-cleaning process is completed, TiN 33 is deposited on the interlayer insulating film 32 including the contact hole as a barrier metal for preventing mutual diffusion between the subsequent copper film and the semiconductor substrate 31. Then, the TiN 33 is chemically mechanically polished or etched back to remain only in the contact hole.
도 4b에 도시된 바와 같이, TiN(33)상에 선택적으로 구리막을 증착하기 전에 전처리 공정을 실시한다.As shown in FIG. 4B, a pretreatment process is performed prior to selectively depositing a copper film on TiN 33.
전처리 공정은, 금속촉매를 이용한 전처리 용액을 이용하는데, 이러한 전처리 용액에 사용되는 금속 촉매는 팔라듐(Pd), 금(Au), 은(Ag), 주석(Sn), 니켈(Ni), 철(Fe), 구리(Cu) 및 백금(Pt)중에서 선택된 어느 하나를 사용한다.The pretreatment process uses a pretreatment solution using a metal catalyst, and the metal catalysts used in the pretreatment solution are palladium (Pd), gold (Au), silver (Ag), tin (Sn), nickel (Ni), iron ( Fe), copper (Cu) and platinum (Pt) are used.
이하, 팔라듐을 금속촉매로 이용한 팔라듐 전처리 공정에 대해서 설명하기로 한다.Hereinafter, a palladium pretreatment process using palladium as a metal catalyst will be described.
먼저 팔라듐을 금속촉매로 이용한 전처리용액은, 팔라듐 클로라이드(PdCl2, 0.01∼0.1g/l), 암모니아(NH4OH, 5∼20ml), 염산(HCl, 1∼20ml), 불산(HF, 1∼10ml)을 혼합하고, 이때 팔라듐 전처리 용액에 표면 산화제로 질산(HNO3, 1∼20ml)과 팔라듐전처리용액의 안정성을 위한 계면활성제로서 폴리에틸렌글리콘 (PolyEethelyeneGlycol; PEG) 또는 트리톤(Triton)을 미량(0.001∼1mol/l) 첨가한다.First, the pretreatment solution using palladium as a metal catalyst is palladium chloride (PdCl 2 , 0.01 to 0.1 g / l), ammonia (NH 4 OH, 5 to 20 ml), hydrochloric acid (HCl, 1 to 20 ml), hydrofluoric acid (HF, 1 10 ml), and a small amount of polyethylene glycol (PolyEethelyeneGlycol (PEG) or Triton) is used as a surfactant for the stability of the nitric acid (HNO 3 , 1-20 ml) and the palladium pretreatment solution as a surface oxidant. (0.001-1 mol / l) is added.
상술한 바와 같은 팔라듐 전처리용액을 이용하는 이유는, 구리막이 증착될 TiN(34)의 표면에서 자발적인 촉매 활성화 경향을 갖도록 하기 위함이다.The reason for using the palladium pretreatment solution as described above is to have a tendency for spontaneous catalyst activation on the surface of the TiN 34 to be deposited.
다음으로, 팔라듐 전처리 용액을 이용한 전처리의 공정 온도를 변화시켜 층간절연막(32) 표면과 TiN(33) 표면에서 서로 다른 결합력과 크기를 갖는 전처리 용액내 팔라듐(Pd) 입자(34)만을 성장시킨다.Next, only the palladium (Pd) particles 34 in the pretreatment solution having different bonding strengths and sizes are grown on the surface of the interlayer insulating film 32 and the TiN 33 by changing the process temperature of the pretreatment using the palladium pretreatment solution.
예컨대, 팔라듐 전처리용액의 공정온도를 50℃에서 80℃로 증가시키면, Pd(NH3)2Cl2에서 팔라듐(Pd) 금속 입자만이 층간절연막(32) 및 TiN(33) 표면에만 성장하게 된다. 이때, 증착된 팔라듐(Pd) 입자의 크기는 수십 나노(nano)에서 수백 나노까지를 갖는다.For example, when the process temperature of the palladium pretreatment solution is increased from 50 ° C. to 80 ° C., only palladium (Pd) metal particles are grown on the surface of the interlayer insulating film 32 and TiN 33 at Pd (NH 3 ) 2 Cl 2 . . At this time, the deposited palladium (Pd) particles have a size of several tens (nano) to several hundred nano.
이처럼, 팔라듐 전처리용액에 의한 전처리 공정 조건 중에서 온도를 변화시킴으로서 TiN(33) 표면 및 층간절연막(32)의 표면에 증착되는 팔라듐 입자(34)들의 형태가 다르도록 할 수 있다.As such, the temperature of the palladium particles 34 deposited on the surface of the TiN 33 and the surface of the interlayer insulating layer 32 may be different by changing the temperature in the pretreatment process conditions using the palladium pretreatment solution.
만약, 상온에서 팔라듐전처리용액을 이용한 전처리 공정을 진행하였을 경우에는, 팔라듐전처리 용액내에서 TiN(33) 표면에 흡착되어 있는 환원된 팔라듐(Pd) 입자(34)들과 함께 상당량의 팔라듐화합물[Pd(NH3)2Cl2]이 층간절연막(32)를 포함한 전표면에 존재하게 된다.If the pretreatment process using the palladium pretreatment solution is performed at room temperature, a significant amount of palladium compound [Pd] is added together with the reduced palladium (Pd) particles 34 adsorbed on the TiN 33 surface in the palladium pretreatment solution. (NH 3 ) 2 Cl 2 ] is present on the entire surface including the interlayer insulating film 32.
이와 같이 팔라듐 전처리용액의 전처리 공정 온도를 조절하여 Pd(NH3)2Cl2에서 순수한 금속의 팔라듐 입자(34)만을 성장시킬 수 있다.As such, only the palladium particles 34 of pure metal may be grown in Pd (NH 3 ) 2 Cl 2 by adjusting the pretreatment process temperature of the palladium pretreatment solution.
다음으로, 도 4c에 도시된 바와 같이, TiN(33) 표면에만 팔라듐입자(34)들이 잔류하도록 물(H2O)를 이용한 후세정 공정을 진행한다.Next, as shown in FIG. 4C, the post-cleaning process using water (H 2 O) is performed such that the palladium particles 34 remain only on the TiN 33 surface.
후세정 공정은 TiN(33) 표면에만 팔라듐 입자(34)들을 잔류시키기 위해서, 팔라듐화합물이 물(H2O)에 쉽게 용해가 되는 특성을 이용한 세정을 실시한다.In the post-cleaning process, the palladium compound 34 is easily dissolved in water (H 2 O) in order to retain the palladium particles 34 only on the TiN 33 surface.
한편, 팔라듐 전처리용액을 이용한 전처리 공정 온도가 80℃까지 상승함에 따라 증착된 팔라듐 입자(34)들의 형태는 유기 화합물 형태가 아닌 주로 순수 금속 팔라듐 상태로 존재한다.Meanwhile, as the pretreatment process temperature using the palladium pretreatment solution rises to 80 ° C., the forms of the deposited palladium particles 34 exist mainly in the form of pure metal palladium, not in the form of organic compounds.
이러한 순수 금속의 팔라듐 입자(34)들이 TiN(33) 표면에서 성장할 경우에는 표면에 흡착력이 매우 강하기 때문에, 후세정 공정시 층간절연막(32) 표면에 형성된 팔라듐입자들은 쉽게 탈착이 되나, TiN(33) 표면에 성장한 팔라듐입자(34)들은 계속 잔류한다.When the palladium particles 34 of the pure metal grow on the TiN 33 surface, since the adsorption force is very strong on the surface, the palladium particles formed on the surface of the interlayer insulating layer 32 are easily desorbed during the post-cleaning process. The palladium particles 34 grown on the surface remain.
다음으로, 도 4d에 도시된 바와같이, TiN(33) 표면상에 잔류하는 팔라듐입자(34)들상에 통상의 구리막 증착을 위한 무전해도금용액을 이용하여 구리막(35)을 콘택홀내 TiN(33) 표면에만 선택적으로 증착한다.Next, as shown in FIG. 4D, the copper film 35 is formed in the contact hole TiN using an electroless plating solution for depositing a conventional copper film on the palladium particles 34 remaining on the TiN 33 surface. (33) Selective deposition only on the surface.
한편, 구리막(35)을 증착하기 위한 무전해도금용액은 공지의 기술을 이용할 수 있으며, 여기서는 그 설명을 생략한다.In addition, a well-known technique can be used for the electroless plating solution for depositing the copper film 35, and the description is abbreviate | omitted here.
이처럼, 구리막(35)을 선택적으로 콘택홀내에만 형성할 수 있어 종래 구리막의 평탄화 공정이 불필요하다.In this way, the copper film 35 can be selectively formed only in the contact hole, so that the conventional copper film planarization process is unnecessary.
한편, TiN(34) 증착시에도 금속촉매를 이용한 전처리 공정을 적용하여 콘택홀내에만 성장시킬 수 있다.Meanwhile, even when the TiN 34 is deposited, it can be grown only in the contact hole by applying a pretreatment process using a metal catalyst.
상술한 것처럼, 본 발명에 따른 금속촉매 및 무전해도금법에 의한 콘택은 반도체기판에만 성장되는 것은 아니고, 후속 세정공정시에도 금속촉매 입자들이 고착된 상태를 유지할 수 있는 모든 막에서도 성장시킬수 있으며, 실리콘막과 구리막외에도 반도체소자의 제조 공정에서 적용되는 실리콘, 구리외에 텅스텐, 알루미늄, 탄탈륨, 티타늄, 몰리브덴, 티타늄나이트라이드, 텅스텐나이트라이드 및 탄탈륨나이트라이드중에서 선택된 하나의 증착시에도 적용가능하다.As described above, the contact of the metal catalyst and the electroless plating method according to the present invention is not only grown on the semiconductor substrate, but also can be grown on any film capable of keeping the metal catalyst particles fixed during the subsequent cleaning process. In addition to the film and the copper film, it is also applicable to the deposition of one selected from tungsten, aluminum, tantalum, titanium, molybdenum, titanium nitride, tungsten nitride and tantalum nitride in addition to silicon and copper which are used in the manufacturing process of semiconductor devices.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 금속촉매입자를 이용한 전처리 공정 및 후세정공정을 이용하여 선택적으로 콘택을 형성하므로, 마스크 오정렬 여유도를 확보하면서 콘택저항 특성을 개선시킬 수 있는 효과가 있다.According to the present invention as described above, since the contact is selectively formed using the pretreatment process and the post-cleaning process using the metal catalyst particles, the contact resistance characteristics can be improved while securing the mask misalignment margin.
또한, 무전해 도금법의 장점과 함께 원하는 콘택홀 내에만 선택적으로 콘택을 성장시키므로써 추가 성장된 막을 제거하기 위한 공정을 생략할 수 있어 공정을단순화시킬 수 있는 효과가 있다.In addition, by selectively growing a contact only in a desired contact hole along with the advantages of the electroless plating method, a process for removing an additional grown film can be omitted, thereby simplifying the process.
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