KR20030050596A - Method for forming isolation in semiconductor device - Google Patents
Method for forming isolation in semiconductor device Download PDFInfo
- Publication number
- KR20030050596A KR20030050596A KR1020010081080A KR20010081080A KR20030050596A KR 20030050596 A KR20030050596 A KR 20030050596A KR 1020010081080 A KR1020010081080 A KR 1020010081080A KR 20010081080 A KR20010081080 A KR 20010081080A KR 20030050596 A KR20030050596 A KR 20030050596A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- high density
- density plasma
- plasma oxide
- mask pattern
- Prior art date
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000007789 gas Substances 0.000 claims description 6
- 239000012495 reaction gas Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 abstract description 10
- 230000000452 restraining effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 230000008021 deposition Effects 0.000 description 8
- 239000000126 substance Substances 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 특히 소자분리막(ISO) 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming an isolation layer (ISO).
일반적으로 반도체 장치의 소자분리(Isolation; ISO)는 LOCOS(Local Oxidation of Silicon) 또는 PGI(Profiled Grove Isolation) 등과 같은 통상적인 소자 분리 방법을 이용하여 반도체기판의 소정 부분에 필드절연막을 형성하여 활성영역을 한정하는 필드영역을 형성한다.In general, device isolation (ISO) of a semiconductor device is an active region by forming a field insulating film on a predetermined portion of a semiconductor substrate by using a conventional device isolation method such as LOCOS (Local Oxidation of Silicon) or PGI (Profiled Grove Isolation). A field area defining the area is formed.
소자 분리 방법 중에서 LOCOS 방법은 활성영역을 한정하는 산화 마스크인 질화막(Nitride)을 반도체기판상에 형성하고, 포토리소그래피(Photolithograpy) 방법으로 패터닝하여 반도체기판의 소정 부분을 노출시킨 후, 노출된 반도체기판을 산화시켜 소자 분리 영역으로 이용되는 필드산화막(Field Oxide)을 형성한다.Among the device isolation methods, the LOCOS method forms a nitride film, which is an oxidation mask defining an active region, on a semiconductor substrate, is patterned by a photolithography method to expose a predetermined portion of the semiconductor substrate, and then the exposed semiconductor substrate. Is oxidized to form a field oxide film used as an isolation region.
LOCOS 방법은 공정이 단순하고, 넓은 부위와 좁은 부위를 동시에 분리할 수 있다는 장점을 갖고 있지만, 측면산화에 의한 새부리(Bird's beak)가 형성되어 소자 분리 영역의 폭이 넓어져서 소오스/드레인 영역의 유효 면적을 감소시킨다. 또한, 필드산화막 형성시 산화막의 가장자리에 열 팽창계수의 차이에 따른 응력이 집중됨으로써, 실리콘 기판에 결정 결함이 발생하여 누설전류가 많은 단점이 있다.The LOCOS method has the advantage of simple process and the separation of wide and narrow areas at the same time. However, Bird's beak is formed by lateral oxidation, so the width of device isolation area is widened, so that the effective source / drain area is effective. Reduce the area. In addition, when the field oxide film is formed, stress is concentrated on the edges of the oxide film due to the difference in thermal expansion coefficient, so that a crystal defect occurs in the silicon substrate and thus a leakage current is increased.
최근에 반도체소자의 집적도가 증가함에 따라 디자인 룰이 감소하고, 따라서 반도체소자와 반도체소자를 분리하는 소자분리막의 크기도 같은 스케일(scale)만큼 축소되어 통상의 LOCOS, PBL 등과 같은 소자 분리 방법은 그 적용이 한계에 이르게되었다.In recent years, as the integration degree of semiconductor devices increases, the design rule decreases. Accordingly, the size of the device isolation layer separating the semiconductor devices from the semiconductor devices is also reduced by the same scale, so that a conventional device separation method such as LOCOS, PBL, etc. Application has reached its limit.
이를 해결하기 위해 적용된 STI 방법은 반도체기판상에 반도체기판과 식각선택비가 양호한 질화막을 형성하고, 질화막을 하드마스크(Hardmask)로 사용하기 위해 질화막을 포토리소그래피 방법으로 패터닝하여 질화막 패턴을 형성하고, 질화막 패턴을 하드 마스크로 사용하여 반도체기판을 소정 깊이로 건식 식각 방법으로 패터닝하여 트렌치를 형성한 후, 트렌치에 절연막을 매립시킨 후 화학적기계적연마(Chemical Mechanical Polishing; CMP)하여 트렌치에 매립되는 필드절연막을 형성한다.The STI method applied to solve this problem is to form a nitride film having a good etching selectivity with a semiconductor substrate on the semiconductor substrate, and to form a nitride film pattern by patterning the nitride film by photolithography to use the nitride film as a hard mask. Using the pattern as a hard mask, the semiconductor substrate is patterned by dry etching to a predetermined depth to form a trench, an insulating film is embedded in the trench, and chemical mechanical polishing (CMP) is used to fill a field insulating film embedded in the trench. Form.
최근에는 대부분의 메모리 장치에서 소자간 분리를 위해 트렌치에 매립되는 물질로 고밀도 플라즈마 산화막(High Density Plasma Oxide) 예컨대 USG(Undoped Silicate Glass)을 이용하고 있다.Recently, high-density plasma oxide (USG), such as USG (Undoped Silicate Glass), is used as a material embedded in a trench for isolation between devices in most memory devices.
도 1a 내지 도 1d는 종래기술에 따른 소자분리막 형성 방법을 도시한 공정 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a device isolation film according to the prior art.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 패드산화막(12)과 패드질화막(13)을 증착한다. 이때, 패드질화막(13)은 후속 화학적기계적연마(CMPS) 공정에서 스톱층(Stop layer)으로 활용한다.As shown in FIG. 1A, a pad oxide film 12 and a pad nitride film 13 are deposited on the semiconductor substrate 11. In this case, the pad nitride layer 13 is used as a stop layer in a subsequent chemical mechanical polishing (CMPS) process.
다음으로, 패드질화막(13)상에 감광막을 도포한 후 노광 및 현상으로 패터닝하여 트렌치를 형성하기 위한 STI 마스크(14)를 형성한 다음, STI 마스크(14)를 이용하여 패드질화막(13), 패드산화막(12)을 순차적으로 식각한다.Next, after coating the photoresist film on the pad nitride film 13 and patterning by exposure and development to form an STI mask 14 for forming a trench, the pad nitride film 13, using the STI mask 14, The pad oxide film 12 is sequentially etched.
그리고, 계속해서, 패드산화막(12) 식각후 노출된 반도체기판(11)을 소정 깊이로 식각하여 다수의 트렌치(15)를 형성한다.Subsequently, the semiconductor substrate 11 exposed after the pad oxide film 12 is etched is etched to a predetermined depth to form a plurality of trenches 15.
도 1b에 도시된 바와 같이, STI 마스크(14)를 제거한 후, 트렌치(15)의 측벽을 산화시켜 측벽산화막(16)을 성장시키고, 전면에 고밀도 플라즈마 산화막, 예컨대 USG막(17)을 증착한다.As shown in FIG. 1B, after the STI mask 14 is removed, the sidewall of the trench 15 is oxidized to grow the sidewall oxide film 16, and a high density plasma oxide film such as a USG film 17 is deposited on the entire surface. .
이 때, USG막(17) 증착시 공극(18, void; v)이 발생된다.At this time, voids 18 are generated during deposition of the USG film 17.
도 1c에 도시된 바와 같이, 패드질화막(13)이 노출될때까지 USG막(17)을 화학적기계적연마한다. 이 때, 공극(18)이 노출된다.As shown in FIG. 1C, the USG film 17 is chemically mechanically polished until the pad nitride film 13 is exposed. At this time, the voids 18 are exposed.
도 1d에 도시된 바와 같이, 패드질화막(13) 및 패드산화막(12)을 제거한 후, USG막(17)을 습식식각으로 등방성식각하여 USG막(17)으로 이루어진 STI구조의 소자분리막을 형성한다.As shown in FIG. 1D, after the pad nitride film 13 and the pad oxide film 12 are removed, the USG film 17 isotropically etched by wet etching to form an element isolation film having an STI structure made of the USG film 17. .
상술한 종래기술에서는 트렌치에 매립되는 고밀도플라즈마산화막으로서 USG막을 이용하였으나, USG막(17)은 그 증착특성상 공극(18)이 발생되고, 이러한 공극(18)은 패드질화막과 패드산화막 제거후에도 노출됨에 따라 소자간 절연불량을 초래하여 누설전류를 발생시키는 원인이 된다.In the above-described conventional technique, the USG film is used as the high density plasma oxide film embedded in the trench, but the USG film 17 has pores 18 due to its deposition characteristics, and the pores 18 are exposed even after the pad nitride film and the pad oxide film are removed. As a result, insulation failure between devices may occur, causing leakage current.
이러한 공극을 제거하기 위해서, USG막 대신에 가류성 산화막(Flowable oxide)을 적용한 소자분리막 형성 방법에 제안되었다(도 2 참조).In order to remove such voids, a device isolation film formation method using a volatile oxide film instead of the USG film has been proposed (see FIG. 2).
그러나, 도 2에 도시된 바와 같이, 가류성 산화막을 이용하는 경우에는 공극이 없는 소자분리막(22) 형성이 가능하지만, 습식 식각 속도가 고밀도 플라즈마 산화막에 비해 매우 빨라 트랜지스터 형성을 위한 후속 공정에서의 세정 공정 진행시에 과도하게 식각되어 소자분리막(22)의 높이가 반도체기판(21)보다 낮아지는 모우트(Moat) 현상('A')이 발생되고, 이에 따라 소자간 분리막으로서의 기능을 할 수 없는 문제점이 있다.However, as shown in FIG. 2, when the vulcanizable oxide film is used, it is possible to form the device isolation film 22 without voids, but the wet etching rate is much faster than that of the high density plasma oxide film. During the process, excessive etching is performed to cause a moat phenomenon ('A') in which the height of the device isolation layer 22 is lower than that of the semiconductor substrate 21. Thus, the device cannot function as an interlayer isolation film. There is a problem.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 트렌치에 매립되는 고밀도 플라즈마 산화막의 보이드 형성에 따른 누설전류를 억제하고, 모우트 현상을 방지하는데 적합한 반도체장치의 소자분리막 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and provides a method for forming a device isolation film of a semiconductor device suitable for suppressing leakage current due to void formation of a high density plasma oxide film embedded in a trench and preventing a mote phenomenon. Its purpose is to.
도 1a 내지 도 1d는 종래기술의 제1예에 따른 소자분리막의 형성 방법을 도시한 공정 단면도,1A to 1D are cross-sectional views illustrating a method of forming a device isolation film according to a first example of the prior art;
도 2는 종래기술의 제2예에 따른 소자분리막을 도시한 도면,2 is a view showing a device isolation film according to a second example of the prior art;
도 3a 내지 도 3e는 본 발명의 실시예에 따른 소자분리막의 형성 방법을 도시한 공정 단면도.3A to 3E are cross-sectional views illustrating a method of forming an isolation layer in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 패드산화막31 semiconductor substrate 32 pad oxide film
33 : 패드질화막 34 : STI 마스크33: pad nitride film 34: STI mask
35 : 트렌치 36 : 측벽산화막35 trench 36 sidewall oxide film
37 : 제1USG막 38 : 공극37: 1st USG film 38: void
39 : 제2USG막 40 : 소자분리막39: second USG film 40: device isolation film
상기 목적을 달성하기 위한 본 발명의 반도체장치의 소자분리막의 형성 방법은 반도체기판상에 패드산화막과 패드질화막의 순서로 적층된 마스크패턴을 형성하는 단계, 상기 마스크패턴에 의해 노출된 상기 반도체기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계, 상기 트렌치를 포함한 상기 마스크패턴상에 제1고밀도플라즈마산화막을 형성하는 단계, 상기 마스크패턴의 표면이 드러날때까지 상기 제1고밀도플라즈마산화막을 평탄화하는 단계, 상기 평탄화된 제1고밀도플라즈마산화막상에 제2고밀도플라즈마산화막을 형성하는 단계, 상기 마스크패턴의 표면이 드러날때까지 상기 제2고밀도플라즈마산화막을 평탄화하는 단계, 및 상기 마스크패턴을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.In order to achieve the above object, a method of forming a device isolation film of a semiconductor device according to the present invention includes forming a mask pattern stacked on a semiconductor substrate in the order of a pad oxide film and a pad nitride film, wherein the semiconductor substrate is exposed by the mask pattern. Forming a trench by etching to a predetermined depth, forming a first high density plasma oxide layer on the mask pattern including the trench, and planarizing the first high density plasma oxide layer until the surface of the mask pattern is exposed; Forming a second high density plasma oxide film on the planarized first high density plasma oxide film, planarizing the second high density plasma oxide film until the surface of the mask pattern is exposed, and removing the mask pattern Characterized in that made.
바람직하게, 상기 제1고밀도플라즈마산화막은 3500Å∼6000Å의 두께로 형성되는 USG막이고, 제2고밀도플라즈마산화막은 1000Å∼2500Å의 두께로 형성되는 USG막인 것을 특징으로 한다.Preferably, the first high density plasma oxide film is a USG film having a thickness of 3500 kPa to 6000 kPa, and the second high density plasma oxide film is a USG film formed of a thickness of 1000 kPa to 2500 kPa.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체장치의 소자분리막 형성 방법을 도시한 공정 단면도이다.3A to 3E are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
도 3a에 도시된 바와 같이, 반도체기판(31)상에 패드산화막(32)과 패드질화막(33)을 증착한다. 이때, 패드질화막(33)은 후속 화학적기계적연마(CMP) 공정에서 연마스톱층으로 활용된다.As shown in FIG. 3A, a pad oxide film 32 and a pad nitride film 33 are deposited on the semiconductor substrate 31. In this case, the pad nitride layer 33 is used as a polishing stop layer in a subsequent chemical mechanical polishing (CMP) process.
여기서, 패드산화막(32)은 30Å∼200Å의 두께로 형성되고, 패드질화막(33)은 500Å∼4000Å 두께로 형성된다.Here, the pad oxide film 32 is formed to a thickness of 30 kPa to 200 kPa, and the pad nitride film 33 is formed to a thickness of 500 kPa to 4000 kPa.
다음으로, 패드질화막(33)상에 감광막을 도포한 후 노광 및 현상으로 패터닝하여 트렌치를 형성하기 위한 STI 마스크(34)를 형성한 다음, STI 마스크(34)를 이용하여 패드질화막(33), 패드산화막(32)을 순차적으로 식각한다.Next, after coating the photoresist film on the pad nitride film 33 and patterned by exposure and development to form an STI mask 34 for forming a trench, the pad nitride film 33, using the STI mask 34, The pad oxide film 32 is sequentially etched.
계속해서, 패드산화막(32) 식각후 노출된 반도체기판(31)을 소정 깊이로 식각하여 다수의 트렌치(35)를 형성한다.Subsequently, the plurality of trenches 35 are formed by etching the exposed semiconductor substrate 31 to a predetermined depth after etching the pad oxide layer 32.
이 때, 트렌치(35)를 형성하기 위한 반도체기판(31)의 식각은, 700W∼1000W의 소스파워, 80W∼110W의 바이어스 파워, 5mTorr∼15mTorr의 진공,10sccm∼30sccm의 Cl2가스와 5sccm∼15sccm의 아르곤 가스를 혼합하여 이루어진다.At this time, the etching of the semiconductor substrate 31 for forming the trench 35 includes a source power of 700 W to 1000 W, a bias power of 80 W to 110 W, a vacuum of 5 mTorr to 15 mTorr, a Cl 2 gas of 10 sccm to 30 sccm, and 5 sccm to Made by mixing 15 sccm of argon gas.
그리고, 트렌치(35)는 2000Å∼3500Å의 깊이로 형성된다.The trench 35 is formed to a depth of 2000 kPa to 3500 kPa.
한편, 트렌치(35) 형성을 위한 감광막 도포전에 반사방지막(Anti-Reflection Coating; ARC)을 형성할 수 있다. 이 때, 반사방지막은 300Å∼900Å의 두께로 형성하고 감광막은 5500Å∼8600Å의 두께로 형성한다.Meanwhile, an anti-reflection coating (ARC) may be formed before the photoresist coating for forming the trench 35. At this time, the antireflection film is formed to a thickness of 300 kPa to 900 kPa and the photosensitive film is formed to a thickness of 5500 kPa to 8600 kPa.
도 3b에 도시된 바와 같이, STI 마스크(34)를 제거한 후, 트렌치(35)를 산화시켜 50Å∼200Å의 측벽산화막(36)을 형성하고, 측벽산화막(36)이 형성된 전면에 제1USG막(37)을 증착한다.As shown in FIG. 3B, after the STI mask 34 is removed, the trench 35 is oxidized to form a sidewall oxide film 36 having a thickness of 50 to 200 GPa, and the first USG film ( 37).
여기서, 제1USG막(37) 증착시 패드질화막(33) 근처에 공극(38)이 발생되도록 조절하는데, 이를 위한 증착조건은 저주파수전원(1500W∼4500W)과 고주파수 전원( 1000W∼2500W)을 인가하고, SiH4(24sccm∼100sccm)의 소스가스와 O2(40sccm∼180sccm)의 반응가스를 이용하고, 증착시 2mTorr∼12mTorr의 진공을 유지한다.Here, when the first USG film 37 is deposited, the voids 38 are adjusted to be generated near the pad nitride film 33. The deposition conditions for this are applied by applying a low frequency power source (1500W to 4500W) and a high frequency power source (1000W to 2500W). , Using a source gas of SiH 4 (24 sccm to 100 sccm) and a reaction gas of O 2 (40 sccm to 180 sccm), and maintaining a vacuum of 2 mTorr to 12 mTorr during deposition.
한편, 제1USG막(37)은 3500Å∼6000Å의 두께로 형성된다.On the other hand, the first USG film 37 is formed to a thickness of 3500 kPa to 6000 kPa.
도 3c에 도시된 바와 같이, 제1USG막(37)을 패드질화막(33)의 표면이 드러날때까지 화학적기계적연마하여 평탄화한다. 이 때, 제1USG막(37)에 발생된 공극(38)의 일부가 노출된다.As shown in FIG. 3C, the first USG film 37 is planarized by chemical mechanical polishing until the surface of the pad nitride film 33 is exposed. At this time, a part of the gap 38 generated in the first USG film 37 is exposed.
다음으로, 평탄화된 제1USG막(37)상에 제2USG막(39)을 증착한다.Next, a second USG film 39 is deposited on the planarized first USG film 37.
이 때, 제2USG막(39) 증착시 평탄화후 드러난 제1USG막의 공극(38)을 완전히매립하도록 조절하는데, 이를 위한 증착조건은 저주파수전원(2000W∼4500W)과 고주파수 전원(1500W∼3500W)을 인가하고, SiH4(24sccm∼100sccm)의 소스가스와 O2(40sccm∼180sccm)의 반응가스를 이용하고, 증착시 2mTorr∼12mTorr의 진공을 유지한다.At this time, the deposition of the second USG film 39 is controlled to completely fill the voids 38 of the first USG film after planarization. The deposition conditions for this are applied to a low frequency power source (2000W to 4500W) and a high frequency power source (1500W to 3500W). Then, using a source gas of SiH 4 (24 sccm to 100 sccm) and a reaction gas of O 2 (40 sccm to 180 sccm), a vacuum of 2 mTorr to 12 mTorr is maintained during deposition.
한편, 제2USG막(39)은 1000Å∼2500Å의 두께로 형성된다On the other hand, the second USG film 39 is formed to a thickness of 1000 GPa to 2500 GPa.
상술한 제1, 2 USG막(37,39) 증착후 막의 치밀화를 위해 950℃∼1150℃의 온도에서 0.5∼3시간동안 열처리할 수 있다.After the deposition of the first and second USG films 37 and 39 described above, the film may be heat treated at a temperature of 950 ° C. to 1150 ° C. for 0.5 to 3 hours.
도 3d에 도시된 바와 같이, 제2USG막(39)을 패드질화막(33)의 표면이 드러날때까지 화학적기계적연마하여 평탄화한다. 이 때의 화학적기계적연마 조건은 연마 테이블의 회전속도를 20rpm∼70rpm, 스핀들(spindle)의 회전속도를 15∼30rpm, 누르는 압력을 5.5∼7psi로 한다.As shown in FIG. 3D, the second USG film 39 is planarized by chemical mechanical polishing until the surface of the pad nitride film 33 is exposed. The chemical mechanical polishing conditions at this time are 20 to 70 rpm for the rotation speed of the polishing table, 15 to 30 rpm for the rotation speed of the spindle, and 5.5 to 7 psi for the pressing pressure.
상술한 제2USG막(39)의 화학적기계적연마후, 제1USG막(37)과 제1USG막()의 공극에 매립된 제2USG막(39)으로 이루어진 소자분리막(이하 도면부호 '40'으로 통합함)이 형성된다.After the chemical mechanical polishing of the second USG film 39 described above, an element isolation film made of a second USG film 39 embedded in a gap between the first USG film 37 and the first USG film 39 (hereinafter referred to as '40'). Is formed.
도 3e에 도시된 바와 같이, 계속해서, 패드질화막(33)과 패드산화막(32)을 제거한 후, 소자분리막(40)을 습식식각으로 등방성 식각하여 최종 STI구조의 소자분리막(40)을 형성한다.As shown in FIG. 3E, after the pad nitride layer 33 and the pad oxide layer 32 are removed, the device isolation layer 40 is isotropically etched by wet etching to form the device isolation layer 40 having a final STI structure. .
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 공극이 없는 소자분리막을 형성하므로써 누설전류를 억제하여 소자의 수율을 향상시킬 수 있는 효과가 있다.The present invention described above has the effect of improving the yield of the device by suppressing the leakage current by forming the device isolation film having no voids.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010081080A KR20030050596A (en) | 2001-12-19 | 2001-12-19 | Method for forming isolation in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010081080A KR20030050596A (en) | 2001-12-19 | 2001-12-19 | Method for forming isolation in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030050596A true KR20030050596A (en) | 2003-06-25 |
Family
ID=29576312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010081080A KR20030050596A (en) | 2001-12-19 | 2001-12-19 | Method for forming isolation in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030050596A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100427717B1 (en) * | 2002-06-04 | 2004-04-28 | 주식회사 하이닉스반도체 | Manufacturing Method of Semiconductor Device |
| KR100701692B1 (en) * | 2005-04-15 | 2007-03-29 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
-
2001
- 2001-12-19 KR KR1020010081080A patent/KR20030050596A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100427717B1 (en) * | 2002-06-04 | 2004-04-28 | 주식회사 하이닉스반도체 | Manufacturing Method of Semiconductor Device |
| KR100701692B1 (en) * | 2005-04-15 | 2007-03-29 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4498483B2 (en) | Method for forming trench isolation in semiconductor device | |
| KR100224700B1 (en) | Isolation method of semiconductor device | |
| KR20030013761A (en) | Structure of Trench Isolation and Method of Forming The Same | |
| JPH05315441A (en) | Manufacture of semiconductor device provided with polishing process | |
| KR100513799B1 (en) | Method for making semiconductor device having trench isolation | |
| KR100677998B1 (en) | Method for manufacturing shallow trench isolation layer of the semiconductor device | |
| KR0172792B1 (en) | Method of manufacturing isolation for semiconductor device | |
| KR100708530B1 (en) | Method for preventing divot pattern during the shallow trench isolation process | |
| KR20030050596A (en) | Method for forming isolation in semiconductor device | |
| KR100475025B1 (en) | Forming method for field oxide of semiconductor device | |
| KR20040036757A (en) | Isolation method of semiconductor device using shallow trench isolation process | |
| KR100874429B1 (en) | Gap filling method in semiconductor device manufacturing | |
| US20020137305A1 (en) | Fabrication method of shallow trench isolation | |
| KR20040110792A (en) | The method for forming shall trench isolation in semiconductor device | |
| KR100894791B1 (en) | Method of forming a isolation layer in a semiconductor device | |
| KR19990057948A (en) | Trench type isolation layer formation method for semiconductor devices having different trench widths | |
| KR20010063731A (en) | Method of forming an isolation layer in a semiconductor device | |
| KR100477924B1 (en) | Device isolation film formation method of semiconductor device | |
| KR100480625B1 (en) | Method for forming trench isolation and semiconductor device comprising the same | |
| KR100507380B1 (en) | Method of forming an isolation layer in a semiconductor device | |
| KR20050003061A (en) | Fabricating method for trench isoaltion layer using bottom anti reflection coating | |
| KR100808378B1 (en) | Formation method of trench in semiconductor device | |
| KR100528448B1 (en) | Shallow trench isolation method of semiconductor device | |
| KR20080062560A (en) | Method for forming isolation to semiconductor device | |
| KR20040105980A (en) | The method for forming shallow trench isolation in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |