KR20030044341A - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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Publication number
KR20030044341A
KR20030044341A KR1020010075057A KR20010075057A KR20030044341A KR 20030044341 A KR20030044341 A KR 20030044341A KR 1020010075057 A KR1020010075057 A KR 1020010075057A KR 20010075057 A KR20010075057 A KR 20010075057A KR 20030044341 A KR20030044341 A KR 20030044341A
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South Korea
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film
via hole
layer
deposited
gas
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KR1020010075057A
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Korean (ko)
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조영아
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주식회사 하이닉스반도체
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Priority to KR1020010075057A priority Critical patent/KR20030044341A/en
Publication of KR20030044341A publication Critical patent/KR20030044341A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to reduce fabricating cost by forming low interconnection resistance without depositing a Ti layer and a TiN layer in an expensive cluster tool, and to improve step coverage of the TiN layer and a tungsten layer by increasing an area of a metal interconnection and a via hole and removing an oxide on an interface. CONSTITUTION: After the metal interconnection having a predetermined slope is formed in a predetermined region on a semiconductor substrate(21) of a predetermined structure, an interlayer dielectric(24) is formed on the resultant structure. A predetermined region of the interlayer dielectric is etched to form a via hole exposing the metal interconnection. The Ti layer(26) and the TiN layer(27) are deposited on the resultant structure including the via hole by using different chambers. A plasma treatment is performed to remove a titanium oxide layer formed on the Ti layer caused by vacuum breakdown. The TiN layer is deposited. The tungsten layer(29) is deposited to fill the via hole and is patterned to form a tungsten plug.

Description

반도체 소자의 제조 방법{Method of manufacturing a semiconductor device}Method of manufacturing a semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 하부 배선을 약간의 기울기를 갖도록 사다리꼴로 형성하고, 확산 방지막으로 Ti막 및 TiN막을 다른 챔버를 이용하여 증착하되, Ti막을 증착한 후 진공 파괴시 대기중에 노출되어 형성되는 티타늄 산화막을 플라즈마 처리를 실시하여 제거하고 TiN막을 증착함으로써 오정렬에 의한 콘택 면적의 감소를 방지하고, 콘택 저항을 감소시킬 수 있는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and in particular, the lower wiring is formed in a trapezoidal shape with a slight inclination, and a Ti film and a TiN film are deposited using different chambers as a diffusion barrier film, but when the Ti film is deposited and vacuum destroyed. The present invention relates to a method for manufacturing a semiconductor device capable of preventing a reduction in contact area due to misalignment and reducing contact resistance by removing a titanium oxide film formed by exposure to the atmosphere by performing a plasma treatment and depositing a TiN film.

디자인 룰의 감소와 고속 소자의 요구에 따라 다층의 배선 구조와 스택 비아 공정이 널리 사용되고 있다. 스택 비아 공정의 경우 리소그라피 공정 및 식각 공정으로 하부의 배선을 정확하게 노출시키는 것이 가장 중요하지만, 공정 진행상 오정렬이 필연적으로 발생되며, 이를 고려한 공정 마진이 필요하다.Multi-layered wiring structures and stack via processes are widely used due to the reduction of design rules and the demand for high-speed devices. In the case of the stack via process, it is most important to accurately expose the lower wiring by the lithography process and the etching process, but misalignment occurs inevitably during the process, and a process margin is required in consideration of this.

실제 오정렬이 발생한 배선 및 비아홀에 후속 공정으로 확산 방지막 및 플러그 형성 공정등을 실시하면, 확산 방지막 상에 산화막이 형성된다. 이로 인하여 콘택의 면적이 감소하는 동시에 저항이 증가된다.When a diffusion barrier and a plug forming step are performed on the wiring and via hole where actual misalignment has occurred, an oxide film is formed on the diffusion barrier. This reduces the area of contact and increases resistance.

그럼, 금속 배선 형성 공정 및 비아홀 형성 공정을 포함하는 종래의 반도체 소자의 제조 방법을 도 1(a) 내지 도 1(c)를 이용하여 설명하면 다음과 같다.Then, a conventional method of manufacturing a semiconductor device including a metal wiring forming step and a via hole forming step will be described with reference to FIGS. 1A to 1C.

도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 금속층(12) 및 반사 방지막(13)을 형성한다. 소정의 마스크를 이용한 리소그라피공정 및 식각 공정으로 반사 방지막(13) 및 금속층(12)을 식각하여 금속 배선을 형성한다. 전체 구조 상부에 층간 절연막(14)을 형성한 후 평탄화시킨다.Referring to FIG. 1A, a metal layer 12 and an antireflection film 13 are formed on a semiconductor substrate 11 on which a predetermined structure is formed. The anti-reflection film 13 and the metal layer 12 are etched by a lithography process and an etching process using a predetermined mask to form metal wirings. The interlayer insulating film 14 is formed over the entire structure and then planarized.

도 1(b)는 소정의 마스크를 이용한 리소그라피 공정 및 식각 공정을 실시하여 층간 절연막(14)의 소정 영역을 식각하여 비아홀(15)을 형성한 상태의 단면도이다.FIG. 1B is a cross-sectional view of a state in which the via hole 15 is formed by etching a predetermined region of the interlayer insulating layer 14 by performing a lithography process and an etching process using a predetermined mask.

도 1(c)는 비아홀(15) 내부에 Ti막(16) 및 TiN막(17)을 적층하여 확산 방지막을 형성한 상태의 단면도이다. 그런데, Ti막(16) 및 TiN막(17)은 인시투 공정으로 진행되는데, Ti막을 증착한 후 TiN막을 증착하기 위한 챔버 조건을 조성하는 과정에서 Ti막 상부에 산화막(18)이 형성된다. 이러한 산화막에 의해 콘택의 면적이 감소하는 동시에 저항이 증가된다.FIG. 1C is a cross-sectional view of the Ti film 16 and the TiN film 17 stacked in the via hole 15 to form a diffusion barrier film. However, the Ti film 16 and the TiN film 17 proceed in an in-situ process. An oxide film 18 is formed on the Ti film in the process of forming a chamber condition for depositing the TiN film after depositing the Ti film. By this oxide film, the contact area is reduced and resistance is increased.

본 발명의 목적은 콘택의 면적을 증가시킬 수 있고 콘택 저항을 감소시킬 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.An object of the present invention is to provide a method for manufacturing a semiconductor device that can increase the area of the contact and reduce the contact resistance.

본 발명의 다른 목적은 저저항의 금속 배선을 형성할 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a low resistance metal wiring.

본 발명에서는 스택 비아에서 오정렬에 의한 콘택 면적의 감소를 방지하고, 콘택 저항을 감소시키기 위해 하부 배선을 약간의 기울기를 갖도록 사다리꼴로 형성하고, 확산 방지막으로 Ti막 및 TiN막을 다른 챔버를 이용하여 증착하되, Ti막을증착한 후 진공 파괴시 대기중에 노출되어 형성되는 티타늄 산화막을 플라즈마 처리를 실시하여 제거하고 TiN막을 증착한다.In the present invention, in order to prevent a decrease in contact area due to misalignment in the stack via and to reduce contact resistance, the lower wiring is formed in a trapezoidal shape with a slight inclination, and a Ti film and a TiN film are deposited using different chambers as a diffusion barrier. However, after the Ti film is deposited, the titanium oxide film formed by exposure to the air during vacuum breakdown is removed by plasma treatment to deposit a TiN film.

도 1(a) 내지 도 1(c)는 종래의 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a conventional method for manufacturing a semiconductor device.

도 2(a) 내지 도 2(d)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) to 2 (d) are cross-sectional views of devices sequentially shown to explain a method for manufacturing a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11 및 21 : 반도체 기판12 및 22 : 금속층11 and 21: semiconductor substrate 12 and 22: metal layer

13 및 23 : 반사 방지막14 및 24 : 층간 절연막13 and 23: antireflection film 14 and 24: interlayer insulating film

15 및 25 : 비아홀16 및 26 : Ti막15 and 25: Via hole 16 and 26: Ti film

17 및 27 : TiN막18 및 28 : 티타늄 산화막17 and 27: TiN film 18 and 28: titanium oxide film

29 : 텅스텐막29: tungsten film

본 발명에 따른 반도체 소자의 제조 방법은 소정의 구조가 형성된 반도체 기판 상부의 소정 영역에 소정의 기울기를 갖는 금속 배선을 형성한 후 전체 구조 상부에 층간 절연막을 형성하는 단계와, 상기 층간 절연막의 소정 영역을 식각하여 상기 금속 배선을 노출시키는 비아홀을 형성하는 단계와, 상기 비아홀을 포함한 전체 구조 상부에 서로 다른 챔버를 이용하여 Ti막 및 TiN막을 증착하되, Ti막을 증착한 후 진공 파괴에 의해 상기 Ti막상에 형성되는 티타늄 산화막을 플라즈마 처리를 실시하여 제거하고 상기 TiN막을 증착하는 단계와, 상기 비아홀이 매립되도록 텅스텐막을 증착한 후 패터닝하여 텅스텐 플러그를 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to the present invention, a method of manufacturing a semiconductor device includes forming a metal wiring having a predetermined slope in a predetermined region on a semiconductor substrate on which a predetermined structure is formed, and then forming an interlayer insulating film over the entire structure, and Etching a region to form a via hole exposing the metal wiring, and depositing a Ti film and a TiN film by using different chambers on the entire structure including the via hole, and depositing the Ti film and depositing the Ti film by vacuum breaking. And removing the titanium oxide film formed on the film by performing a plasma treatment, depositing the TiN film, and depositing and patterning a tungsten film so as to fill the via hole, thereby forming a tungsten plug.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2(a) 내지 도 2(d)는 본 발명에 따른 금속 배선 형성 공정과 비아홀 형성 공정을 포함하는 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (d) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a semiconductor device including a metal wiring forming process and a via hole forming process according to the present invention.

도 2(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(21) 상부에 금속층(22) 및 반사 방지막(23)을 형성한다. 소정의 마스크를 이용한 리소그라피공정 및 경사 식각 공정으로 반사 방지막(23) 및 금속층(22)을 식각하여 사다리꼴 형태로 금속 배선을 형성한다. 전체 구조 상부에 층간 절연막(24)을 형성한 후 평탄화시킨다.Referring to FIG. 2A, the metal layer 22 and the anti-reflection film 23 are formed on the semiconductor substrate 21 having a predetermined structure. The anti-reflection film 23 and the metal layer 22 are etched by a lithography process and an oblique etching process using a predetermined mask to form a metal wiring in a trapezoidal form. The interlayer insulating film 24 is formed over the entire structure and then planarized.

도 2(b)를 참조하면, 소정의 마스크를 이용한 리소그라피 공정 및 식각 공정을 실시하여 층간 절연막(24)의 소정 영역을 식각하여 비아홀(25)을 형성한다. 소정의 챔버에서 비아홀(25)을 포함한 전체 구조 상부에 Ti막(26)을 증착한다. Ti막(26)을 증착한 후 다른 챔버로 인입하는 과정에서 진공이 파괴되고 대기중에 노출되어 Ti막(26) 상부에 티타늄 산화막(28)이 형성된다.Referring to FIG. 2B, a via hole 25 is formed by etching a predetermined region of the interlayer insulating layer 24 by performing a lithography process and an etching process using a predetermined mask. The Ti film 26 is deposited on the entire structure including the via holes 25 in a predetermined chamber. In the process of depositing the Ti film 26 and drawing it into another chamber, the vacuum is broken and exposed to the atmosphere, thereby forming a titanium oxide film 28 on the Ti film 26.

도 2(c)를 참조하면, 플라즈마 식각 공정을 실시하여 티타늄 산화막(28)을 제거한다. 플라즈마를 발생시키기 위한 기체로는 N2, H2, N2와 H2의 혼합 기체, N2, H2및 Ar의 혼합 기체중 어느 하나를 사용한다. 그리고, 플라스마 소오스로는 캐패시턴스 타입 RF 플라즈마(capacitance type RF plasma), ICP(inductively coupled plasma), ECF, TCP, 헬리콘(helicon)등을 사용한다. 또한, 플라즈마 처리는 챔버의 온도를 300∼800℃, 압력을 0.1∼100Torr로 유지한 상태에서 N2를 0∼2slm, H2를 0∼2slm 정도 유입시키고, 100W∼5㎾의 전력을 인가하여 10초∼10분 동안 실시한다.Referring to FIG. 2C, the titanium oxide layer 28 is removed by performing a plasma etching process. A gas for generating a plasma is used for any one of N 2, H 2, N 2 and the mixture of H 2 gas, N 2, H 2 and a mixed gas of Ar. As a plasma source, capacitance type RF plasma, inductively coupled plasma, ICP, ECF, TCP, helicon, etc. are used. In addition, in the plasma treatment, N 2 is introduced into 0 to 2 slm and H 2 is introduced into about 0 to 2 slm while the chamber temperature is maintained at 300 to 800 ° C. and the pressure is maintained at 0.1 to 100 Torr. Run for 10 seconds to 10 minutes.

상기와 같은 조건에서 N2및 H2혼합 기체를 이용한 플라즈마 식각에 의한 티타늄 산화막 제거 반응은 [화학식 1]과 같다.Under the above conditions, the titanium oxide film removal reaction by plasma etching using N 2 and H 2 mixed gas is as shown in [Formula 1].

TiO2+ 2H2+ 1/2N2→TiN + 2H20↑TiO 2 + 2H 2 + 1 / 2N 2 → TiN + 2H 2 0 ↑

도 2(d)를 참조하면, 티타늄 산화막(28)을 제거한 후 전체 구조 상부에 TiN막(27)을 증착한다. TiN막(27)은 TDMAT를 전구체로 사용한 MOCVD 방법을 이용하여 증착하며, 증착과 플라즈마 처리를 반복 실시하여 형성한다. 이때, TiN막(27)은 300∼600℃의 온도와 0.1∼100Torr의 압력에서 5초∼5분 동안 증착한다. 한편, MOCVD 증착 공정과 플라즈마 처리를 TiN막(27)이 30∼70Å 두께로 증착될 때마다 반복 실시한다. 그리고, CVD 방법으로 텅스텐막(29)을 형성한 후 RIE 식각 공정 또는 CMP 공정을 실시하여 텅스텐막(29), TiN막(27) 및 Ti막(26)을 제거하여 층간 절연막(24)를 노출시켜 텅스텐 플러그를 형성한다.Referring to FIG. 2D, after removing the titanium oxide film 28, a TiN film 27 is deposited on the entire structure. The TiN film 27 is deposited by the MOCVD method using TDMAT as a precursor, and is formed by repeatedly performing deposition and plasma treatment. At this time, the TiN film 27 is deposited for 5 seconds to 5 minutes at a temperature of 300 to 600 ° C. and a pressure of 0.1 to 100 Torr. On the other hand, the MOCVD deposition process and the plasma treatment are repeatedly performed whenever the TiN film 27 is deposited to a thickness of 30 to 70 占 퐉. After the tungsten film 29 is formed by CVD, an RIE etching process or a CMP process is performed to remove the tungsten film 29, the TiN film 27, and the Ti film 26 to expose the interlayer insulating film 24. To form a tungsten plug.

상술한 바와 같이 본 발명에 의하면 하부 금속 배선을 약간의 경사를 갖도록 형성함으로써 수직하게 형성할 때 보다 공정 마진을 증가시킬 수 있고, 비아홀을 형성하기 위한 식각 공정에서 마진을 증가시킬 수 있다. 또한, Ti막을 증착한 후 진공 파괴에 의해 대기중에 노출되어 티타늄 산화막이 형성되지만, TiN막을 증착하기 전에 플라즈마 처리로 제거하여 진공을 유지한 상태에서 공정을 실시하는 것과 동일한 수준의 낮은 배선 저항을 얻을 수 있다. 따라서, Ti막과 TiN막을 고가의 클러스터 툴(cluster tool)에서 증착하지 않고도 낮은 배선 저항을 얻을 수 있어 장비 구성이 용이해지고 생산 원가를 절감할 수 있으며, 장비의 수율 측면에서 유리하다. 그리고, 금속 배선 및 비아홀의 면적 증가와 계면에 존재하던 산화막을 제거할 수 있으므로 콘택 저항을 감소시킬 수 있어 후속 TiN막 및 텅스텐막의 스텝 커버러지를 향상시킬 수 있어 저저항의 배선을 형성할 수 있다.As described above, according to the present invention, by forming the lower metal wiring to have a slight inclination, the process margin can be increased more than when the vertical metal line is formed vertically, and the margin can be increased in the etching process for forming the via hole. In addition, after depositing the Ti film, the titanium oxide film is formed by exposure to the atmosphere by vacuum breakdown, but before the deposition of the TiN film, the titanium oxide film is removed by plasma treatment to obtain a low wiring resistance at the same level as the process performed under vacuum. Can be. Therefore, a low wiring resistance can be obtained without depositing a Ti film and a TiN film in an expensive cluster tool, thereby facilitating a device configuration, reducing a production cost, and advantageous in terms of yield of equipment. In addition, since the area of the metal wiring and the via hole and the oxide film existing at the interface can be removed, the contact resistance can be reduced, thereby improving the step coverage of the subsequent TiN film and the tungsten film, thereby forming a low resistance wiring. .

Claims (8)

소정의 구조가 형성된 반도체 기판 상부의 소정 영역에 소정의 기울기를 갖는 금속 배선을 형성한 후 전체 구조 상부에 층간 절연막을 형성하는 단계와,Forming a metal wiring having a predetermined slope in a predetermined region on the semiconductor substrate having a predetermined structure, and then forming an interlayer insulating film on the entire structure; 상기 층간 절연막의 소정 영역을 식각하여 상기 금속 배선을 노출시키는 비아홀을 형성하는 단계와,Etching via a predetermined region of the interlayer insulating layer to form a via hole exposing the metal line; 상기 비아홀을 포함한 전체 구조 상부에 서로 다른 챔버를 이용하여 Ti막 및 TiN막을 증착하되, Ti막을 증착한 후 진공 파괴에 의해 상기 Ti막상에 형성되는 티타늄 산화막을 플라즈마 처리를 실시하여 제거하고 상기 TiN막을 증착하는 단계와,The Ti film and the TiN film are deposited by using different chambers on the entire structure including the via hole. After the Ti film is deposited, the titanium oxide film formed on the Ti film by vacuum destruction is removed by plasma treatment to remove the TiN film. Depositing, 상기 비아홀이 매립되도록 텅스텐막을 증착한 후 패터닝하여 텅스텐 플러그를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 제조 방법.And depositing a tungsten film so as to fill the via hole, and then patterning the tungsten plug to form a tungsten plug. 제 1 항에 있어서, 상기 플라즈마 처리는 N2가스, H2가스, N2와 H2의 혼합 기체, N2, H2및 Ar의 혼합 기체중 어느 하나를 사용하여 실시하는 것을 특징으로 하는 반도체 소자의 제조 방법은The method of claim 1, wherein the plasma processing is a semiconductor, characterized in that the carried out using any of the N 2 gas, H 2 gas, N 2 and the mixture of H 2 gas, N 2, H 2 and a mixed gas of Ar Device manufacturing method 제 1 항에 있어서, 상기 플라즈마 처리는 캐패시턴스 타입 RF 플라즈마, ICP(inductively coupled plasma), ECF, TCP, 헬리콘(helicon)중 어느 하나를 소오스로 사용하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the plasma processing uses any one of a capacitance type RF plasma, an inductively coupled plasma (ICP), an ECF, a TCP, and a helicon as a source. 제 1 항에 있어서, 상기 플라즈마 처리는 챔버를 300 내지 800℃의 온도와 0.1 내지 100Torr의 압력으로 유지한 상태에서 N2가스를 0 내지 2slm, H2가스를 0 내지 2slm 정도 유입시키고, 100W 내지 5㎾의 전력을 인가하여 10초 내지 10분 동안 실시하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the plasma treatment is performed by introducing N 2 gas from 0 to 2 slm and H 2 gas from about 0 to 2 slm while maintaining the chamber at a temperature of 300 to 800 ° C. and a pressure of 0.1 to 100 Torr. The method of manufacturing a semiconductor device, characterized in that for 10 seconds to 10 minutes by applying a power of 5 kW. 제 1 항에 있어서, 상기 TiN막은 TDMAT를 전구체로 사용한 MOCVD 방법으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the TiN film is formed by a MOCVD method using TDMAT as a precursor. 제 1 항에 있어서, 상기 TiN막은 증착과 플라즈마 처리를 반복 실시하여 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the TiN film is formed by repeatedly performing vapor deposition and plasma treatment. 제 6 항에 있어서, 상기 증착과 플라즈마 처리는 상기 TiN막이 30 내지 70Å 두께로 증착될 때마다 반복 실시하는 것을 특징으로 하는 반도체 소자의 제조 방법.7. The method of claim 6, wherein the deposition and plasma processing are repeated each time the TiN film is deposited to a thickness of 30 to 70 kHz. 제 1 항에 있어서, 상기 TiN막은 300 내지 600℃의 온도와 0.1 내지 100Torr의 압력에서 5초 내지 5분 동안 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the TiN film is formed at a temperature of 300 to 600 ° C. and a pressure of 0.1 to 100 Torr for 5 seconds to 5 minutes.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100613348B1 (en) * 2004-12-22 2006-08-21 동부일렉트로닉스 주식회사 Method of forming a metal wiring layer having barrier metal layer by homogeneous deposition
KR101022101B1 (en) * 2007-07-02 2011-03-17 가부시끼가이샤 도시바 Semiconductor memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100613348B1 (en) * 2004-12-22 2006-08-21 동부일렉트로닉스 주식회사 Method of forming a metal wiring layer having barrier metal layer by homogeneous deposition
KR101022101B1 (en) * 2007-07-02 2011-03-17 가부시끼가이샤 도시바 Semiconductor memory

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