KR20030005600A - Josephson junction device and manufacturing method for using the same - Google Patents

Josephson junction device and manufacturing method for using the same Download PDF

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KR20030005600A
KR20030005600A KR1020010040967A KR20010040967A KR20030005600A KR 20030005600 A KR20030005600 A KR 20030005600A KR 1020010040967 A KR1020010040967 A KR 1020010040967A KR 20010040967 A KR20010040967 A KR 20010040967A KR 20030005600 A KR20030005600 A KR 20030005600A
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josephson junction
thin film
seed layer
superconducting thin
layer
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KR1020010040967A
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Korean (ko)
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안준형
계정일
문승현
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엘지전자 주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming superconductor layers
    • H10N60/0381—Processes for depositing or forming superconductor layers by evaporation independent of heat source, e.g. MBE
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming superconductor layers
    • H10N60/0408—Processes for depositing or forming superconductor layers by sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming superconductor layers
    • H10N60/0436—Processes for depositing or forming superconductor layers by chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661—After-treatment, e.g. patterning
    • H10N60/0688—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0744—Manufacture or deposition of contacts or electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H10N60/12—Josephson-effect devices

Abstract

PURPOSE: A method for fabricating a Josephson junction device is provided to easily fabricate the junction device and improve productivity by forming an amorphous layer between epitaxially-grown superconductive grains while using a patterned seed layer and by controlling the thickness of the amorphous layer through a subsequent heat treatment process. CONSTITUTION: An amorphous material is formed on a substrate. The amorphous material is patterned by using photoresist and is etched to form a seed layer(2). A superconductive thin film(3) is deposited on the substrate including the patterned seed layer. A capping layer is formed on the superconductive thin film and is patterned to form an electrode(6).

Description

조셉슨 접합 소자 및 그의 제조 방법{Josephson junction device and manufacturing method for using the same}Josephson junction device and manufacturing method for using the same

본 발명은 조셉슨 접합에 관한 것으로, 특히 싸앗층을 이용하여 에피성장된 초전도 결정립 사이에 비정질층을 형성하여 초전도/비정질/초전도 접합을 형성하므로써, 접합 제작의 편이성과 생산성을 향상시키는 조셉슨 접합 소자 및 그의 제조 방법에 관한 것이다The present invention relates to a Josephson junction, in particular, by forming an amorphous layer between epitaxially grown superconducting grains using a saat layer to form a superconducting / amorphous / superconducting junction, thereby improving the convenience and productivity of joining the Josephson junction element and It relates to the manufacturing method thereof

일반적으로 초전도체는 완전도체성질, 완전반자성성질 그리고 조셉슨 현상을 가진 물질로서, 수십 년 전부터 주목을 받아왔으나 초전도현상이 시작되는 임계온도가 4K정도의 극저온이어서 산업화의 길은 요원한 것으로 인식되었다.In general, superconductors are materials with perfect conductor properties, fully diamagnetic properties, and Josephson phenomena. They have been attracting attention for decades, but the critical temperature at which superconductivity begins is about 4K.

그러나, 1986년 산화물 고온초전도체가 발견된 이후, 값싼 액체질소를 이용하여 충분히 임계온도 이하로 냉각시킬 수 있게 되면서 초전도현상을 이용한 응용 연구가 산업에 적용될 수 있을 것이라는 예상이 나오면서, 고온초전도체를 이용한 다양한 소자 제작이 활발히 전개되었다.However, after the discovery of oxide high temperature superconductors in 1986, it is possible to cool them below the critical temperature sufficiently using cheap liquid nitrogen, and it is expected that applied research using superconductivity will be applied to the industry. Device fabrication has been actively developed.

그러나, 고온초전도체는 간섭길이(coherence length)가 짧고, 이방성이 커서 조셉슨 접합을 제작하는 것이 대단히 어렵다. 따라서, 저온초전도체에서 사용되던 부도체 절연막을 이용한 샌드위치 접합의 제작에는 아무도 성공하지 못하고 있다. 샌드위치 접합이 성공하기만 한다면 제작의 간편성, 재현성 측면에서 우수한 결과를 기대할 수 있다.However, high temperature superconductors have a short coherence length and anisotropy, making it very difficult to fabricate Josephson junctions. Therefore, no one has succeeded in producing a sandwich junction using a non-conductor insulating film used in a low temperature superconductor. If sandwich bonding is successful, excellent results can be expected in terms of simplicity and reproducibility.

도 1은 일반적인 조셉슨 접합 소자의 개략도이다.1 is a schematic diagram of a typical Josephson junction element.

도 1을 참조하면, 2층의 초전도 박막사이에 얇은 비초전도 박막을 증착시켰을 때 간단한 조셉슨 접합 소자가 완성되는 것이다.Referring to FIG. 1, a simple Josephson junction element is completed when a thin non-superconducting thin film is deposited between two superconducting thin films.

도 2는 종래의 다양한 조셉슨 접합 제조 방식을 나타낸 도면이다.Figure 2 is a view showing a variety of conventional Josephson junction manufacturing method.

도 1에 도시된 바와 같이 학계에 발표된 조셉슨 접합 제조 방법들이며, 현재 학계에 발표된 자료에 따르면, 도 1의 (b)와 같은 GB(Grain Boundary) 접합이나, 에지 지오메트리(edge gemetry)를 이용한 SNS(초전도-상전도-초전도), S-artificial interface-S, S-resonant 터널링 베리어-S 접합 등 다양한 시도를 하고있다.Josephson junction manufacturing methods published in the academic world as shown in Figure 1, according to the data published in the current academic community, using GB (Grain Boundary) junction, such as Figure 1 (b) or using edge geometry (edge gemetry) Various attempts have been made, including SNS (superconductor-phase conduction-superconductivity), S-artificial interface-S, and S-resonant tunneling barrier-S junction.

그러나 인공적으로 결정립계(GB)를 형성한 조셉슨 접합(바이크리스탈의 경우)의 경우에는 특수한 형태의 기판을 사용해야 하므로 제작 비용이 높고, 기판상에 형성된 경계면에만 접합제작이 가능하므로 임의의 위치에 임의의 수의 접합 제작이 불가능하며, 경계면을 지나는 배선은 무조건 약결합형이 되는 문제가 있다.However, in the case of the Josephson junction (in the case of a bi-crystal) which artificially formed the grain boundary (GB), a special type of substrate must be used, and thus the manufacturing cost is high, and the bonding production is possible only at the boundary formed on the substrate. It is impossible to manufacture a number of joints, and there is a problem that the wiring passing through the interface is unconditionally weakly bonded.

그리고, 바이에피택시 방법의 경우에는 공정이 복잡하며, 바이에피택시 및 스탭엣지의 경우는 재현성이 낮고 접합의 특성 조절이 불가능하다.In the case of the bi-epitaxial method, the process is complicated, and in the case of the bi-epitaxial and the step edge, the reproducibility is low and the characteristics of the bonding cannot be controlled.

또한 손상된 약결합형 구조의 조셉슨 접합의 경우에는 손상된 부분의 초전도체로의 복귀가 불가능하고, 고가의 장비가 필요하고, 재현성이 낮으며 그 위에 다층박막 제작이 어렵고 접합을 하나씩 제작해야 하므로 수율이 낮은 문제점이 있다.In addition, in case of the Josephson junction of damaged weakly bonded structure, it is impossible to return the damaged portion to the superconductor, expensive equipment is required, low reproducibility, and it is difficult to manufacture multilayer thin film on it, and thus the yield is low. There is a problem.

이와 같이, 종래의 초전도체 조셉슨 접합은 실험조건의 제어가 힘들고, 재현성이 떨어지며, 소요되는 공정시간이 길고, 고가의 장치가 필요한 문제점이 있다.As described above, the conventional superconductor Josephson junction has a problem in that it is difficult to control the experimental conditions, the reproducibility is low, the process time is long, and an expensive device is required.

따라서, 본 발명의 목적은 이상에서 언급한 종래 기술의 문제점을 감안하여 안출한 것으로서, 제조 공정 및 접합 특성의 조절이 용이하고, 재현성을 향상시킬 수 있도록 한 조셉슨 접합 소자 및 제조 방법을 제공하기 위한 것이다.Accordingly, an object of the present invention has been made in view of the above-mentioned problems of the prior art, and to provide a Josephson junction element and a manufacturing method which can easily control the manufacturing process and bonding characteristics and improve reproducibility. will be.

도 1은 일반적인 조셉슨 접합 소자의 개략도1 is a schematic diagram of a typical Josephson junction element

도 2는 종래의 다양한 조셉슨 접합 제조 방법을 나타낸 도면2 is a view showing a variety of conventional Josephson junction manufacturing method

도 3a 내지 도 3f는 본 발명에 따른 조셉슨 접합 소자의 접합 제조 공정을 순차적으로 나타낸 도면3A to 3F are views sequentially showing a junction manufacturing process of the Josephson junction element according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1 : 기판 2 : 씨앗층1 substrate 2 seed layer

3 : 초전도 박막 4 : 비정질층3: superconducting thin film 4: amorphous layer

5 : 캐핑 레이어 6 : 전극5: capping layer 6: electrode

이상과 같은 목적을 달성하기 위한 본 발명의 일 특징에 따르면, 기판 위에 비정질 물질을 형성하는 단계, 상기 비정질 물질을 포토레지스터로 패턴을 형성시키고 식각하여 씨앗층을 형성하는 단계, 상기 패턴이 된 씨앗층을 포함한 기판 위에 초전도 박막을 증착하는 단계, 상기 초전도 박막위에 캐핑(capping) 레이어를 형성하고, 패턴하여 전극을 형성하는 단계를 포함하여 이루어진다.According to an aspect of the present invention for achieving the above object, the step of forming an amorphous material on a substrate, forming a pattern by etching the amorphous material with a photoresist to form a seed layer, the seed becomes the pattern And depositing a superconducting thin film on the substrate including the layer, and forming a capping layer on the superconducting thin film and patterning the electrode.

바람직하게, 상기 기판은 STO, LAO, NGO, MgO, YSZ, 사파이어 실리콘, LSAT 중 어느 하나로 이루어지고, 상기 씨앗층은 단일 씨앗층이거나 씨앗층/버퍼층의 복합구조의 박막으로 이루어진다.Preferably, the substrate is made of any one of STO, LAO, NGO, MgO, YSZ, sapphire silicon, LSAT, the seed layer is a single seed layer or a thin film of a composite structure of the seed layer / buffer layer.

그리고, 상기 씨앗층이나 버퍼층은 SrTiO3, CaTiO3, CeO2, CuO2, Y2O2, BaZrO2, LAO, MgO, YSZ, Al2O3, Si, LSAT, YBCO 중 어느 하나로 이루어지며, 상기 식각 방법은 이온 밀링, RIE, 습식 식각 중 어느 한 방법을 사용한다.The seed layer or the buffer layer is made of any one of SrTiO 3 , CaTiO 3 , CeO 2 , CuO 2 , Y 2 O 2 , BaZrO 2 , LAO, MgO, YSZ, Al 2 O 3 , Si, LSAT, YBCO, The etching method may be any one of ion milling, RIE, and wet etching.

또한, 상기 초전도 박막은 YBCO, RBCO, BSCCO, TIBCCO, LSCO, NCCO중 어느 하나로 이루어지며, 상기 초전도 박막의 증착은 PLD, sputtering, CVD, coevaporation, MBE 중 어느 한 방법을 사용한다.In addition, the superconducting thin film is made of any one of YBCO, RBCO, BSCCO, TIBCCO, LSCO, NCCO, the deposition of the superconducting thin film using any one method of PLD, sputtering, CVD, coevaporation, MBE.

이상과 같은 다른 목적을 달성하기 위한 본 발명의 다른 특징에 따르면, 초전도 박막사이에 얇은 비초전도 박막을 증착시킨 조셉슨 접합 소자에 있어서, 상기 초전도 박막사이에 비정질 층을 형성한다.According to another feature of the present invention for achieving the above object, in the Josephson junction device in which a thin non-superconducting thin film is deposited between superconducting thin films, an amorphous layer is formed between the superconducting thin films.

이하 본 발명의 바람직한 일 실시 예에 따른 구성 및 작용을 첨부된 도면을 참조하여 설명한다.Hereinafter, a configuration and an operation according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

도 3a 내지 도 3e는 본 발명에 따른 조셉슨 접합 소자의 접합 제조 공정을 순차적으로 나타낸 도면이다.3A to 3E are diagrams sequentially illustrating a junction manufacturing process of the Josephson junction element according to the present invention.

먼저 도 3a에 도시된 바와 같이 STO, LAO, NGO, MgO, YSZ, 사파이어 실리콘,LSAT 등의 기판(1)상에 단일 씨앗층(seed layer) 혹은 씨앗층/버퍼층(seed layer/buffer layer)의 복합구조의 박막(2)을 형성한다.First, as shown in FIG. 3A, a single seed layer or seed layer / buffer layer may be formed on a substrate 1 such as STO, LAO, NGO, MgO, YSZ, sapphire silicon, or LSAT. The thin film 2 of a composite structure is formed.

여기서 상기 씨앗층(2) 혹은 버퍼층의 물질은 초전도 물질이 에피성장이 가능한 SrTiO3, CaTiO3, CeO2, CuO2, Y2O2, BaZrO2, LAO, MgO, YSZ, Al2O3, Si, LSAT, YBCO 등의 물질이다.Wherein the seed layer (2) or the material of the buffer layer is SrTiO 3, the superconducting material capable of epitaxial growth CaTiO 3, CeO 2, CuO 2 , Y 2 O 2, BaZrO 2, LAO, MgO, YSZ, Al 2 O 3, Si, LSAT, YBCO and the like.

이어서 상기 씨앗층(혹은 씨앗층/버퍼층 복합구조)(2)이 완성되면 포토리소그래피(photolithography)를 이용하여 포토레지스터로 패턴을 형성시키고, 이온밀링을 이용하여 식각한다. (도 3b)Subsequently, when the seed layer (or seed layer / buffer layer composite structure) 2 is completed, a pattern is formed by a photoresist using photolithography and etched using ion milling. (FIG. 3B)

상기 식각은 상기와 같이 이온 밀링이나, RIE, 습식 식각(wet etching)등의 방법을 이용한다.The etching is performed by ion milling, RIE, wet etching, or the like as described above.

그 다음 도 3c와 같이, 상기 패턴이 된 씨앗층(혹은 씨앗층/ 버퍼층 복합구조)(2)을 포함하는 상기 기판(1) 위에 다양한 증착법을 이용하여 초전도 박막(3)을 증착시킨다.3C, the superconducting thin film 3 is deposited on the substrate 1 including the patterned seed layer (or seed layer / buffer layer composite structure) 2 using various deposition methods.

상기 초전도 박막(3)을 증착시킬 때 사용되는 고온초전도 물질은 산소 함량에 따라 그 특성이 변화하는 YBCO, RBCO(R은 rare earth 물질), BSCCO, TlBCCO, LSCO, NCCO 등이다.The high temperature superconducting material used when depositing the superconducting thin film 3 is YBCO, RBCO (R is rare earth material), BSCCO, TlBCCO, LSCO, NCCO, etc., whose properties change according to oxygen content.

그리고, 상기 초전도 박막(3)을 증착시키는 증작법은 PLD, sputtering, CVD, coevaporation, MBE등이다.In addition, a deposition method for depositing the superconducting thin film 3 is PLD, sputtering, CVD, coevaporation, MBE, and the like.

상기와 같이 형성된 초전도 박막(3)은 씨앗층(혹은 씨앗층/버퍼층 복합 구조)(2) 상에서는 에피성장을 하게 되어 우수한 초전도 특성을 나타내고, 반면 씨앗층(2)이 없는 부분 위에 형성된 박막의 경우는 비정질(4)상태의 비초전도층을 형성한다.The superconducting thin film 3 formed as described above is epitaxially grown on the seed layer (or the seed layer / buffer layer composite structure) 2 and exhibits excellent superconductivity, whereas the thin film formed on the part without the seed layer 2 is present. Forms a non-superconducting layer in an amorphous (4) state.

또한, 초전도박막(3)의 증착과 후속열처리 과정 중에 일어나는 초전도 결정립의 래터럴(lateral)방향으로의 성장을 통하여 에피성장된 초전도 결정립 사이의 비정질막(4)의 두께를 조절할 수 있다.In addition, it is possible to control the thickness of the amorphous film 4 between the epitaxially grown superconducting grains through the growth of the superconducting grains in the lateral direction during deposition of the superconducting thin film 3 and subsequent heat treatment.

다음으로 상기 초전도 박막(3)을 보호하는 역할을 하는 SrTiO3(STO)등의 캐핑 레이어(5)를 형성한다. (도 3d)Next, a capping layer 5 such as SrTiO 3 (STO), which serves to protect the superconducting thin film 3, is formed. (FIG. 3D)

마지막으로 전극(6)으로써 리프트-오프(lift-off)법으로 Au 등의 전극(6)을 패턴 제작하며, 상기 Au의 접착력을 좋게 하기 위하여 산소분위기 600도 이하에서 열처리를 한다.Finally, as the electrode 6, a pattern of electrodes 6 such as Au is manufactured by a lift-off method, and heat treatment is performed at an oxygen atmosphere of 600 degrees or less in order to improve the adhesion of the Au.

이상의 설명에서와 같이 본 발명은 패턴된 씨앗층을 이용하여 에피성장된 초전도 결정립과 그 사이에 비정질 층(layer)을 형성시키고, 후속 열처리등을 통하여 비정질 층의 두께를 조절 가능하므로 접합 제작의 편이성과 생산성을 향상시키고 접합 특성 조절 및 재현성을 향상시키는 효과가 있다.As described above, according to the present invention, the epitaxially grown superconducting grains using the patterned seed layer and an amorphous layer are formed therebetween, and the thickness of the amorphous layer can be adjusted through subsequent heat treatment. It has the effect of improving the productivity and controlling the bonding properties and reproducibility.

또한, 본 발명은 여러 장의 소자나 대면적의 소자에 대해서 간편하게 적용할 수 있는 공정으로 시편의 지오메트리를 바꾼다 하더라도 쉽게 적용 가능하며, 특히 미세자기검출등에 쓰이는 SQUID와 같은 소자에 적용할 수 있는 효과를 볼 수 있다.In addition, the present invention is a process that can be easily applied to a large number of devices or large-area device even if the geometry of the specimen is changed, it is easy to apply, especially the effect that can be applied to devices such as SQUID used in fine magnetic detection can see.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정하는 것이 아니라 특허 청구 범위에 의해서 정해져야 한다.Therefore, the technical scope of the present invention should not be limited to the contents described in the examples, but should be defined by the claims.

Claims (8)

기판 위에 비정질 물질을 형성하는 단계;Forming an amorphous material over the substrate; 상기 비정질 물질을 포토레지스터로 패턴을 형성시키고, 식각하여 씨앗층을 형성하는 단계;Forming a pattern of the amorphous material by using a photoresist and etching to form a seed layer; 상기 패턴 된 씨앗층을 포함한 기판 위에 초전도 박막을 증착하는 단계Depositing a superconducting thin film on the substrate including the patterned seed layer 상기 초전도 박막위에 캐핑(capping) 레이어를 형성하고, 패턴하여 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 조셉슨 접합 제조 방법Josephson junction manufacturing method comprising the step of forming a capping layer on the superconducting thin film, patterned to form an electrode 제 1항에 있어서,The method of claim 1, 상기 기판은 STO, LAO, NGO, MgO, YSZ, 사파이어 실리콘, LSAT 중 어느 하나로 이루어지는 것을 특징으로 하는 조셉슨 접합 제조 방법Josephson junction manufacturing method characterized in that the substrate is made of any one of STO, LAO, NGO, MgO, YSZ, sapphire silicon, LSAT 제 1항에 있어서,The method of claim 1, 상기 씨앗층은 단일 씨앗층이거나 씨앗층/버퍼층의 복합구조의 박막으로 이루어지는 것을 특징으로 하는 조셉슨 접합 제조 방법Josephson junction manufacturing method characterized in that the seed layer is made of a single seed layer or a thin film of a composite structure of the seed layer / buffer layer. 제 3항에 있어서,The method of claim 3, wherein 상기 씨앗층이나 버퍼층은 SrTiO3, CaTiO3, CeO2, CuO2, Y2O2, BaZrO2, LAO,MgO, YSZ, Al2O3, Si, LSAT, YBCO 중 어느 하나로 이루어지는 것을 특징으로 하는 조셉슨 접합 제조 방법The seed layer or the buffer layer is made of any one of SrTiO 3 , CaTiO 3 , CeO 2 , CuO 2 , Y 2 O 2 , BaZrO 2 , LAO, MgO, YSZ, Al 2 O 3 , Si, LSAT, YBCO Josephson junction manufacturing method 제 1항에 있어서,The method of claim 1, 상기 식각 방법은 이온 밀링, RIE, 습식 식각 중 어느 한 방법을 사용하는 것을 특징으로 하는 조셉슨 접합 제조 방법.The etching method is Josephson junction manufacturing method using any one of ion milling, RIE, wet etching. 제 1항에 있어서,The method of claim 1, 상기 초전도 박막은 YBCO, RBCO, BSCCO, TIBCCO, LSCO, NCCO중 어느 하나로 이루어지는 것을 특징으로 하는 조셉슨 접합 제조 방법.The superconducting thin film Josephson junction manufacturing method characterized in that made of any one of YBCO, RBCO, BSCCO, TIBCCO, LSCO, NCCO. 제 1항에 있어서The method of claim 1 상기 초전도 박막의 증착은 PLD, sputtering, CVD, coevaporation, MBE 중 어느 한 방법을 사용하는 것을 특징으로 하는 조셉슨 접합 제조 방법Josephson junction manufacturing method characterized in that the deposition of the superconducting thin film using any one of PLD, sputtering, CVD, coevaporation, MBE 초전도 박막사이에 얇은 비초전도 박막을 증착시킨 조셉슨 접합 소자에 있어서,In a Josephson junction device in which a thin non-superconducting thin film is deposited between superconducting thin films, 상기 초전도 박막사이에 비정질 증을 형성하는 것을 특징으로 하는 조셉슨 접합 소자.Josephson junction element, characterized in that to form amorphous between the superconducting thin film.
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Publication number Priority date Publication date Assignee Title
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190042720A (en) * 2016-09-15 2019-04-24 구글 엘엘씨 Capping layer to reduce ion mill damage
US10957841B2 (en) 2016-09-15 2021-03-23 Google Llc Capping layer for reducing ion mill damage

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