KR20030003388A - Manufacturing method of Alignment mark and overlay accuracy measurement mark of semiconductor device - Google Patents

Manufacturing method of Alignment mark and overlay accuracy measurement mark of semiconductor device Download PDF

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Publication number
KR20030003388A
KR20030003388A KR1020010039125A KR20010039125A KR20030003388A KR 20030003388 A KR20030003388 A KR 20030003388A KR 1020010039125 A KR1020010039125 A KR 1020010039125A KR 20010039125 A KR20010039125 A KR 20010039125A KR 20030003388 A KR20030003388 A KR 20030003388A
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South Korea
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mark
layer
alignment
field oxide
semiconductor device
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KR1020010039125A
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Korean (ko)
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정영배
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주식회사 하이닉스반도체
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Priority to KR1020010039125A priority Critical patent/KR20030003388A/en
Publication of KR20030003388A publication Critical patent/KR20030003388A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Abstract

PURPOSE: An alignment mark of a semiconductor device and a method for fabricating an overlay accuracy measurement mark are provided to improve reliability of the semiconductor device by maintaining a state of stepped portion after performing a tungsten deposition process, a CMP process, and a metal wiring formation process. CONSTITUTION: A field oxide layer(12) is formed on a mark formation region of a semiconductor substrate(10). A nitride layer(14) as an etch barrier is formed on the field oxide layer(12). An interlayer dielectric(16) is formed on an entire surface of the semiconductor substrate(10) after a MOS process is performed. The interlayer dielectric(16) is planarized. An alignment mark and an outline pattern of an overlay accuracy measurement mark are formed by removing sequentially the interlayer dielectric(16), the nitride layer(14), and the field oxide layer(12). A tungsten layer(18) is formed on the inside of a stepped portion by depositing tungsten thereon and performing a CMP process. The first internal pattern is formed on the inside of the tungsten layer(18). A metal wire(20) and the second internal pattern(21) are formed thereon.

Description

반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법{Manufacturing method of Alignment mark and overlay accuracy measurement mark of semiconductor device}Manufacturing method of alignment mark and overlay accuracy measurement mark of semiconductor device

본 발명은 반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법에 관한 것으로서, 특히 W층을 화학-기계적 연마(chemical-mechanical polishing; 이하 CMP라 칭함) 하는 공정을 구비하는 소자에서 버니어 패턴의 외곽패턴을 단차가 크게 형성하여 후속 정렬마크나 중첩도 측정마크의 단차도 크게 유지되도록하여 정렬 보정이 용이하도록하여 공정수율 및 소자작동의 신뢰성을 향상시킬 수 있는 반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an alignment mark and a superimposition mark of a semiconductor device, and in particular, an outline of a vernier pattern in a device having a process of chemical-mechanical polishing (hereinafter referred to as CMP) of a W layer. The pattern is formed with a large step so that the level of the subsequent alignment mark or overlapping measurement mark is kept large so that the alignment can be easily corrected to improve the process yield and the reliability of device operation. It relates to a manufacturing method of.

일반적으로 고집적 반도체소자는 다수개의 적층막들과 노광마스크가 중첩 사용되는 복잡한 공정을 거치게 되며, 단계별로 사용되는 노광마스크들 간의 정렬이나 스탭퍼와 웨이퍼간의 정렬은 특정 형상의 마크를 기준으로 이루어진다.In general, a highly integrated semiconductor device undergoes a complicated process in which a plurality of stacked layers and an exposure mask are overlapped, and an alignment between exposure masks used in steps or an alignment between a stepper and a wafer is performed based on a mark of a specific shape.

상기 마크들은 다른 마스크들간의 정렬(layer to layer alignment)이나, 하나의 마스크에 대한 다이간의 정렬에 사용되는 정렬 키(alignment key) 혹은 정렬마크와, 패턴간의 중첩 정밀도인 오버레이(overlay)를 측정하기 위한 중첩도(overlay accuracy) 측정마크가 있다.The marks measure layer to layer alignment, or an alignment key or alignment mark used to align between dies for one mask, and an overlay, the precision of the overlap between the patterns. There is an overlay accuracy measurement mark.

반도체소자의 제조 공정에 사용되는 스탭 앤 리피트(step and repeat) 방식의 노광장비인 스테퍼(steper)는 스테이지가 X-Y 방향으로 움직이며 반복적으로 이동 정렬하여 노광하는 장치이다. 상기 스테이지는 스탭퍼 정렬마크를 기준을 자동 또는 수동으로 웨이퍼의 정렬이 이루어지며, 스테이지는 기계적으로 동작되므로 반복되는 공정시 정렬 오차가 발생되고, 정렬오차가 허용 범위를 초과하면 소자에 불량이 발생된다.A stepper, which is a step and repeat type exposure apparatus used in a semiconductor device manufacturing process, is a device in which a stage moves in the X-Y direction and repeatedly moves in alignment. The stage is aligned automatically or manually based on the stepper alignment mark, and the stage is mechanically operated so that an alignment error occurs during the repeated process, and a defect occurs in the device when the alignment error exceeds the allowable range. .

상기와 같이 오정렬에 따른 중첩 정확도의 조정범위는 소자의 디자인 룰(design rule)에 따르며, 통상 디자인 룰의 20∼30% 이내이다.As described above, the adjustment range of the overlapping accuracy due to misalignment depends on the design rule of the device, and is usually within 20 to 30% of the design rule.

또한 반도체기판 상에 형성된 각층들간의 정렬이 정확하게 이루어졌는지를 확인하는 중첩도 측정마크 또는 오버레이 측정마크도 정렬 마크와 동일한 방법으로 사용된다.In addition, an overlapping measurement mark or an overlay measurement mark for confirming whether the alignment between the layers formed on the semiconductor substrate is correctly used is used in the same manner as the alignment mark.

종래 정렬마크 및 오버레이 측정마크는 반도체 웨이퍼에서 칩이 형성되지 않는 부분인 스크라이브 라인(scribe line) 상에 형성되며, 상기 정렬마크를 이용한 오정렬 정도의 측정 방법으로는 버니어(venier) 정렬마크를 이용한 시각 점검 방법과, 박스 인 박스(box in box)나 박스 인 바(box in bar) 정렬 마크를 이용한 자동 점검 방법에 의해 측정한 후, 보상한다.Conventional alignment marks and overlay measurement marks are formed on a scribe line, which is a portion where a chip is not formed in a semiconductor wafer, and a measurement method of a misalignment degree using the alignment marks is based on a time using a venier alignment mark. After the measurement by the inspection method and the automatic inspection method using a box in box or a box in bar alignment mark, compensation is made.

근래에는 금속배선 공정에서 W층을 주로 사용되며, 이러한 W층은 CMP 방법으로 패턴닝되는데, 이러한 CMP 공정은 노광작업시 전공정에서 형성한 정렬마크를 노광장비에서 인식할 때와 현상후 중첩도 측정장비에서 중첩도를 측정할 때 오류를 발생시키는 경우가 많다.Recently, the W layer is mainly used in the metallization process, and the W layer is patterned by the CMP method. This CMP process is used when the exposure equipment recognizes the alignment mark formed in the previous process during the exposure operation and the degree of overlap after development. Errors often occur when measuring the degree of overlap in a measuring instrument.

도 1a 내지 도 1d는 종래 기술에 따른 반도체소자의 정렬마크 및 중첩도 측정마크의 제조 공정도로서, 필드산화막 에치 베리어인 질화막이 있는 경우의 예이다.1A to 1D are manufacturing process diagrams of an alignment mark and an overlapping measurement mark of a semiconductor device according to the prior art, and are examples of a case where a nitride film that is a field oxide etch barrier is present.

먼저, 실리콘 웨이퍼등의 반도체기판(10)상에 필드산화막(12)과 질화막(14) 및 층간절연막(16)을 순차적으로 형성하고, 상기 층간절연막(16)의 상부를 CMP로 평탄화한 후, (도 1a 참조), 자기정렬콘택 형성 공정에서 상기 정렬마크 및 중첩도 측정마크의 외곽 박스가 되도록 상기 층간절연막(16)과 질화막(14)을 식각하여 외곽패턴(17)을 형성한다. (도 1b 참조).First, the field oxide film 12, the nitride film 14, and the interlayer insulating film 16 are sequentially formed on a semiconductor substrate 10 such as a silicon wafer, and the top of the interlayer insulating film 16 is planarized with CMP. In the self-aligning contact forming process, the interlayer insulating layer 16 and the nitride layer 14 are etched to form the outer box of the alignment mark and the overlap measurement mark, thereby forming the outer pattern 17. (See FIG. 1B).

그다음 상기 구조의 전표면에 W층 도포 및 CMP 공정을 진행하여 상기 패턴의 내측에 W층(18)을 형성하여 제1내측패턴(19)을 형성하고, (도 1c 참조), 알루미늄으로된 금속배선(20)을 형성하여 제2내측패턴(21)을 형성한다. 여기서 상기 W층(18)과 금속배선(20)의 자체 단차에 의해 형성된 제1내측패턴(19)과 제2내측패턴(21)이 정렬마크 및 중첩도 측정마크가 된다. (도 1d 참조).Then, the W layer is applied to the entire surface of the structure and a CMP process to form a W layer 18 inside the pattern to form a first inner pattern 19 (see FIG. 1C), and the metal of aluminum The wiring 20 is formed to form the second inner pattern 21. Here, the first inner pattern 19 and the second inner pattern 21 formed by the step between the W layer 18 and the metal wiring 20 become alignment marks and overlapping measurement marks. (See FIG. 1D).

상기와 같은 종래 기술에 따른 반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법은 W층이나 금속배선에 의해 형성되는 내측 패턴의 단차가 매우 적어 측정에 오차가 발생되고, 아예 측정이 되지 않는 공정수율 및 소자작동의 신뢰성을 떨어뜨리는 문제점이 있다.The manufacturing method of the alignment mark and the degree of overlap measurement of the semiconductor device according to the prior art as described above is a step in which an error occurs in the measurement because the step difference of the inner pattern formed by the W layer or the metal wiring is very small, and the measurement is not performed at all. There is a problem of lowering the yield and reliability of device operation.

본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본 발명의 목적은 W층 CMP나 금속배선 도포등과 같은 공정에서도 단차를 어느정도 이상으로 유지할 수 있어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법을 제공함에 있다.The present invention is to solve the above problems, the object of the present invention can maintain the step to a certain degree even in the process such as W layer CMP or metal wiring coating can improve the process yield and the reliability of device operation An object of the present invention is to provide a method of manufacturing an alignment mark and an overlapping measurement mark of a semiconductor device.

도 1a 내지 도 1d는 종래 기술에 따른 정렬마크 및 중첩도 측정마크의 제조공정도.1a to 1d is a manufacturing process diagram of the alignment mark and the degree of overlap measurement measurement according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 정렬마크 및 중첩도 측정마크의 제조공정도.Figure 2a to 2d is a manufacturing process diagram of the alignment mark and the degree of overlap measurement measurement in accordance with the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

10 : 반도체기판 12 : 필드산화막10: semiconductor substrate 12: field oxide film

14 : 질화막 16 : 층간절연막14 nitride film 16 interlayer insulating film

17 : 외곽패턴 18 : W층17: outer pattern 18: W floor

19 : 제1내측패턴 20 : 금속배선19: first inner pattern 20: metal wiring

21 : 제2내측패턴21: second inner pattern

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법의 특징은,Features of the manufacturing method of the alignment mark and the degree of overlap measurement of the semiconductor device according to the present invention for achieving the above object,

반도체기판의 일측에 형성되어 웨이퍼의 정렬이나 층간 오버레이를 측정하는 반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법에 있어서,In the manufacturing method of the alignment mark and the degree of overlap measurement of the semiconductor device formed on one side of the semiconductor substrate to measure the alignment or interlayer overlay of the wafer,

반도체기판의 마크 부분에 필드산화막과 필드산화막 에치 베리어용 질화막및 층간절연막을 순차적으로 형성하고, 상기 층간절연막의 상부를 평탄화시키는 공정과,Forming a field oxide film, a nitride film for an etch barrier and an interlayer insulating film in sequence on the mark portion of the semiconductor substrate, and planarizing an upper portion of the interlayer insulating film;

사진식각 공정을 진행하여 상기 마크 부분의 층간절연막과 질화막 및 필드산화막을 순차적으로 정렬마크 및 중첩도 측정마크의 외곽패턴을 형성하는 공정과,Performing a photolithography process to sequentially form the interlayer insulating film, the nitride film, and the field oxide film of the mark portion, the outer pattern of the alignment mark and the overlap measurement measurement mark;

상기 구조의 전표면에 W층 도포 및 평탄화로 상기 외곽패턴의 내측에 내부적으로 단차를 가지는 W층에 의해 제1내측패턴을 형성하는 공정과,Forming a first inner pattern by the W layer having a step internally inside the outer pattern by applying and planarizing the W layer on the entire surface of the structure;

상기 W층상에 단차진 표면을 가지는 금속배선을 형성하여 제2내측패턴을 형성하는 공정을 구비함에 있다.And forming a second inner pattern by forming a metal wiring having a stepped surface on the W layer.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing an alignment mark and an overlapping measurement mark of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 정렬마크 및 중첩도 측정마크의 제조 공정도이다.2A to 2D are manufacturing process diagrams of alignment marks and overlapping measurement marks of a semiconductor device according to the present invention.

먼저, 도 1a 에서와 같이 실리콘 웨이퍼등의 반도체기판(10)상에 소자분리 공정시 마크가 형성되는 부분에도 필드산화막(12)을 형성하고, 필드산화막(12) 에치 베리어가 되는 질화막(14)을 형성한 후, MOS 공정후에 전면에 층간절연막(16)을 형성하고, 상기 층간절연막(16)의 상부를 CMP로 평탄화한다. (도 2a 참조).First, as shown in FIG. 1A, a field oxide film 12 is formed on a portion where a mark is formed in a device separation process on a semiconductor substrate 10 such as a silicon wafer, and the nitride film 14 serving as an etch barrier of the field oxide film 12 is formed. After the MOS process, the interlayer insulating film 16 is formed on the entire surface after the MOS process, and the upper portion of the interlayer insulating film 16 is planarized to CMP. (See FIG. 2A).

그다음 마스크 공정을 실시하여 마크 부분의 층간절연막(16)과 질화막(14) 및 필드산화막(12)을 순차적으로 제거하여 반도체기판(10)을 노출시키는 정렬마크 및 중첩도 측정마크의 외곽패턴(17)을 형성하여 단차를 증가시킨 후, 다른 부분의 자기정렬콘택등과 같은 식각 공정시에는 마크 부분이 보호되도록 한다. (도 2b 참조).Then, a mask process is performed to sequentially remove the interlayer insulating film 16, the nitride film 14, and the field oxide film 12 of the mark portion, thereby revealing the alignment pattern 17 and the overlap pattern measuring mark exposing the semiconductor substrate 10. After the step is increased, the mark part is protected during an etching process such as a self-aligned contact of another part. (See FIG. 2B).

그다음 상기 구조의 전표면에 W층 도포 및 CMP 공정을 진행하여 상기 단차의 내측에 W층(18)을 형성하면, W층(18)의 내측에 제1내측패턴(19)이 형성되며, 이 제1내측패턴(19)은 필드산화막(12)이 제거된 부분만큼 내부적으로 큰 단차를 유지할 수 있고, (도 2c 참조), 연이어 알루미늄으로된 금속배선(20)을 형성하여도 마찬가지로 단차가 유지된 제2내측패턴(21)이 형성되어 상기 W층(18)과 금속배선(20)의 제1 및 제2내측패턴(19),(21)을 정렬마크 및 중첩도 측정마크로 용이하게 사용할 수 있다. (도 2d 참조).Then, the W layer coating and CMP processes are performed on the entire surface of the structure to form the W layer 18 inside the step, and the first inner pattern 19 is formed inside the W layer 18. The first inner pattern 19 may maintain a large step internally as much as the portion of the field oxide film 12 is removed (see FIG. 2C), and the step may be similarly maintained even when a metal wiring 20 made of aluminum is successively formed. Second inner pattern 21 is formed so that the first and second inner patterns 19 and 21 of the W layer 18 and the metal wiring 20 can be easily used as alignment marks and superimposition measurement marks. have. (See FIG. 2D).

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법은 필드산화막 에치 베리어인 질화막이 존재하는 경우 자기정렬콘택과 같은 별도의 식각 공정에서 마크 부분의 층간절연막과 질화막 및 필드산화막을 제거하여 반도체기판을 노출시키는 외곽마크를 큰 단차로 형성하고, 다른 부분의 식각 공정을 진행한 후, 그 내부를 채우는 W층을 형성하고, 금속배선 공정을 진행하였으므로, 버니어 패턴인 정렬마크 및 중첩도 측정마크의 외곽패턴의 단차가 증가되어 그 내측에 형성되는 정렬마크나 중첩도 측정마크가 단차가 유지되어 웨이퍼 정렬이나 층간 오버레이의 측정이 용이하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing the alignment mark and the overlap measurement mark of the semiconductor device according to the present invention, when the nitride film, which is a field oxide film etch barrier, is present, the interlayer insulating film of the mark portion in a separate etching process, such as a self-aligned contact, Since the nitride film and the field oxide film were removed to form an outline mark exposing the semiconductor substrate with a large step, the etching process of the other part was performed, the W layer filling the inside was formed, and the metal wiring process was performed. Increasing the level of the outer pattern of the alignment mark and the superimposition measurement mark, the alignment mark or the superimposition measurement mark formed therein is maintained so that the alignment of the alignment mark and the superimposition degree can be easily measured for wafer alignment or interlayer overlay. There is an advantage to improve.

Claims (1)

반도체기판의 일측에 형성되어 웨이퍼의 정렬이나 층간 오버레이를 측정하는 반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법에 있어서,In the manufacturing method of the alignment mark and the degree of overlap measurement of the semiconductor device formed on one side of the semiconductor substrate to measure the alignment or interlayer overlay of the wafer, 반도체기판의 마크 부분에 필드산화막과 필드산화막 에치 배리어용 질화막 및 층간절연막을 순차적으로 형성하고, 상기 층간절연막의 상부를 평탄화시키는 공정과,Forming a field oxide film, a field oxide film etch barrier nitride film, and an interlayer insulating film sequentially on the mark portion of the semiconductor substrate, and planarizing an upper portion of the interlayer insulating film; 사진식각 공정을 진행하여 상기 마크 부분의 층간절연막과 질화막 및 필드산화막을 순차적으로 정렬마크 및 중첩도 측정마크의 외곽패턴을 형성하는 공정과,Performing a photolithography process to sequentially form the interlayer insulating film, the nitride film, and the field oxide film of the mark portion, the outer pattern of the alignment mark and the overlap measurement measurement mark; 상기 구조의 전표면에 W층 도포 및 평탄화로 상기 외곽패턴의 내측에 내부적으로 단차를 가지는 W층에 의해 제1내측패턴을 형성하는 공정과,Forming a first inner pattern by the W layer having a step internally inside the outer pattern by applying and planarizing the W layer on the entire surface of the structure; 상기 W층상에 단차진 표면을 가지는 금속배선을 형성하여 제2내측패턴을 형성하는 공정을 구비하는 반도체소자의 정렬마크 및 중첩도 측정마크의 제조방법.And forming a second inner pattern by forming a metal wiring having a stepped surface on the W layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100607788B1 (en) * 2004-12-29 2006-08-02 동부일렉트로닉스 주식회사 Method for forming the overlay mark of semiconductor deivce

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100607788B1 (en) * 2004-12-29 2006-08-02 동부일렉트로닉스 주식회사 Method for forming the overlay mark of semiconductor deivce

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