KR20020096384A - Method for planation of Semiconductor Device - Google Patents

Method for planation of Semiconductor Device Download PDF

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Publication number
KR20020096384A
KR20020096384A KR1020010034796A KR20010034796A KR20020096384A KR 20020096384 A KR20020096384 A KR 20020096384A KR 1020010034796 A KR1020010034796 A KR 1020010034796A KR 20010034796 A KR20010034796 A KR 20010034796A KR 20020096384 A KR20020096384 A KR 20020096384A
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film
layer
buffer
semiconductor device
word line
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KR1020010034796A
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Korean (ko)
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김구영
송영택
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주식회사 하이닉스반도체
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Publication of KR20020096384A publication Critical patent/KR20020096384A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for planarizing a semiconductor device is provided to perform a uniform planarization in a chemical mechanical polishing(CMP) process without a loss of a mask nitride layer of a word line, by depositing an oxide nitride layer as a buffer layer such that the oxide nitride layer has a polishing rate slower than that of a plug formation layer. CONSTITUTION: The plug formation layer and the buffer layer are sequentially formed on the entire surface of a semiconductor substrate(100) having a self-aligned contact hole formed in an interlayer dielectric(130). A T-type mask is formed on the buffer layer. The buffer layer in a portion except a contact plug formation portion is removed by using the T-type mask. The T-type mask is eliminated. A CMP process is performed to planarize the upper portion of the word line.

Description

반도체소자의 평탄화 방법{Method for planation of Semiconductor Device}Method for planarization of semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 워드라인과 비트라인을 절연하기 위한 연마 공정에 있어서, 층간절연막 내에 셀프얼라인 콘택홀이 형성된 반도체기판 전체에 플러그형성막과 버퍼막을 순차적으로 적층하고, 감광막을 도포하여 콘택플러그 형성부위를 제외한 나머지 부분의 버퍼막을 제거한 후, 상기 감광막을 제거하고 화학기계적 연마 공정을 진행하여 평탄화함으로써, 상기 화학기계적 연마 시, 워드라인의 마스크질화막의 손실없이 균일하게 평탄화 할 수 있는 반도체소자의 평탄화방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, in a polishing process for insulating word lines and bit lines, a plug forming film and a buffer film are sequentially stacked on an entire semiconductor substrate having a self-aligned contact hole formed in an interlayer insulating film. After the photoresist is applied to remove the buffer layer except for the contact plug forming portion, the photoresist is removed and the chemical mechanical polishing process is performed to planarize the substrate. The present invention relates to a planarization method of a semiconductor device capable of flattening.

일반적으로, 집적도가 낮은 반도체소자는 단차가 작아 각 도전층들의 평탄화에 별다른 문제점이 없었으나, 소자가 고집적화되어 각층들간의 단차 및 적층되는 막의 수가 증가되면 소자의 제조 공정에서 나칭(notching)이나 단선등의 불량들이 발생하게 되며, 이를 방지하기 위하여 적층막들의 상부를 평탄화하는 공정이 공정수율 및 소자의 신뢰성에 중요한 영향을 미치게 된다.In general, a semiconductor device with low integration has a small level difference and thus there is no problem in planarization of each conductive layer. However, when the device is highly integrated and the number of steps and stacked films between the layers increases, notching or disconnection in the manufacturing process of the device Defects, etc. occur, and the process of planarizing the top of the stacked layers has a significant effect on the process yield and the reliability of the device in order to prevent this.

도 1a 내지 도 1c는 종래 반도체소자의 평탄화 방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A through 1C are cross-sectional views sequentially illustrating a planarization method of a conventional semiconductor device.

도 1a에 도시된 바와 같이, 워드라인이(20) 형성된 반도체기판(10) 전체에 질화물을 사용하여 난반사 방지막(30)을 형성한 후, 층간절연막(40)을 적층한다.As shown in FIG. 1A, after forming the anti-reflective film 30 using nitride on the entire semiconductor substrate 10 on which the word lines 20 are formed, the interlayer insulating film 40 is stacked.

그리고, 상기 층간절연막(40) 상에 T-type의 플러그 마스크(미도시함)를 형성한 후, 층간절연막(40)과 난반사 방지막(30)을 식각하여 셀프얼라인 콘택(50)을 형성한다.After forming a T-type plug mask (not shown) on the interlayer insulating layer 40, the interlayer insulating layer 40 and the diffuse reflection prevention layer 30 are etched to form a self-aligned contact 50. .

이어서, 도 1b에 도시된 바와 같이, 상기 셀프얼라인 콘택이 형성된 결과물전체에 플러그형성막을 적층한 후, 상기 워드라인 중 상부 마스크질화막까지 산화막용 슬러리를 이용하여 화학기계적 연마를 진행하여 평탄화 하였다.Subsequently, as shown in FIG. 1B, after the plug forming layer was stacked on the entire product formed with the self-aligned contact, chemical mechanical polishing was performed to the upper mask nitride layer of the word line using chemical slurry to planarize.

이때, 상기 셀프얼라인 콘택 지역과 층간절연막이 남아 있는 지역의 단차에 의해 플러그형성막 증착 시, 단차가 형성되었다.At this time, when the plug formation film is deposited by the step between the self-aligned contact area and the area where the interlayer insulating film remains, a step is formed.

그런데, 상기 셀프얼라인 콘택 지역과 층간절연막이 남아 있는 지역의 단차에 의해 플러그형성막 역시 단차가 형성됨으로써, 화학기계적 연마 시, 연마 균일도가 크게 떨어져서 "A"와 같이 셀프얼라인 콘택 영역이 과도하게 연마되며, 그 결과 워드라인 중 상부 마스크질화막이 손실되는 문제점이 있었다.However, the step of forming the plug forming film is also formed by the step between the self-aligned contact area and the region where the interlayer insulating film remains, so that the polishing uniformity is greatly reduced during chemical mechanical polishing, so that the self-aligned contact area is excessive as shown in "A". As a result, the upper mask nitride film is lost in the word line.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 워드라인과 비트라인을 절연하기 위한 연마 공정에 있어서, 층간절연막 내에 셀프얼라인 콘택홀이 형성된 반도체기판 전체에 플러그형성막과 버퍼막을 순차적으로 적층하고, 감광막을 도포하여 콘택플러그 형성부위를 제외한 나머지 부분의 버퍼막을 제거한 후, 상기 감광막을 제거하고 화학기계적 연마 공정을 진행하여 평탄화함으로써, 상기 화학기계적 연마 시, 워드라인의 마스크질화막의 손실없이 균일하게 평탄화 할 수 있도록 하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a plug in an entire semiconductor substrate in which a self-aligned contact hole is formed in an interlayer insulating film in a polishing process for insulating word lines and bit lines. The film and the buffer film are sequentially stacked and the photoresist film is applied to remove the buffer film except for the contact plug forming portion, and then the photoresist film is removed and the chemical mechanical polishing process is performed to planarize the word line. The purpose is to be able to planarize uniformly without losing the mask nitride film.

도 1a 내지 도 1b는 종래 반도체소자의 평탄화 방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A through 1B are cross-sectional views sequentially illustrating a planarization method of a conventional semiconductor device.

도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 평탄화 방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2D are cross-sectional views sequentially illustrating a planarization method of a semiconductor device according to the present invention.

-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-

100 : 반도체기판 110 : 워드라인100: semiconductor substrate 110: word line

120 : 난반사 방지막 130 : 층간절연막120: antireflection film 130: interlayer insulating film

140 : 셀프얼라인 콘택홀 150 : 플러그형성막140: self-aligned contact hole 150: plug formation film

160 : 버퍼막 170 : 감광막160: buffer film 170: photosensitive film

180 : 마스크질화막180: mask nitride film

상기 목적을 달성하기 위하여, 본 발명은 반도체소자의 워드라인과 비트라인을 절연하기 위한 연마 공정에 있어서, 층간절연막 내에 셀프얼라인 콘택홀이 형성된 반도체기판 전체에 플러그형성막과 버퍼막을 순차적으로 적층하는 단계와; 상기 버퍼막 상부에 티-타입 마스크를 형성한 후, 이를 이용하여 콘택플러그 형성부위를 제외한 나머지 부분의 버퍼막을 제거하는 단계와; 상기 티-타입 마스크를 제거한 후, 워드라인 상부까지 화학기계적 연마 공정을 진행하여 평탄화하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 평탄화방법을 제공한다.In order to achieve the above object, according to the present invention, a plug forming film and a buffer film are sequentially stacked on an entire semiconductor substrate having a self-aligned contact hole formed in an interlayer insulating film in a polishing process for insulating a word line and a bit line of a semiconductor device. Making a step; Forming a tee-type mask on the buffer layer, and then removing the buffer layer except for the contact plug forming portion using the tee-type mask; After removing the tee-type mask, a planarization method of the semiconductor device comprising the step of planarizing by performing a chemical mechanical polishing process to the upper part of the word line.

본 발명은 상기 플러그형성막보다 연마 속도가 느린 질화산화막으로 버퍼막을 더 증착하여 화학기계적 연마 공정을 진행함으로써, 상기 화학기계적 연마 시, 워드라인의 마스크질화막의 손실없이 균일하게 평탄화하는 것을 특징으로 한다.The present invention is characterized in that the chemical mechanical polishing process is performed by further depositing a buffer film with a nitride oxide film having a lower polishing speed than the plug forming film, so that the chemical mechanical polishing can be uniformly flattened without loss of the mask nitride film of the word line. .

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 평탄화 방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2D are cross-sectional views sequentially illustrating a planarization method of a semiconductor device according to the present invention.

도 2a에 도시된 바와 같이, 워드라인이(110) 형성된 반도체기판(100) 전체에 질화물을 사용하여 난반사 방지막(120)을 형성한 후, 층간절연막(130)을 적층한다.As shown in FIG. 2A, after the diffuse reflection prevention layer 120 is formed using nitride on the entire semiconductor substrate 100 on which the word lines 110 are formed, the interlayer insulating layer 130 is stacked.

이때, 상기 층간절연막(130)은 산화계 실리콘을 사용하여 적층한다.In this case, the interlayer insulating layer 130 is laminated using oxidized silicon.

그리고, 상기 층간절연막(130) 상에 T-type의 플러그 마스크(미도시함)를 형성한 후, 층간절연막(130)과 난반사 방지막(120)을 식각하여 셀프얼라인 콘택홀(140)을 형성한다.After forming a T-type plug mask (not shown) on the interlayer insulating layer 130, the self-aligned contact hole 140 is formed by etching the interlayer insulating layer 130 and the diffuse reflection prevention layer 120. do.

이어서, 도 2b에 도시된 바와 같이, 상기 셀프얼라인 콘택홀(미도시함)이 형성된 결과물 상에 플러그형성막(150)과 버퍼막(160)을 순차적으로 적층한다.Subsequently, as shown in FIG. 2B, the plug forming layer 150 and the buffer layer 160 are sequentially stacked on the resultant product having the self-aligned contact hole (not shown).

그리고, 상기 버퍼막(160)은 질화계 산화막을 이용하여 LPCVD방법 또는 PECVD방법 중 어느 하나의 방법을 선택하여 100∼2000Å의 두께로 증착한다.In addition, the buffer film 160 is deposited using a nitride oxide film, either LPCVD method or PECVD method, to a thickness of 100 to 2000 kPa.

그 후, 도 2c에 도시된 바와 같이, 상기 버퍼막(160) 상부에 감광막(170)를 형성하여, 콘택플러그 형성부위를 제외한 나머지 부분의 버퍼막(160)을 습식식각 또는 건식식각하여 제거한다.Thereafter, as shown in FIG. 2C, the photoresist layer 170 is formed on the buffer layer 160, and the remaining portion of the buffer layer 160 except for the contact plug forming portion is removed by wet etching or dry etching. .

계속하여, 도 2d에 도시된 바와 같이, 상기 감광막(미도시함)을 제거한 후, 상기 워드라인(110) 중 상부 마스크질화막(180)까지 폴리계의 슬러리를 이용하여 화학기계적 연마를 진행함으로써 평탄화한다.Subsequently, as shown in FIG. 2D, the photoresist film (not shown) is removed and then planarized by chemical mechanical polishing using a poly-based slurry to the upper mask nitride film 180 of the word line 110. do.

이때, 상기 화학기계적 연마 시, 단차가 높은 플러그형성막(130)이 버퍼막보다 연마속도가 빨라 워드라인의 마스크질화막(180)의 손실없이 균일한 두께로 평탄화된다.At this time, during the chemical mechanical polishing, the plug forming film 130 having a high step is planarized to a uniform thickness without losing the mask nitride film 180 of the word line because the polishing speed is higher than that of the buffer film.

따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 평탄화방법을 이용하게 되면, 워드라인과 비트라인을 절연하기 위한 연마 공정에 있어서, 층간절연막 내에 셀프얼라인 콘택홀이 형성된 반도체기판 전체에 플러그형성막과 버퍼막을 순차적으로 적층하고, 감광막을 도포하여 콘택플러그 형성부위를 제외한 나머지 부분의 버퍼막을 제거한 후, 상기 감광막을 제거하고 화학기계적 연마 공정을 진행하여평탄화함으로써, 상기 화학기계적 연마 시, 단차가 높은 플러그형성막이 버퍼막보다 연마속도가 빨라 워드라인의 마스크질화막의 손실없이 균일한 두께로 평탄화 할 수 있도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the method of planarizing the semiconductor device according to the present invention is used, in the polishing process for insulating the word line and the bit line, a plug is formed on the entire semiconductor substrate having the self-aligned contact hole formed in the interlayer insulating film. After forming the forming film and the buffer film sequentially, applying a photosensitive film to remove the remaining buffer film except for the contact plug forming portion, and then removing the photosensitive film and performing a chemical mechanical polishing process to flatten the step, It is a very useful and effective invention that a high plug forming film has a higher polishing rate than a buffer film so that it can be planarized to a uniform thickness without loss of a mask nitride film of a word line.

Claims (5)

반도체소자의 워드라인과 비트라인을 절연하기 위한 연마 공정에 있어서,In the polishing process for insulating the word line and bit line of the semiconductor device, 층간절연막 내에 셀프얼라인 콘택홀이 형성된 반도체기판 전체에 플러그형성막과 버퍼막을 순차적으로 적층하는 단계와;Sequentially depositing a plug formation film and a buffer film on the entire semiconductor substrate having a self-aligned contact hole in the interlayer insulating film; 상기 버퍼막 상부에 티-타입 마스크를 형성한 후, 이를 이용하여 콘택플러그 형성부위를 제외한 나머지 부분의 버퍼막을 제거하는 단계와;Forming a tee-type mask on the buffer layer, and then removing the buffer layer except for the contact plug forming portion using the tee-type mask; 상기 티-타입 마스크를 제거한 후, 워드라인 상부까지 화학기계적 연마 공정을 진행하여 평탄화하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 평탄화방법.And removing the tee-type mask, and performing a chemical mechanical polishing process to the upper part of the word line to planarize the semiconductor device. 제 1항에 있어서, 상기 층간절연막은 산화계 실리콘으로 이루어진 것을 특징으로 하는 반도체소자의 평탄화방법.The method of claim 1, wherein the interlayer insulating film is made of silicon oxide oxide. 제 1항에 있어서, 상기 버퍼막은 질화계 산화막을 이용하여 LPCVD방법 또는 PECVD방법 중 어느 하나의 방법을 선택하여 증착하는 것을 특징으로 하는 반도체소자의 평탄화방법.The method of claim 1, wherein the buffer film is deposited by selecting any one of an LPCVD method and a PECVD method using a nitride oxide film. 제 1항 또는 제 3항에 있어서, 상기 버퍼막은 100∼2000Å의 두께로 증착하는 것을 특징으로 하는 반도체소자의 평탄화방법.4. The method of claim 1 or 3, wherein the buffer film is deposited to a thickness of 100 to 2000 microseconds. 제 1항에 있어서, 상기 화학기계적 연마 시, 폴리계의 슬러리를 사용하여 연마하는 것을 특징으로 하는 반도체소자의 평탄화방법.The method of claim 1, wherein the chemical mechanical polishing is performed using a poly slurry.
KR1020010034796A 2001-06-19 2001-06-19 Method for planation of Semiconductor Device KR20020096384A (en)

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