KR20020095508A - method of fabricating a liquid crystal display - Google Patents
method of fabricating a liquid crystal display Download PDFInfo
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- KR20020095508A KR20020095508A KR1020010033455A KR20010033455A KR20020095508A KR 20020095508 A KR20020095508 A KR 20020095508A KR 1020010033455 A KR1020010033455 A KR 1020010033455A KR 20010033455 A KR20010033455 A KR 20010033455A KR 20020095508 A KR20020095508 A KR 20020095508A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
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- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 액정표시장치의 제조방법에 관한 것으로, 보다 상세하게는 감광막패턴을 마스크로 하여 금속막을 패턴 식각하여 데이타라인 및 소오스/드레인전극을 형성할 경우, 감광막패턴과 금속막 간의 접착력을 향상시킬 수 있는 액정표시장치의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a liquid crystal display device, and more particularly, to form a data line and a source / drain electrode by pattern etching a metal film using a photoresist pattern as a mask, thereby improving adhesion between the photoresist pattern and the metal film. The present invention relates to a method for manufacturing a liquid crystal display device.
도 1a 내지 도 1d는 종래기술에 따른 액정표시장치의 제조공정도이고, 도 2는 도 1a에서 A의 부분확대도이다. 그리고 도 3은 종래기술에 따른 문제점을 보이기 위한 도면이다.1A to 1D are manufacturing process diagrams of a liquid crystal display device according to the prior art, and FIG. 2 is a partially enlarged view of A of FIG. 1A. 3 is a view for showing a problem according to the prior art.
종래기술에 따른 액정표시장치의 제조방법은, 도 1a에 도시된 바와 같이, 글라스기판(100) 상에 비정질실리콘층(102)을 증착한 다음, 스퍼터링(sputtering)에 의해 Mo/Al/Mo을 연속적으로 증착하여 다중의 금속막(104)을 형성한다.In the method of manufacturing a liquid crystal display according to the related art, as shown in FIG. 1A, an amorphous silicon layer 102 is deposited on a glass substrate 100, and then Mo / Al / Mo is formed by sputtering. By depositing successively, a plurality of metal films 104 are formed.
이 후, 순수(DeIonized water) 공급(110)에 의해 상기 금속막(104)의 표면의 파티클(particle)을 제거하여 세정처리한다. 상기 세정처리된 금속막(104) 표면을 살펴보게 되면, 도 2에 도시된 도면부호 120처럼, 표면거칠기가 미세하게 나타난다. 이때, 상기 금속막(104)의 접촉각(contact angle)이 2∼3도 가량된다.Thereafter, particles of the surface of the metal film 104 are removed and cleaned by a deionized water supply 110. Looking at the surface of the cleaned metal film 104, as shown in FIG. 2, the surface roughness is minute. At this time, the contact angle of the metal film 104 is about 2 to 3 degrees.
이어서, 도 1b에 도시된 바와 같이, 금속막 상에 감광막을 도포한 다음, 소정영역을 잔류시키도록 노광 및 현상하여 감광막 패턴(108)을 형성한다.Subsequently, as illustrated in FIG. 1B, a photosensitive film is coated on the metal film, and then exposed and developed to leave a predetermined area to form the photosensitive film pattern 108.
그 다음, 감광막 패턴(108)을 마스크로 이용하여 금속막을 1차 식각하여 데이타라인(data line)(104a)를 형성한다.Next, the metal film is first etched using the photoresist pattern 108 as a mask to form a data line 104a.
이 후, 도면에는 도시되어 있지 않지만, 상기 감광막 패턴(108)을 에싱하여 채널영역에 대응되는 부분을 제거한 다음, 이를 마스크로 하여 상기 금속막을 2차 식각하여 소오스/드레인전극을 형성한다.Subsequently, although not shown in the drawing, the photoresist pattern 108 is removed to remove portions corresponding to the channel regions, and then the metal layer is secondly etched to form a source / drain electrode.
이어서, 도 1c에 도시된 바와 같이, 감광막 패턴(108)을 마스크로 하여 비정질실리콘층을 식각하여 활성층(103)을 형성한다.Subsequently, as shown in FIG. 1C, the amorphous silicon layer is etched using the photoresist pattern 108 as a mask to form the active layer 103.
그 다음, 도 1d에 도시된 바와 같이, 감광막 패턴을 제거한다.Then, as shown in Fig. 1D, the photoresist pattern is removed.
이 후, 도면에 도시되지 않았지만, 소오스/드레인전극을 덮도록 보호막을 증착한 후, 상기 보호막을 식각하여 드레인전극과 대응된 부분을 노출시키는 개구부를 형성하고, 상기 개구부를 덮어 드레인전극과 전기적으로 연결되는 화소전극을 형성한다.Subsequently, although not shown in the drawings, a protective film is deposited to cover the source / drain electrodes, and then, the protective film is etched to form an opening that exposes a portion corresponding to the drain electrode, and covers the opening to electrically connect the drain electrode. A pixel electrode to be connected is formed.
그러나, 종래기술에 따른 액정표시장치의 제조방법은, 도 3에 도시된 바와 같이, 감광막 패턴을 이용하여 금속막 및 비정질실리콘층에 케미컬(chemical)에 의한 습식 식각 공정을 진행할 경우, 금속막과 감광막 패턴 간의 접착 불량에 의해 케미컬이 감광막 패턴이 떨어져 나감으로써 원하는 패터닝을 얻을 수 없는 문제점이 있었다.However, the manufacturing method of the liquid crystal display according to the prior art, as shown in Figure 3, when performing a wet etching process by a chemical (chemical) to the metal film and the amorphous silicon layer using a photosensitive film pattern, There was a problem in that the desired patterning could not be obtained because the chemical fell off the photoresist pattern due to poor adhesion between the photoresist patterns.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 감광막 패턴과 금속막 간의 접착력을 향상시킬 수 있는 액정표시장치의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a liquid crystal display device capable of improving the adhesive force between the photosensitive film pattern and the metal film.
도 1a 내지 도 1d는 종래기술에 따른 액정표시장치의 제조공정도.1A to 1D are manufacturing process diagrams of a liquid crystal display device according to the prior art.
도 2는 도 1a에서 A의 부분확대도.2 is an enlarged partial view of A in FIG. 1A;
도 3은 종래기술에 따른 문제점을 보이기 위한 도면.3 is a view for showing a problem according to the prior art.
도 4a 내지 도 4d는 본 발명에 따른 박막트랜지스터의 제조공정도.4a to 4d is a manufacturing process diagram of a thin film transistor according to the present invention.
도 5는 도 4a에서 B의 부분확대도.5 is an enlarged partial view of B in FIG. 4A;
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
200. 글라스기판 202. 비정질실리콘층200. Glass substrate 202. Amorphous silicon layer
204. 금속막 204a. 데이타라인204. Metal film 204a. Data line
208. 감광막 패턴 210. BOE케미컬 공급208. Photoresist pattern 210. BOE chemical supply
상기 목적을 달성하기 위한 본 발명의 박막트랜지스터의 제조방법은 글라스기판 상에 비정질실리콘층과 금속막을 순차적으로 형성하는 단계와, 금속막의 표면거칠기를 증가시키는 단계와, 표면거칠기가 증가된 금속막 상에 제 1마스크패턴을 형성하는 단계와, 제 1마스크 패턴을 이용하여 금속막을 1차 식각하여 데이타라인을 형성하는 단계와, 제 1마스크 패턴을 이용하여 비정질실리콘층을 식각하여 활성층을 형성하는 단계와, 제 1마스크패턴을 에싱처리하여 비정질실리콘층의 채널영역을 노출시키는 제 2마스크패턴을 형성하는 단계와, 제 2마스크패턴을 이용하여 잔류된 금속막을 2차로 식각하여 소오스/드레인전극을 형성하는 단계와, 제 2감광막 패턴을 제거하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a thin film transistor of the present invention includes sequentially forming an amorphous silicon layer and a metal film on a glass substrate, increasing the surface roughness of the metal film, and increasing the surface roughness on the metal film. Forming a first mask pattern on the substrate, first etching the metal layer using the first mask pattern to form a data line, and etching the amorphous silicon layer using the first mask pattern to form an active layer And forming a second mask pattern for exposing the channel region of the amorphous silicon layer by ashing the first mask pattern, and secondly etching the remaining metal film using the second mask pattern to form source / drain electrodes. And removing the second photoresist pattern.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 4a 내지 도 4d는 본 발명에 따른 박막트랜지스터의 제조공정도이고, 도 5는 도 4a에서 B의 부분확대도이다.4A to 4D are manufacturing process diagrams of the thin film transistor according to the present invention, and FIG. 5 is a partially enlarged view of B in FIG. 4A.
본 발명에 따른 액정표시장치의 제조방법은, 도 4a에 도시된 바와 같이, 먼저 글라스기판(200) 상에 비정질실리콘층(102)과 금속막(104)를 순차적으로 형성한다. 상기 금속막(104)으로는 Mo/Al/Mo, Mo/AlNd/Mo, Cr/Al 또는 Cr/AlNd 중 어느 하나의 다중막을 스퍼터링에 의해 증착하여 이용한다.In the method of manufacturing a liquid crystal display according to the present invention, as shown in FIG. 4A, first, an amorphous silicon layer 102 and a metal film 104 are sequentially formed on a glass substrate 200. As the metal film 104, a multilayer film of any one of Mo / Al / Mo, Mo / AlNd / Mo, Cr / Al, or Cr / AlNd is deposited and used by sputtering.
이 후, BOE(Buffer Oxide Etchant)케미컬 공급(210)을 실시하여 금속막(204)을 계면처리한다. 상기 금속막(204)의 계면처리는 먼저, BOE를 100:1비율로 하여 금속막을 세정한 다음, 상기 세정처리된 금속막을 BOE를 6:3비율로 하여 처리함으로써, 도 5에 도시된 바와 같이, 표면거칠기를 증가시킨다.Thereafter, BOE (Buffer Oxide Etchant) chemical supply 210 is performed to interface the metal film 204. In the interfacial treatment of the metal film 204, first, the metal film is washed with a BOE ratio of 100: 1, and then the washed metal film is treated with a BOE ratio of 6: 3, as shown in FIG. , Increase surface roughness.
이때, 상기 금속막(204)의 계면처리는 300초 이하로 진행시킨다.At this time, the interfacial treatment of the metal film 204 proceeds to 300 seconds or less.
상기 세정처리된 금속막(204) 표면을 살펴보게 되면, 도 5에 도시된 도면부호 220처럼, 표면거칠기가 증가된 것을 알 수 있다. 상기 금속막(204)의 접촉각은 7도 이상된다.Looking at the surface of the cleaned metal film 204, it can be seen that the surface roughness is increased, as shown by 220 shown in FIG. The contact angle of the metal film 204 is 7 degrees or more.
이어서, 도 4b에 도시된 바와 같이, 표면거칠기가 증가된 금속막 상에 감광막을 도포한 다음, 소정영역을 잔류시키도록 노광 및 현상하여 감광막 패턴(208)을 형성한다.Subsequently, as illustrated in FIG. 4B, a photoresist film is coated on the metal film having an increased surface roughness, and then exposed and developed to leave a predetermined region to form a photoresist pattern 208.
그 다음, 감광막 패턴(208)을 마스크로 이용하여 금속막을 1차 식각하여 데이타라인(204a)를 디파인(define)한다.Next, the metal film is first etched using the photoresist pattern 208 as a mask to define the data line 204a.
이 후, 도면에는 도시되어 있지 않지만, 상기 감광막 패턴(208)을 에싱처리하여 채널영역에 대응되는 부분을 제거한 다음, 이를 마스크로 하여 상기 금속막을 2차 식각하여 소오스/드레인전극을 형성한다.Subsequently, although not shown in the drawing, the photoresist pattern 208 is subjected to an ashing process to remove portions corresponding to the channel regions, and then the metal layer is etched second to form a source / drain electrode.
상기 금속막의 1차, 2차 식각은 건식 식각 또는 습식 식각방법을 이용한다.The primary and secondary etching of the metal film uses a dry etching method or a wet etching method.
이어서, 도 4c에 도시된 바와 같이, 감광막 패턴(208)을 마스크로 하여 비정질실리콘층을 식각하여 활성층(203)을 형성한다.Subsequently, as shown in FIG. 4C, the amorphous silicon layer is etched using the photoresist pattern 208 as a mask to form the active layer 203.
그 다음, 도 4d에 도시된 바와 같이, 감광막 패턴을 제거한다.Then, as shown in Fig. 4D, the photoresist pattern is removed.
상기에서 언급한 바와 같이, 본 발명은 금속막의 표면을 BOE 케미컬에 의한 계면처리를 실시하여 표면거칠기를 증가시킴으로써, 감광막 패턴 간의 접촉면적을 크게하여 접착력을 향상시킨다.As mentioned above, in the present invention, the surface of the metal film is subjected to an interfacial treatment with BOE chemical to increase the surface roughness, thereby increasing the contact area between the photosensitive film patterns, thereby improving adhesion.
이상에서와 같이, 본 발명은 금속막에 BOE케미컬에 의한 계면처리를 실시하여 금속막의 표면거칠기를 증가시킴으로써, 금속막과 감광막 패턴 간의 접촉면적을 크게한다. 따라서, 감광막 패턴과 금속막 간의 접착력을 향상시킬 수 있다.As described above, the present invention increases the surface roughness of the metal film by performing an interfacial treatment with the BOE chemical on the metal film, thereby increasing the contact area between the metal film and the photosensitive film pattern. Therefore, the adhesive force between the photosensitive film pattern and a metal film can be improved.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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Cited By (2)
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---|---|---|---|---|
KR100813358B1 (en) * | 2003-01-27 | 2008-03-12 | 샤프 가부시키가이샤 | Liquid crystal display having aluminum wiring |
CN116013853A (en) * | 2023-03-27 | 2023-04-25 | 合肥晶合集成电路股份有限公司 | Method for preparing interconnection structure |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5817419A (en) * | 1981-07-24 | 1983-02-01 | Toshiba Corp | Liquid crystal display device |
KR100251091B1 (en) * | 1996-11-29 | 2000-04-15 | 구본준 | Method of manufacturing liquid crystal display device and liquid crystal display device |
KR100338011B1 (en) * | 1999-06-30 | 2002-05-24 | 윤종용 | a manufacturing method of panels for liquid crystal displays |
KR100586240B1 (en) * | 2000-05-18 | 2006-06-02 | 엘지.필립스 엘시디 주식회사 | Method for fabricating the array substrate for LCD and the same |
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2001
- 2001-06-14 KR KR10-2001-0033455A patent/KR100507279B1/en active IP Right Grant
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100813358B1 (en) * | 2003-01-27 | 2008-03-12 | 샤프 가부시키가이샤 | Liquid crystal display having aluminum wiring |
CN116013853A (en) * | 2023-03-27 | 2023-04-25 | 合肥晶合集成电路股份有限公司 | Method for preparing interconnection structure |
CN116013853B (en) * | 2023-03-27 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Method for preparing interconnection structure |
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