KR20020093868A - Method of surface treatment of semiconductor - Google Patents
Method of surface treatment of semiconductor Download PDFInfo
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- KR20020093868A KR20020093868A KR1020027012943A KR20027012943A KR20020093868A KR 20020093868 A KR20020093868 A KR 20020093868A KR 1020027012943 A KR1020027012943 A KR 1020027012943A KR 20027012943 A KR20027012943 A KR 20027012943A KR 20020093868 A KR20020093868 A KR 20020093868A
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- reaction chamber
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- longitudinal direction
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004381 surface treatment Methods 0.000 title claims description 7
- 239000007789 gas Substances 0.000 claims abstract description 64
- 238000006243 chemical reaction Methods 0.000 claims abstract description 61
- 235000012431 wafers Nutrition 0.000 claims abstract description 55
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 239000007795 chemical reaction product Substances 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- 239000002826 coolant Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 230000005284 excitation Effects 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000000112 cooling gas Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000012495 reaction gas Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 19
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 238000001816 cooling Methods 0.000 description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000002156 mixing Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910017855 NH 4 F Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000005281 excited state Effects 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
본 발명은 마이크로웨이브로 여기되는 반응가스를 이용하여 반도체장치의 콘택트 홀로부터 자연산화막을 제거하기 위한 방법을 제공한다. 이 방법은 생산량을 증가시킨다. 반응가스가 종방향으로 정렬되고 323K 이하의 온도로 유지되는 다수의 반도체 실리콘 웨이퍼(10)의 회전중에 반응실(20)의 종방향으로 연장되고 반응실의 내부압력 보다 압력이 높은 챔버(5, 22)를 통하여 반응실(20)에 수평방향으로 도입되고, 이후에 상기 반응실이 약 373K 이상으로 가열된다.The present invention provides a method for removing a native oxide film from a contact hole of a semiconductor device by using a reaction gas excited by microwaves. This method increases output. The chamber 5 extending in the longitudinal direction of the reaction chamber 20 and having a pressure higher than the internal pressure of the reaction chamber during the rotation of the plurality of semiconductor silicon wafers 10 in which the reaction gases are aligned in the longitudinal direction and maintained at a temperature of 323 K or less. 22) is introduced into the reaction chamber 20 in the horizontal direction, after which the reaction chamber is heated to about 373 K or more.
Description
종래 콘택트 홀에 형성되는 자연산화막은 화학적인 드라이 에칭 또는 IPA(이소프로필 알코올) 세정방법에 의하여 제거되었다. 그러나, 이러한 방법은 콘택트 홀의 크기가 현저히 적아지고 애스팩트비가 커지는 현재의 상황에서는 더 이상 적용될 수 없다. 일본국 특허공개공보 5-275392에는 반도체 실리콘 웨이퍼(이하 간단히 '웨이퍼'라 함)용으로 사용되는 시이트형의 자연산화막제거장치가 기술되어 있다. 상기 특허문헌에 있어서, 자연산화막은 서셉터에 의하여 웨이퍼를 약 173K(-100℃)로 냉각시킨 상태에서 플라즈마 여기된 NF3와 H2의 가스혼합물을 하류측 반응실에 유입시킴으로서 에칭된다. 이러한 에칭공정은 (NH4)2SiF6또는 유사한 물질이 웨이퍼에 형성될 때 중단될 수 있다. 그리고, 이러한 에칭공정을 다시 시작하기 위하여 웨이퍼가 불활성 Ar 플라즈마로 조사된다.The natural oxide film formed in the conventional contact hole has been removed by chemical dry etching or IPA (isopropyl alcohol) cleaning. However, this method can no longer be applied in the present situation where the size of the contact hole becomes significantly smaller and the aspect ratio becomes larger. Japanese Patent Laid-Open No. 5-275392 describes a sheet type natural oxide film removing apparatus used for a semiconductor silicon wafer (hereinafter simply referred to as a "wafer"). In this patent document, the native oxide film is etched by introducing a gas mixture of plasma-excited NF 3 and H 2 into the downstream reaction chamber while the wafer is cooled to about 173 K (-100 ° C.) by a susceptor. This etching process can be stopped when (NH 4 ) 2 SiF 6 or similar material is formed on the wafer. Then, the wafer is irradiated with an inert Ar plasma to restart this etching process.
또한 NF3와 NH3를 이용하여 SiO2의 자연산화막을 에칭하는 방법이 발표된 바 있다(1999 DRY PROCESS SYMPOSSIUM, In-situ observation of Si Native Oxide Removal Empolying Hot NF3/NH3Exposure, Ogawa et al. pp.273-278). 상기 논문에서는 웨이퍼에 형성된 자연산화막은 100℃ 이상의 온도에서 (NH4)2SiF6를 해리하여 제거된다. 또한 상기 논문에서는 반응생성물이 NH4F·HF 또는 NH4F인 것으로 추정하고 있다. 다음의 설명에서 원료가스의 반응생성물을 에칭가스라 하였다.In addition, a method of etching a natural oxide film of SiO 2 using NF 3 and NH 3 has been published (1999 DRY PROCESS SYMPOSSIUM, In-situ observation of Si Native Oxide Removal Empolying Hot NF 3 / NH 3 Exposure, Ogawa et al. pp. 273-278). In this paper, the native oxide film formed on the wafer is removed by dissociating (NH 4 ) 2 SiF 6 at a temperature of 100 ° C. or higher. The paper also assumes that the reaction product is NH 4 F.HF or NH 4 F. In the following description, the reaction product of the raw material gas was called an etching gas.
종래의 시이트형 자연산화막 제거방법에 있어서는 냉각과정, 플라즈마 에칭과정 및 반응생성물을 제거하는 과정을 포함하는 반응시간이 웨이퍼당 약 4분이다. 그리고, 웨이퍼의 출입에 소요되는 오버헤드 시간을 포함하는 요구된 전체 반응시간은 약 7분이다. 이와 같이, 자연산화막을 제거하기 위한 전체 공정은 각 웨이퍼를 출입시키는데 소요되는 오버헤드 시간이 포함됨으로서 제조라인에 병목현상을 일으킨다. 이러한 문제점은 감압CVD방법과 같은 수직배치방법이 자연산화막을 제거하는데 이용되는 경우에 해소될수는 있으나 현재 이러한 방법이 제안된 바는 없다. 아울러, 통상적인 시이트형 자연산화막 제거방법에 있어서는 에칭속도를 높이므로서 요구된 처리시간을 단축시키기 위하여 서셉터를 이용해 웨이퍼를 293K 이하로 냉각시키는 것이 절대적으로 필요하다. 그러나 이러한 냉각기술은 복잡한 냉각시스템을 이용하여야 한다.In the conventional sheet type natural oxide film removal method, a reaction time including a cooling process, a plasma etching process, and a process of removing a reaction product is about 4 minutes per wafer. The required total reaction time, including the overhead time required for entry and exit of the wafer, is about 7 minutes. As such, the entire process for removing the native oxide film is a bottleneck in the manufacturing line by including the overhead time required to enter and exit each wafer. This problem can be solved when a vertical arrangement method such as a reduced pressure CVD method is used to remove the native oxide film, but this method has not been proposed at present. In addition, in the conventional sheet type natural oxide film removal method, it is absolutely necessary to cool the wafer to 293K or less using a susceptor in order to shorten the required processing time while increasing the etching rate. However, this cooling technique requires the use of complex cooling systems.
본 발명은 반도체의 표면처리방법에 관한 것이다. 특히, 본 발명은 실리콘 웨이퍼상에 반도체장치를 제조하는 공정에서 폴리실리콘, 도프드 폴리실리콘, 금속, TiSi2, WSi2또는 TiN과 같은 전극물질을 매입하기 위하여 사용되는 반도체장치의 콘택트 홀에 노출된 실리콘에 형성되는 자연산화막 또는 레지스트와 실리콘의 반응에 의하여 생성된 스컴 등을 제거하는 드라이 에칭방법에 관한 것이다.The present invention relates to a surface treatment method of a semiconductor. In particular, the present invention is exposed to contact holes in semiconductor devices used to embed electrode materials such as polysilicon, doped polysilicon, metal, TiSi 2 , WSi 2 or TiN in the process of manufacturing semiconductor devices on silicon wafers. The present invention relates to a dry etching method for removing scum and the like formed by a reaction between a natural oxide film or a resist formed on silicon and a resist and silicon.
도 1은 본 발명의 제1관점에 따른 방법을 수행하기 위하여 사용되는 장치의 종단면도.1 is a longitudinal sectional view of an apparatus used to carry out a method according to the first aspect of the invention.
도 2는 도 1의 A-A선 단면도.2 is a cross-sectional view taken along the line A-A of FIG.
도 3은 본 발명의 제2관점에 따른 방법을 수행하기 위하여 사용되는 장치의 종단면도.3 is a longitudinal sectional view of an apparatus used to carry out a method according to the second aspect of the invention.
도 4는 간접냉각가스방법을 설명하는 도 1의 제1챔버의 부분확대 사시도.4 is a partially enlarged perspective view of the first chamber of FIG. 1 illustrating an indirect cooling gas method;
도 5는 도 4의 V-V선 단면도.5 is a cross-sectional view taken along the line V-V in FIG. 4.
따라서, 본 발명의 목적은 높은 처리속도 또는 재현성을 가지고 1~2시간내에 한번에 50장 이상, 특히 100장 이상의 웨이퍼를 처리할 수 있는 처리방법을 제공함으로서 상기 언급된 문제점을 해소하는데 있다.Accordingly, it is an object of the present invention to solve the above-mentioned problems by providing a processing method capable of processing 50 or more wafers, in particular 100 or more wafers at once, within 1-2 hours with high processing speed or reproducibility.
본 발명의 제1관점에 따라서, 콘택트 홀에 자연산화막 또는 스컴이 형성된 반도체 실리콘 웨이퍼를 수용하는 반응실에서 수소, 암모니아 및 질소로부터 선택된 적어도 하나의 가스를 포함하는 제1마이크로웨이브 여기가스와 탄소 또는 산소를 전혀 포함하지 않는 불소함유화합물의 제2가스의 반응생성물에 의하여 반도체의 표면을 처리하는 방법을 제공하는 바, 종방향으로 정렬되고 323K 이하의 온도로 유지되는 다수의 반도체 실리콘 웨이퍼가 회전되는 동안에 상기 반응생성물이 반응실의 종방향으로 연장되고 반응실의 내부압력 보다 압력이 높은 챔버를 통하여 반응실에 수평방향으로 도입되고, 이후에 상기 반도체 실리콘 웨이퍼가 약 373K 이상으로 가열됨을 특징으로 한다.According to a first aspect of the present invention, a first microwave excitation gas and carbon containing at least one gas selected from hydrogen, ammonia and nitrogen in a reaction chamber containing a semiconductor silicon wafer having a natural oxide film or scum formed in a contact hole, or A method of treating a surface of a semiconductor by a reaction product of a second gas of a fluorine-containing compound containing no oxygen, wherein a plurality of semiconductor silicon wafers aligned in the longitudinal direction and maintained at a temperature of 323 K or less are rotated. During which the reaction product extends in the longitudinal direction of the reaction chamber and is introduced horizontally into the reaction chamber through a chamber having a pressure higher than the internal pressure of the reaction chamber, after which the semiconductor silicon wafer is heated to at least about 373K. .
본 발명의 제1관점의 방법에 있어서, 제1가스는 (a) 반응실의 종방향으로 연장되게 배열되고 (b) 이후 상세히 설명되는 바와 같이 종방향으로 배열되고 제2챔버에 대하여 개방된 다수의 제1분출구를 갖는 제1챔버에 주입되고, 제2가스는 (c) 반응실의 종방향으로 연장되게 배열되고 (d) 종방향으로 배열되고 반응실에 대하여 개방된 다수의 제2분출구를 갖는 제2챔버에 주입되며, (e) 상기 제2챔버의 내부압력이 제1챔버의 내부압력과 반응실의 내부압력 사이이다.In the method of the first aspect of the invention, the first gas is (a) arranged to extend in the longitudinal direction of the reaction chamber and (b) a plurality of longitudinally arranged and open to the second chamber as described in detail below. The second gas is injected into a first chamber having a first outlet of and the second gas is (c) arranged to extend in the longitudinal direction of the reaction chamber and (d) a plurality of second outlets arranged in the longitudinal direction and open to the reaction chamber. And (e) the internal pressure of the second chamber is between the internal pressure of the first chamber and the internal pressure of the reaction chamber.
본 발명의 제2관점에 있어서, 상기 언급된 범주의 방법이 제공되는 바, 종방향으로 정렬되고 323K 이하의 온도로 유지되는 다수의 반도체 실리콘 웨이퍼가 회전되는 동안에, 제1가스가 (a) 반응실의 종방향으로 연장되게 배열되고 (b) 종방향으로 배열되고 반응실에 대하여 개방된 다수의 제1분출구를 갖는 제1챔버에 주입되며 (c) 상기 제1챔버의 내부압력이 반응실의 내부압력 보다 높고, 제2가스가 (d) 반응실의 종방향으로 연장되게 배열되고 (e) 종방향으로 배열되고 반응실에 대하여 개방된 다수의 제2분출구를 갖는 제2챔버에 주입되며 (f) 상기 제2챔버의 내부압력이 반응실의 내부압력 보다 높고, 이후에 상기 반도체 실리콘 웨이퍼가 약 373K 이상으로 가열됨을 특징으로 한다.In a second aspect of the present invention, a method of the above-mentioned category is provided wherein during the rotation of a plurality of semiconductor silicon wafers that are aligned in the longitudinal direction and maintained at a temperature of 323 K or less, the first gas reacts with (a) (B) injected into a first chamber having a plurality of first outlets arranged longitudinally and open to the reaction chamber, and (c) an internal pressure of the first chamber Higher than the internal pressure, a second gas is injected into the second chamber (d) arranged to extend in the longitudinal direction of the reaction chamber and (e) arranged in the longitudinal direction and having a plurality of second outlets open to the reaction chamber ( f) the internal pressure of the second chamber is higher than the internal pressure of the reaction chamber, after which the semiconductor silicon wafer is heated to about 373K or more.
이하 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail.
본 발명에 따른 방법은 종방향으로 적층된 50~100장의 웨이퍼를 처리할 수 있게 되어 있다.The method according to the invention is able to process 50 to 100 wafers stacked in the longitudinal direction.
종래의 시이트형 자연산화막제거방법에 있어서는 에칭속도를 높이기 위하여 웨이퍼가 전형적으로 173K(-100℃)로 냉각된다. 그러나, 본 발명에 따라서는 온도가 323K 이하일 때에 처리상의 문제가 야기되지 않으므로 배치처리의 경우에 웨이퍼가 특별히 냉각될 필요는 없다. 만약 마이크로웨이브 회로의 임피던스 부정합으로 온도가 323K 이상 높아지는 경우 웨이퍼를 서셉터를 이용하여 냉각시키는 것이 어려우므로 통상의 방법과는 다르게 본 발명에 따라서는 웨이퍼가 액체질소의 기화가스를 이용하여 303~318K 사이의 온도로 냉각된다. 본 발명에 따라서, 비록 웨이퍼의 표면이 실온과 323K의 온도범위에서 처리될 수는 있으나 본 발명의 방법에 이용될 수 있는 최저웨이퍼온도가 253K이므로 웨이퍼가 253~323K의 온도범위에서 표면처리될 수 있다. 반응시스템에 주입되는 냉각매체가 웨이퍼 온도(373K 이상) 보다 현저히 낮은 온도로 냉각되고 반응시스템의 압력과 배기펌프의 압력이 일정한 관계를 유지할 때 웨이퍼 온도는 만족스러운 정도의 재현성을 가지고 효과적으로 제어될 수 있다.In the conventional sheet type natural oxide film removal method, the wafer is typically cooled to 173 K (-100 ° C.) in order to increase the etching rate. However, according to the present invention, no processing problem is caused when the temperature is 323 K or less, so that the wafer does not need to be cooled particularly in the case of batch processing. If the temperature rises above 323K due to impedance mismatch in the microwave circuit, it is difficult to cool the wafer using a susceptor. Cooled to a temperature between. According to the present invention, although the surface of the wafer can be processed at room temperature and in the temperature range of 323K, the wafer can be surface treated in the temperature range of 253 ~ 323K because the lowest wafer temperature that can be used in the method of the present invention is 253K. have. The wafer temperature can be effectively controlled with satisfactory reproducibility when the cooling medium injected into the reaction system cools significantly below the wafer temperature (above 373K) and the pressure of the reaction system and the exhaust pump pressure remain constant. have.
가스냉각방식은 물과 같은 냉각매체를 제1 또는 제2챔버의 벽에 흘려 제1가스 또는 제2가스의 온도를 323K 이하로 유지할 수 있도록 하는 간접냉각방식으로 대체될 수 있다.The gas cooling method may be replaced by an indirect cooling method in which a cooling medium such as water flows on the wall of the first or second chamber to maintain the temperature of the first gas or the second gas at 323 K or less.
본 발명에 따른 에칭에 이용되는 챔버(제1 및 제2챔버)는 상대측에 대하여 내부가스 압력차를 보이고 또한 반응실의 내부압력과도 압력차를 보이며 가스가 유입 및 저장되었다가 분출될 수 있는 튜브 또는 캐비넷일 수 있다. 이러한 압력차에 의하여 챔버내의 래디컬, 분자 및 원자는 균일한 분포를 보인다. 가스는 제1챔버와 제2챔버 사이의 내부가스 압력차가 400Pa(3 torr)~1.3KPa(10 torr)일 때 균일한 농도로 다수의 웨이퍼측으로 유동될 수 있게 된다. 각 챔버는 공유하는 통공에 의하여 서로 연통하고 독립된 각각의 통공을 통하여 낮은 압력으로 유지된 반응실과 연통된다. 압력차는 통공의 직경을 차등화함으로서 나타날 수 있다. 반응실의 내부가스압력은 일반적으로 133Pa(1 torr)~400Pa(3 torr) 사이이다.The chambers (first and second chambers) used for etching according to the present invention show an internal gas pressure difference with respect to the other side, and a pressure difference with the internal pressure of the reaction chamber, and gas can be introduced, stored, and ejected. It can be a tube or a cabinet. Due to this pressure difference, radicals, molecules and atoms in the chamber have a uniform distribution. The gas may be flowed to the plurality of wafers at a uniform concentration when the internal gas pressure difference between the first chamber and the second chamber is 400 Pa (3 torr) to 1.3 KPa (10 torr). Each chamber is in communication with the reaction chamber maintained at a low pressure through each of the independent through-hole communication through a common through-hole. The pressure difference can be seen by differentiating the diameter of the through hole. The internal gas pressure of the reaction chamber is generally between 133 Pa (1 torr) and 400 Pa (3 torr).
제1 및 제2챔버는 반응실의 종방향으로 연장되게 배열되고반응실내에서 종방향으로 적층된 웨이퍼의 전체 높이와 동일한 길이를 갖는다. 그리고 에칭가스는 최소의 이동거리에서 균일하게 웨이퍼에 공급된다. 각 챔버에는 다수의 통공이 종방향으로 배열되어 있어 가스가 최소의 이동거리에서 수평으로 웨이퍼의 펴면에 주입될 수 있다.각 챔버의 분출구는 적층된 웨이퍼의 각 높이에 일치하도록 배열된다.The first and second chambers are arranged to extend in the longitudinal direction of the reaction chamber and have a length equal to the overall height of the wafers stacked longitudinally in the reaction chamber. The etching gas is uniformly supplied to the wafer at the minimum travel distance. Each chamber is arranged with a plurality of apertures in the longitudinal direction so that gas can be injected into the unfolded surface of the wafer horizontally at the minimum travel distance. The outlets of each chamber are arranged to match the respective heights of the stacked wafers.
제1가스와 제2가스를 혼합시키는 다음중의 어떠한 방식도 본 발명의 목적을 위하여 이용될 수 있다.Any of the following ways of mixing the first gas and the second gas may be used for the purposes of the present invention.
(a) 제1가스와 제2가스가 챔버측으로 연장된 파이프내에서 혼합되거나 제1가스가 제1챔버로 유입되고 제2챔버에서 생성된 에칭가스가 반응실의 내부공간으로 주입된다(본 발명의 제1관점에서). 이러한 혼합방식에 있어서는 제1챔버의 내부압력이 제2챔버 보다 높은 반면에 제2챔버의 내부압력은 반응실 보다 높다. 이러한 혼합방식에 있어서, 제2챔버는 2cm 이하의 간극을 두고 반응실의 웨이퍼에 근접되게 배치되는 것이 좋다.(a) The first gas and the second gas are mixed in a pipe extending to the chamber side or the first gas is introduced into the first chamber and the etching gas generated in the second chamber is injected into the inner space of the reaction chamber (the present invention) From the first point of view). In this mixing method, the internal pressure of the first chamber is higher than that of the second chamber while the internal pressure of the second chamber is higher than that of the reaction chamber. In this mixing method, the second chamber is preferably disposed close to the wafer of the reaction chamber with a gap of 2 cm or less.
(b) 제1분출구로부터 분출되는 제1가스와 제2분출구로부터 분출되는 제2가스는 반응실의 내부공간에서 혼합된다(본 발명의 제2관점에서). 이러한 혼합방식에서, 비록 에칭가스가 비교적 광범위하게 상하로 분류되기는 하나 생성된 에칭가스가 웨이퍼의 콘택트 홀에 접촉되는데 요구된 시간은 크게 단축된다.(b) The first gas ejected from the first outlet and the second gas ejected from the second outlet are mixed in the interior space of the reaction chamber (in the second aspect of the present invention). In this mixing mode, although the etching gas is classified relatively broadly up and down, the time required for the generated etching gas to contact the contact hole of the wafer is greatly shortened.
8~12 인치 웨이퍼의 경우, 일반적으로 자연산화막은 두께가 20 옹스트롬 이하이고 이러한 두께의 변화량은 2~10 옹스트롬이다. 만약 자연산화막이 0~5 옹스트롬의 막두께로 콘택트 홀에 형성되는 경우, 표면은 목표값으로서 5 옹스트롬이 에칭된다. 만약 자연산화막이 두꺼운 경우에는 제1가스에 알곤이 혼합되고 마이크로웨이브로 여기된 알곤에 의하여 반응속도가 상승된다.In the case of 8 to 12 inch wafers, the natural oxide film generally has a thickness of 20 angstroms or less and the variation in thickness is 2 to 10 angstroms. If a native oxide film is formed in the contact hole with a film thickness of 0 to 5 angstroms, the surface is etched 5 angstroms as a target value. If the natural oxide film is thick, argon is mixed with the first gas and the reaction rate is increased by argon excited by microwaves.
계속하여, 에칭가스를 배기한 후 (NH4)2SiF6또는 유사한 물질의 착체가 반응실의 내부를 가열함으로서 에칭가스로부터 해리된다. 따라서, 착체가가 제거되고 Si 표면에 하이드로겐 터미네이션(Si-H 결합)이 형성된다.Subsequently, after the etching gas is exhausted, a complex of (NH 4 ) 2 SiF 6 or a similar material is released from the etching gas by heating the inside of the reaction chamber. Thus, the complex value is removed and hydrogen termination (Si-H bond) is formed on the Si surface.
본 발명은 첨부도면에 의거하여 상세히 설명된다. 도 1과 도 2는 본 발명의 제1관점에 따른 방법을 설명하고 도 3은 본 발명의 제1관점에 따른 방법을 설명한다.The invention is explained in detail on the basis of the accompanying drawings. 1 and 2 illustrate a method according to the first aspect of the present invention and FIG. 3 illustrates a method according to the first aspect of the present invention.
도 2과 도 2는 도시를 간단히 하고 설명을 용이하게 하기 위하여 적은 수의 웨이퍼가 적층되어 있는 것을 보이고 있다. 도 1과 도 2는 내부압력이 약 0.8KPa(5 torr)~1.3KPa(10 torr)인 제1챔버(5), 웨이퍼(10), 내부압력이 0.13Pa(10-3torr)~1.3KPa(10 torr)인 반응실(20)과, 내부압력이 400Pa(3 torr)~600Pa(5 torr)인 제2챔버(22)를 보이고 있다.2 and 2 show that a small number of wafers are stacked for simplicity of illustration and ease of explanation. 1 and 2 show the first chamber 5, the wafer 10, and the internal pressure of about 0.1 kPa (10 −3 torr) to about 1.3 KPa having an internal pressure of about 0.8 KPa (5 torr) to 1.3 KPa (10 torr). The reaction chamber 20 of (10 torr) and the second chamber 22 having an internal pressure of 400 Pa (3 torr) to 600 Pa (5 torr) are shown.
반응실(20)은 폐쇄상부를 가지고 저면판(12)에 의하여 폐쇄되고 종방향으로 10~50mm의 간격을 두고 배열된 다수의 12 인치 웨이퍼(10)를 수용하는 개방저면부를 갖는 알루미늄 튜브(8)의 구조로 되어 있다. 웨이퍼는 회전축(9a)에 고정되고에칭가스와 균일하게 반응하도록 회전축(9a)에 의하여 회전구동될 수 있게 된 지그(9)에 의하여 종방향으로 고정되어 있다. 전형적으로 H2와 N2의 혼합가스인 제1가스는 1ℓ/분의 유량으로 입력포트(1)를 통하여 제1챔버(5)로 유입될 수 있게 되어 있으며, 예를 들어 제1챔버의 내부압력은 665Pa(5 torr)~2.6KPa(20 torr)의 레벨로 유지된다. 도 1과 도 2에서, 부호 6과 7은 각각 제1챔버(5)를 구성하는 격판과 제1챔버의 캐비넷의 외벽을 나타내며 이들은 각각 미세입자의 발생을 억제할 수 있도록 알루미늄 재질로 되어 있다. 제1챔버(5)에는 상부에 사파이어 창(4)이 구비되어 있으며, 제1챔버의 내측의 제1가스는 출력레벨이 400W이고 주파수가 2.45GHz이며 사파이어 창을 통하여 전달되는 마이크로웨이브에 의하여 여기된다. 도 1과 도2에서 부호 3은 마이크로웨이브 도파관이다. 다른 한편으로 제2가스는 100~300cc/분의 유량으로 유입포트(2)를 통하여 제2챔버(22)로 유입되며, 이 제2챔버(22)에는 전기적으로 비전도성인 산화알루미늄판(16)과 알루미늄판(6)을 포함하는 격벽이 구비되어 있다. 제1가스는 직경이 0.5~1.0mm이고 수직으로 배열된 다수의 통공(제1분출구)(6a)를 통하여 제2챔버(22)로 유동하고 수직으로 배열된 다수의 통공(제2분출구)(22a)를 통하여 반응실(20)로 유동한다. 통공(22a)과 웨이퍼(10)는 10~20mm의 거리를 두고 떨어져 있으며 통공(22a)의 수는 웨이퍼의 수보다 작거나 같다. 통공(22a)의 수는 웨이퍼의 수의 1/3 이상인 것이 좋다.The reaction chamber 20 has a closed top and an aluminum tube 8 having an open bottom which is closed by the bottom plate 12 and accommodates a plurality of 12 inch wafers 10 arranged at intervals of 10 to 50 mm in the longitudinal direction. ) Structure. The wafer is fixed in the longitudinal direction by a jig 9 which is fixed to the rotating shaft 9a and can be rotated by the rotating shaft 9a so as to react uniformly with the etching gas. The first gas, typically a mixture of H 2 and N 2 , can be introduced into the first chamber 5 through the input port 1 at a flow rate of 1 l / min, for example, inside the first chamber. Pressure is maintained at levels between 665 Pa (5 torr) and 2.6 KPa (20 torr). 1 and 2, reference numerals 6 and 7 represent the diaphragms constituting the first chamber 5 and the outer wall of the cabinet of the first chamber, respectively, which are each made of aluminum so as to suppress the generation of fine particles. The first chamber (5) is provided with a sapphire window (4) at the top, the first gas inside the first chamber is excited by a microwave transmitted through the sapphire window with an output level of 400W and a frequency of 2.45GHz do. In FIG. 1 and FIG. 2, the code | symbol 3 is a microwave waveguide. On the other hand, the second gas flows into the second chamber 22 through the inlet port 2 at a flow rate of 100 to 300 cc / min, and the second chamber 22 has an electrically nonconductive aluminum oxide plate 16. ) And an aluminum plate 6 is provided. The first gas flows to the second chamber 22 through a plurality of vertically arranged through holes (first outlets) 6a having a diameter of 0.5 to 1.0 mm and is arranged vertically through a plurality of through holes (second outlets) ( It flows into the reaction chamber 20 through 22a). The through hole 22a and the wafer 10 are separated by a distance of 10 to 20 mm, and the number of the through holes 22a is smaller than or equal to the number of wafers. The number of through holes 22a is preferably 1/3 or more of the number of wafers.
이러한 가스주입단계에서, 에칭가스는 비록 약간은 상하로 유동하기는 하나 실질적으로 수평으로 유동하여 반응성이 높은 발생초기의 에칭가스가 웨이퍼(10)에 공급된다. 자연산화막이 제거되는 속도는 특히 통공(22a)과 웨이퍼(10)가 10~20mm의 거리를 두고 서로 떨어져 있을 때 웨이퍼의 간격(d)에 의하여 영향을 받는다. 자연산화막의 제거속도는 d=15~30mm일 때 0.5nm(5 옹스트롬)~1nm(10 옹스트롬)/분이다. 실리콘/자연산화막 에칭선택비는 약 1/6이므로 에칭의 변화폭이 큰 경우 대규모 접촉이 이루어질 수 있도록 할 필요가 없다. 반응후, 에칭가스는 반응실(20)로부터 외측으로 연장된 캐비넷(11)내에 잠시 수집되었다가 펌프에 연결된 배기파이프(13)와 밸브(14)를 통하여 배기된다. 도 1에서 부호 15는 압력계를 나타낸다.In this gas injection step, the etching gas flows substantially horizontally although slightly flows up and down, so that the initial generation of highly reactive etching gas is supplied to the wafer 10. The rate at which the natural oxide film is removed is particularly affected by the gap d of the wafer when the through hole 22a and the wafer 10 are separated from each other at a distance of 10 to 20 mm. The removal rate of the native oxide film is 0.5 nm (5 angstroms) to 1 nm (10 angstroms) / minute when d = 15 to 30 mm. Since the silicon / natural oxide etch selectivity is about 1/6, it is not necessary to make a large contact when the etching variation is large. After the reaction, the etching gas is briefly collected in the cabinet 11 extending outward from the reaction chamber 20 and then exhausted through the exhaust pipe 13 and the valve 14 connected to the pump. In Fig. 1, reference numeral 15 denotes a pressure gauge.
반응실(20)내의 웨이퍼(10)는 기화된 액화질소와 같은 냉각가스를 가스유입포트(1) 또는 가스유입포트(2) 또는 특별히 제공된 가스유입포트(도시하지 않았음)를 통하여 반응실(20)로 유동시켜 실온이하의 온도로 냉각될 수 있다. 아울러, 반응후, 반응실(20)내의 웨이퍼(10)가 반응실(20)내에 배치된 램프(30)에 의하여 약 373K의 온도로 가열될 때 착체의 해리가 촉진되고 입자생성이 방지된다. 웨이퍼(10)는 가열을 위한 별도의 장치로 옮겨질 수 있다.The wafer 10 in the reaction chamber 20 carries a cooling gas such as vaporized liquid nitrogen through the gas inlet port 1 or the gas inlet port 2 or a specially provided gas inlet port (not shown). 20) to cool down to room temperature. In addition, after the reaction, when the wafer 10 in the reaction chamber 20 is heated to a temperature of about 373K by the lamp 30 disposed in the reaction chamber 20, dissociation of the complex is promoted and particle formation is prevented. Wafer 10 may be transferred to a separate device for heating.
도 3은 본 발명의 제1관점에 따른 방법을 수행하기 위하여 사용되는 장치를 단면으로 보인 것이다. 도 3에서의 구성요소중에서 도 1의 구성요소와 동일 또는 유사한 것에 대하여서는 동일한 부호를 붙였다. 도 3에서 보인 바와 같이, 제2챔버(22)는 서로 약 5~10mm의 간극을 두고 반응실(10)의 제1챔버(5)에 인접하여 배치되어 있다.3 shows in cross section an apparatus used for carrying out the method according to the first aspect of the invention. The same reference numerals are given to the same or similar components as those in FIG. As shown in FIG. 3, the second chamber 22 is disposed adjacent to the first chamber 5 of the reaction chamber 10 with a gap of about 5 to 10 mm from each other.
제1가스와 제2가스는 수평방향으로 유동하는 중에 서로 혼합되어 에칭가스를 생성하고 웨이퍼(10)와 간격을 두고 있는 공간을 통하여 배기파이프(13)로 흡인되는 과정에서 반응실의 웨이퍼(10)와 반응한다.The first gas and the second gas are mixed with each other while flowing in the horizontal direction to generate an etching gas and sucked into the exhaust pipe 13 through a space spaced from the wafer 10. React).
도 4와 도 5는 283K~288K사이 온도의 물을 챔버의 벽중에서 하나에 형성된 냉각매체유로(32)를 통하여 흘려 보냄으로서 반응생성물과 가스를 냉각하는 방법을 보이고 있다. 특히, 냉각매체유로(32)는 역 U자 형으로 되어 있고 분출구(6a)를 둘러싸도록 제1챔버(5)의 격판(6)에 배치되어 있다. 냉각수에 의하여 간접작으로 냉각되는 마이크로웨이브 여기가스가 그 여기상태를 잃지 않고 제1챔버(22)내의 NF3와 반응할 수 있게 되어 있다. 또한 반응생성물이 실온 보다 약간 낮은 온도에서 웨이퍼(10)와 접촉한다.4 and 5 show a method of cooling the reaction product and the gas by flowing water at a temperature between 283 K and 288 K through a cooling medium flow path 32 formed in one of the walls of the chamber. In particular, the cooling medium flow path 32 has an inverted U shape and is disposed in the diaphragm 6 of the first chamber 5 so as to surround the jet port 6a. The microwave excitation gas cooled indirectly by the cooling water can react with NF 3 in the first chamber 22 without losing its excited state. The reaction product also contacts the wafer 10 at a temperature slightly below room temperature.
이와 같이, 본 발명은 배치방식으로 자연산화막을 제거함으로서 반도체장치의 생산량을 크게 증가시킬 수 있도록 한다.As described above, the present invention makes it possible to greatly increase the yield of the semiconductor device by removing the natural oxide film in a batch manner.
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| JP2000090884A JP2001284307A (en) | 2000-03-29 | 2000-03-29 | Surface treatment method of semiconductor |
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| JP2003086569A (en) * | 2001-09-12 | 2003-03-20 | Tokyo Electron Ltd | Method for plasma treatment |
| KR100829327B1 (en) | 2002-04-05 | 2008-05-13 | 가부시키가이샤 히다치 고쿠사이 덴키 | Substrate processing apparatus and reaction tube |
| US7028356B2 (en) * | 2002-11-26 | 2006-04-18 | Ge Medical Systems Global Technology Company, Llc | Multiconfiguration braking system |
| JP4329403B2 (en) * | 2003-05-19 | 2009-09-09 | 東京エレクトロン株式会社 | Plasma processing equipment |
| KR101025323B1 (en) | 2004-01-13 | 2011-03-29 | 가부시키가이샤 아루박 | Etching apparatus and etching method |
| JP4495470B2 (en) * | 2004-01-13 | 2010-07-07 | 三星電子株式会社 | Etching method |
| JP4987219B2 (en) * | 2004-01-13 | 2012-07-25 | 三星電子株式会社 | Etching equipment |
| JP4495472B2 (en) * | 2004-01-13 | 2010-07-07 | 三星電子株式会社 | Etching method |
| JP4987220B2 (en) * | 2004-01-13 | 2012-07-25 | 三星電子株式会社 | Etching equipment |
| JP4475136B2 (en) | 2005-02-18 | 2010-06-09 | 東京エレクトロン株式会社 | Processing system, pre-processing apparatus and storage medium |
| JP4712806B2 (en) * | 2005-08-15 | 2011-06-29 | 株式会社エフティーエル | Semiconductor surface treatment method |
| JP4746581B2 (en) * | 2007-04-12 | 2011-08-10 | 株式会社日立国際電気 | Substrate processing equipment |
| WO2009001774A1 (en) * | 2007-06-22 | 2008-12-31 | Ulvac, Inc. | Method for protecting semiconductor wafer and process for producing semiconductor device |
| US20090017637A1 (en) * | 2007-07-10 | 2009-01-15 | Yi-Chiau Huang | Method and apparatus for batch processing in a vertical reactor |
| US20090197424A1 (en) * | 2008-01-31 | 2009-08-06 | Hitachi Kokusai Electric Inc. | Substrate processing apparatus and method for manufacturing semiconductor device |
| JP5284182B2 (en) * | 2008-07-23 | 2013-09-11 | 株式会社日立国際電気 | Substrate processing apparatus and semiconductor device manufacturing method |
| CN103184434B (en) * | 2011-12-31 | 2016-08-10 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Pallet apparatus, pallet and semiconductor processing equipment |
| TWI604528B (en) * | 2012-10-02 | 2017-11-01 | 應用材料股份有限公司 | Directional sio2 etch using plasma pre-treatment and high-temperature etchant deposition |
| US11703229B2 (en) * | 2018-12-05 | 2023-07-18 | Yi-Ming Hung | Temperature adjustment apparatus for high temperature oven |
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| JPH04296021A (en) * | 1991-03-26 | 1992-10-20 | Mitsubishi Electric Corp | Surface treatment method for semiconductor substrate |
| DE4132559A1 (en) * | 1991-09-30 | 1993-04-08 | Siemens Ag | Plasma etching in-situ cleaning process for vacuum deposition chambers - with separate plasma discharge excitation of etch gas and admission of activated etch gas to chamber |
| JP2896005B2 (en) * | 1992-02-06 | 1999-05-31 | シャープ株式会社 | Wafer cleaning method |
| JPH06120188A (en) * | 1992-10-09 | 1994-04-28 | Kawasaki Steel Corp | Thermal oxidation method |
| US5556275A (en) * | 1993-09-30 | 1996-09-17 | Tokyo Electron Limited | Heat treatment apparatus |
| JPH07169693A (en) * | 1993-12-16 | 1995-07-04 | Mitsubishi Electric Corp | Horizontal low-pressure cvd device and its cleaning method |
| US5775889A (en) * | 1994-05-17 | 1998-07-07 | Tokyo Electron Limited | Heat treatment process for preventing slips in semiconductor wafers |
| US6171982B1 (en) * | 1997-12-26 | 2001-01-09 | Canon Kabushiki Kaisha | Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same |
| US6204194B1 (en) * | 1998-01-16 | 2001-03-20 | F.T.L. Co., Ltd. | Method and apparatus for producing a semiconductor device |
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