KR20020083572A - chip scale package and method of fabricating the same - Google Patents

chip scale package and method of fabricating the same Download PDF

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Publication number
KR20020083572A
KR20020083572A KR1020010022949A KR20010022949A KR20020083572A KR 20020083572 A KR20020083572 A KR 20020083572A KR 1020010022949 A KR1020010022949 A KR 1020010022949A KR 20010022949 A KR20010022949 A KR 20010022949A KR 20020083572 A KR20020083572 A KR 20020083572A
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South Korea
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chip
ball
substrate
size package
wiring
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KR1020010022949A
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Korean (ko)
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KR100417854B1 (en
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김재면
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A CSP(Chip Scale Package) and a method for manufacturing the same are provided to improve a reliability and to simplify manufacturing processes without using a bonding process of a metal wire. CONSTITUTION: Each bump ball(106) is attached to a plurality of chip pads(102) formed in a wafer(100). An adhesive(104) is coated to expose the bump balls(106). Through holes(108) are formed in a substrate(120). An interconnection(122) having a metal ring is formed on the substrate(120). A protection layer(136) is formed on the interconnection(122) so as to expose a ball land(124) and the thorough hole(108). The substrate(120) is then bonded to the adhesive(104). A conductive layer(112) is formed on the through hole(108) so as to connect between the bump balls(106) and the interconnection(122). A conductive ball(134) is bonded on the ball land(124). The resultant structure is sawed to a unit chip.

Description

칩크기 패키지 구조 및 그 제조방법{chip scale package and method of fabricating the same}Chip scale package structure and method of manufacturing the same {chip scale package and method of fabricating the same}

본 발명은 패키지(package) 구조 및 그 제조방법에 관한 것으로, 보다 상세하게는 반도체 칩과 기판을 전기적으로 연결시키는 금속와이어의 본딩 공정을 생략하여 제조공정을 단순화하여 제품의 신뢰성이 우수한 칩크기(chip scale)의 패키지 구조 및 그 제조방법에 관한 것이다.The present invention relates to a package structure and a method of manufacturing the same. More particularly, the chip size simplifies the manufacturing process by omitting the bonding process of the metal wires electrically connecting the semiconductor chip and the substrate. It relates to a package structure (chip scale) and a method of manufacturing the same.

일반적으로 널리 알려진 바와 같이, 웨이퍼의 박막 성장 기법에 의해 제조된 칩(chip)을 웨이퍼로부터 절단(sawing)분리한 다음, 분리된 칩을 실드(shield)나 몰딩(molding)으로 외부의 습기나 불순물로부터 보호되고 또한 외부회로와의 접속을 위한 리드를 부착한 패키지 형태로 상품화된다.As is generally known, chips produced by a thin film growth technique of a wafer are sawed from a wafer, and then the separated chips are shielded or molded, thereby preventing external moisture or impurities. It is commercialized in the form of a package that is protected from and has a lead attached for connection to an external circuit.

이러한 패키지중 대부분의 공간을 칩이 차지하는 정도의 크기로 몰딩되는 칩크기의 패키지는 그 자체가 단일한 미소 소자(micro device)로 상품화되어 회로기판에 있어서의 실장밀도를 높이고 응용 주문형 집적회로(ASIC:Application Specific IC)등 각종 집적회로에서의 집적도를 높이는 데 유용하다.Chip-sized packages, which are molded to the extent that the chip takes up most of the space, are themselves commercialized as a single micro device, which increases the mounting density of the circuit board and the application specific integrated circuit (ASIC). It is useful for increasing the degree of integration in various integrated circuits such as application specific ICs.

도 1은 종래의 일 실시예에 따른 엘오씨(Lead On Chip)타입의 칩크기 패키지의 단면도이다.1 is a cross-sectional view of a chip size package of a lead on chip type according to a conventional embodiment.

종래의 제 1실시예에 따른 칩크기 패키지는, 도 1에 도시된 바와 같이, 배선(15)이 형성된 기판(12)과, 상면 가장자리 부분에 다수의 칩패드(11)가 형성된 반도체 칩(10)과, 기판(12)과 반도체 칩(10) 사이에 개재되는 접착테이프(14)와, 칩패드(11)와 배선(15)을 연결시키는 금속와이어(13)와, 배선(15)에 부착되는 도전성 볼(17)로 구성된다.As shown in FIG. 1, the chip size package according to the first exemplary embodiment may include a substrate 12 having a wiring 15 formed thereon and a semiconductor chip 10 having a plurality of chip pads 11 formed on an upper edge thereof. ), The adhesive tape 14 interposed between the substrate 12 and the semiconductor chip 10, the metal wire 13 connecting the chip pad 11 and the wiring 15, and the wiring 15. It consists of the electroconductive balls 17 which become.

상기 구성을 갖는 종래의 제 1실시예에 따른 칩크기 패키지의 제조방법은, 기판(12)에 접착테이프(14)를 이용하여 반도체 칩(10)을 부착시킨 다음, 반도체 칩(10)의 칩패드(11)와 기판(12)의 배선(15)과의 전기적 연결을 위하여 금속와이어(13)를 형성한다.In the manufacturing method of the chip size package according to the first embodiment having the above configuration, the semiconductor chip 10 is attached to the substrate 12 using the adhesive tape 14, and then the chip of the semiconductor chip 10 is attached. The metal wire 13 is formed to electrically connect the pad 11 and the wiring 15 of the substrate 12.

이 후, 외부의 먼지나 습기를 차단하기 위해, 금속와이어(13) 및 반도체 칩(10)을 덮도록 몰딩체(19)를 형성한 다음, 외부와의 전기적 연결을 위하여 기판(12)의 배선(15) 상에 솔더볼(17)을 부착시키어 패키지 제조를 완료한다.Thereafter, the molding body 19 is formed to cover the metal wire 13 and the semiconductor chip 10 to block external dust or moisture, and then the wiring of the substrate 12 for electrical connection with the outside. Attaching the solder ball 17 on the (15) to complete the package manufacturing.

도 2는 종래의 다른 실시예에 따른 BGA(Ball Grid Aray)타입의 칩크기 패키지의 단면도이다.2 is a cross-sectional view of a chip size package of a ball grid array (BGA) type according to another exemplary embodiment of the present invention.

종래의 제 1실시예에 따른 칩크기 패키지는, 도 2에 도시된 바와 같이, 배선(25)이 형성된 기판(22)과, 상면 중심부분에 다수의 칩패드(21)가 형성된 반도체 칩(20)과, 기판(22) 상에 반도체 칩(20)의 칩패드(21)가 형성된 면을 부착시키기 위한 접착테이프(24)와, 칩패드(21)와 배선(25)을 연결시키는 금속와이어(23)와, 배선(25) 상에 부착되는 도전성 볼(27)로 구성된다.As shown in FIG. 2, the chip size package according to the first exemplary embodiment may include a substrate 22 having a wiring 25 and a semiconductor chip 20 having a plurality of chip pads 21 formed at a central portion of an upper surface thereof. ), An adhesive tape 24 for attaching the surface on which the chip pad 21 of the semiconductor chip 20 is formed on the substrate 22, and a metal wire connecting the chip pad 21 and the wiring 25 ( 23 and conductive balls 27 attached to the wiring 25.

상기 구성을 갖는 종래의 제 2실시예에 따른 칩크기 패키지의 제조방법은, 접착테이프(24)를 이용하여 기판(22) 상에 반도체 칩(20)의 칩패드(21)가 형성된 면을 부착시킨 후, 금속와이어(23)에 의해 칩패드(21)와 배선(25)을 전기적으로 연결시킨다.In the manufacturing method of the chip size package according to the second embodiment having the above structure, the surface on which the chip pad 21 of the semiconductor chip 20 is formed on the substrate 22 using the adhesive tape 24 is attached. After that, the chip pad 21 and the wiring 25 are electrically connected by the metal wires 23.

이어서, 금속와이어(23) 및 반도체 칩(20)을 덮도록 몰딩체(29)를 형성한 다음, 외부와의 전기적 연결을 위하여 배선(25) 상에 솔더볼(27)을 부착시키어 패키지 제조를 완료한다.Subsequently, the molding body 29 is formed to cover the metal wires 23 and the semiconductor chip 20, and then the solder balls 27 are attached to the wirings 25 for electrical connection with the outside to complete the package manufacturing. do.

그러나, 종래의 제 1, 제 2실시예에서는 반도체 칩과 기판과의 전기적인 연결을 위해 금속와이어를 형성함으로써, 금속와이어의 길이만큼 전기적 연결길이가 증가하게되어 금속와이어로부터 발생되는 커패시턴스(capacitance), 인덕턴스(inductance) 및 레지스턴스(resistance)가 증가하게 된다. 따라서, 신호전달이 지연되고 노이즈(noise)가 발생되어 제품의 동작 특성을 저하시킨다.However, in the first and second embodiments of the related art, since the metal wire is formed for the electrical connection between the semiconductor chip and the substrate, the electrical connection length is increased by the length of the metal wire, thereby generating capacitance from the metal wire. Inductance and resistance will increase. Therefore, signal transmission is delayed and noise is generated, which lowers the operating characteristics of the product.

또한, 종래의 제 1, 제 2실시예에서는 금속와이어의 사용함으로써, 금속와이어를 외부로부터 보호하기 위한 몰딩체 형성 공정이 수반되어야 하므로, 공정이 복잡해질 뿐더러, 실제적인 칩크기의 패키지를 구현할 수 없는 문제점이 발생되었다.In addition, in the first and second embodiments of the related art, by using a metal wire, a molding body forming process for protecting the metal wire from the outside must be involved, which not only complicates the process but also realizes a practical chip size package. There was no problem.

이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 반도체 칩과 기판을 전기적으로 연결시키는 금속와이어의 본딩 공정을 생략하여 제조공정을 단순화하여 제품의 신뢰성이 우수한 칩크기 패키지 구조를 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems, to omit the bonding process of the metal wire to electrically connect the semiconductor chip and the substrate to simplify the manufacturing process to provide a chip size package structure with excellent product reliability. The purpose is.

또한, 본 발명의 다른 목적은 반도체 칩과 기판을 전기적으로 연결시키는 금속와이어의 본딩 공정을 생략하여 제조공정을 단순화하여 제품의 신뢰성이 우수한 칩크기 패키지의 제조방법을 제공함에 그 목적이 있다.In addition, another object of the present invention is to provide a method for producing a chip-size package excellent in the reliability of the product by simplifying the manufacturing process by eliminating the bonding process of the metal wire electrically connecting the semiconductor chip and the substrate.

도 1은 종래의 제 1실시예에 따른 칩크기 패키지의 단면도.1 is a cross-sectional view of a chip size package according to a first embodiment of the prior art.

도 2는 종래의 제 2실시예에 따른 칩크기 패키지의 단면도.Figure 2 is a cross-sectional view of a chip size package according to a second embodiment of the prior art.

도 3은 본 발명에 따른 칩크기 패키지의 단면도.3 is a cross-sectional view of a chip size package according to the present invention.

도 4a 내지 도 4d는 본 발명에 따른 칩크기 패키지의 제조공정도.4a to 4d is a manufacturing process of the chip size package according to the present invention.

도 5는 본 발명에 따른 기판의 상부 평면도.5 is a top plan view of a substrate according to the present invention.

도 6은 본 발명에 따른 기판의 하부 평면도.6 is a bottom plan view of a substrate according to the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

100. 반도체 칩 102. 칩패드100. Semiconductor chip 102. Chip pad

104. 접착제 120. 기판104. Adhesive 120. Substrate

106. 관통홀 112. 범프볼106.Through Hole 112.Bump Ball

122. 배선 124. 볼랜드122. Wiring 124. Borland

132. 도전층 134. 도전성 볼132. Conductive Layers 134. Conductive Balls

136. 보호막136. Shield

상기 목적을 달성하기 위한 본 발명의 칩크기 패키지 구조는 다수의 칩패드가 형성된 반도체 칩과, 칩패드에 부착된 각각의 범프볼(bump ball)과, 반도체 칩상에 범프볼을 노출시키도록 코팅된 접착층과, 접착층 상에 부착되며, 범프볼과 대응된 위치에 다수의 관통홀이 형성된 기판과, 기판을 덮되, 볼랜드 및 관통홀을 애워싸는 메탈링을 갖는 배선과, 배선을 덮되, 관통홀 및 볼랜드를 노출시킨 보호막과, 관통홀을 덮으며, 범프볼과 배선을 연결시킨 도전층과, 볼랜드 상에 부착된 다수의 도전성 볼을 포함한 것을 특징으로 한다.The chip size package structure of the present invention for achieving the above object is coated with a semiconductor chip formed with a plurality of chip pads, each bump ball attached to the chip pad, and to expose the bump ball on the semiconductor chip An adhesive layer, a substrate attached on the adhesive layer, the substrate having a plurality of through holes formed at a position corresponding to the bump ball, a wiring covering the substrate, and having a metal ring surrounding the borland and the through hole; And a protective layer exposing the ball land, a conductive layer covering the through hole, connecting the bump ball and the wiring, and a plurality of conductive balls attached to the ball land.

또한, 상기 다른 목적을 달성하기 위한 본 발명의 칩크기 패키지의 제조방법은 웨이퍼에 형성된 다수의 칩패드에 각각의 범프볼을 부착하는 공정과, 웨이퍼 상에 범프볼을 노출시키도록 접착층을 코팅하는 공정과, 다수의 칩패드와 대응되도록 기판에 다수의 관통홀을 형성하는 공정과, 기판을 덮되, 볼랜드 및 관통홀을 애워싸는 메탈링을 갖는 배선을 형성하는 공정과, 배선을 덮되, 관통홀 및 볼랜드를 노출시키는 보호막을 형성하는 공정과, 접착층에 보호막이 형성된 기판을 부착시키는 공정과, 관통홀을 덮어 범프볼과 배선을 연결시키도록 도전층을 형성하는 공정과, 볼랜드 상에 다수의 도전성 볼을 부착시키는 공정과, 결과물을 칩단위로 쏘잉하는 공정을 구비한 것을 특징으로 한다.In addition, the manufacturing method of the chip size package of the present invention for achieving the above another object is a process of attaching each bump ball to a plurality of chip pads formed on the wafer, and coating the adhesive layer to expose the bump ball on the wafer Forming a plurality of through holes in the substrate so as to correspond to the plurality of chip pads; forming a wiring covering the substrate, the wiring having a metal ring surrounding the borland and the through holes; And a step of forming a protective film exposing the ball lands, a step of attaching a substrate on which the protective film is formed on the adhesive layer, a step of forming a conductive layer covering the through holes and connecting the bump balls and the wiring, and a plurality of conductive films on the ball lands. And a step of attaching the ball and sawing the resultant in chips.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명에 따른 칩크기 패키지로, 웨이퍼 상태에서 반도체 칩 단위로 쏘잉(sawing)된 것을 보인 단면도이다. 그리고 도 5는 본 발명에 따른 기판의 상부 평면도이고, 도 6은 본 발명에 따른 기판의 하부 평면도로, 기판 하부의 평면을 가상적으로 도시한 것이다.3 is a cross-sectional view showing a chip size package according to the present invention, which is sawed by a semiconductor chip unit in a wafer state. FIG. 5 is a top plan view of the substrate according to the present invention, and FIG. 6 is a bottom plan view of the substrate according to the present invention and shows a plane of the bottom of the substrate.

본 발명에 따른 칩크기 패키지 구조는, 도 3, 도 5 및 도 6에 도시된 바와 같이, 다수의 칩패드(102)가 형성된 반도체 칩(100)과, 칩패드(102)에 부착된 각각의 범프볼(106)과, 반도체 칩(100) 상에 범프볼(106)을 노출시키도록 코팅된 접착층(104)과, 접착층(104) 상에 부착되며, 범프볼(106)과 대응된 위치에 다수의 관통홀(108)이 형성된 기판(120)과, 기판(120)을 덮되, 볼랜드(124) 및 관통홀(108)을 애워싸는 메탈링(metal ring)(132)을 갖는 배선(122)과, 배선(122)을 덮되, 관통홀(108) 및 볼랜드(124)를 노출시킨 보호막(136)과, 관통홀(108)을 덮으며, 범프볼(106)과 배선(122)을 연결시킨 도전층(112)과, 볼랜드(124) 상에 부착된 다수의 도전성(134) 볼로 구성된다.As shown in FIGS. 3, 5, and 6, the chip size package structure according to the present invention includes a semiconductor chip 100 having a plurality of chip pads 102 formed thereon, and each chip attached to the chip pads 102. The bump ball 106, the adhesive layer 104 coated to expose the bump ball 106 on the semiconductor chip 100, and are attached on the adhesive layer 104, at a position corresponding to the bump ball 106. Wiring 122 having a substrate 120 having a plurality of through holes 108 formed therein, and a metal ring 132 covering the substrate 120 and surrounding the borland 124 and the through holes 108. And a protective film 136 covering the wiring 122, exposing the through hole 108 and the borland 124, and covering the through hole 108, and connecting the bump ball 106 and the wiring 122. It consists of a conductive layer 112 and a plurality of conductive 134 balls attached on the ball land 124.

도 4a 내지 도 4d는 본 발명에 따른 칩크기 패키지의 제조방법을 보이기 위한 일부 공정단면도이다.Figures 4a to 4d is a partial cross-sectional view for showing a method of manufacturing a chip size package according to the present invention.

상기 구성된 본 발명에 따른 칩크기 패키지의 제조방법은, 도 4a에 도시된 바와 같이, 웨이퍼(101)의 칩패드(102) 상에 각각의 범프볼(106)을 부착시킨다. 상기 칩패드(102)는 웨이퍼(101)의 칩영역 상에 다수 형성되어져 있다.In the method of manufacturing the chip size package according to the present invention configured as described above, as shown in FIG. 4A, each bump ball 106 is attached onto the chip pad 102 of the wafer 101. A plurality of chip pads 102 are formed on the chip region of the wafer 101.

이어서, 웨이퍼(101) 상에 접착제를 도포한 다음, 오븐(oven)에서 변경화시킨 다음, 범프볼(106)을 노출시키도록 패턴 식각하여 접착층(104)를 형성한다.Subsequently, an adhesive is applied on the wafer 101, and then modified in an oven, and then pattern-etched to expose the bump balls 106 to form an adhesive layer 104.

이때, 접착층(104)은 실크 스크린(silk screen) 방식으로 도포하며, 재질로는 통상적인 접착제가 사용된다. 접착층(104)의 다른 예로, 범프볼(106) 형성부위가 개구된 접착테이프를 이용할 수 있으며, 웨이퍼(101)에 상기 접착테이프를 열압착 방식으로 부착한다. 상기 접착테이프의 재질로는 에폭시(epoxy) 계열의 수지 또는 폴리이미드(polyimide) 계열의 수지가 이용된다.In this case, the adhesive layer 104 is applied by a silk screen method, and a conventional adhesive is used as a material. As another example of the adhesive layer 104, an adhesive tape having a portion where the bump ball 106 is formed may be used, and the adhesive tape is attached to the wafer 101 by thermocompression bonding. As the material of the adhesive tape, an epoxy resin or a polyimide resin is used.

다음, 도 4b에 도시된 바와 같이, 기판(120)의 소정부위를 식각하여 다수의 관통홀(108)을 형성한다. 이 때, 관통홀(108)은 도 4a에 도시된 범프볼(106)과 대응된 부분에 형성된다. 상기 기판(120)은 폴리이미드 계열의 플라스틱(plastic), 세라믹(ceramic) 또는 글라스(glass)를 이용한다.Next, as shown in FIG. 4B, a predetermined portion of the substrate 120 is etched to form a plurality of through holes 108. At this time, the through hole 108 is formed in a portion corresponding to the bump ball 106 shown in Figure 4a. The substrate 120 is made of polyimide plastic, ceramic, or glass.

이어서, 기판(120) 상에 금속막을 스퍼터링(sputtering)에 의해 증착한 다음, 다수의 관통홀(108)을 노출시키도록 식각하여 배선(122)을 형성한다.Subsequently, a metal film is deposited on the substrate 120 by sputtering and then etched to expose a plurality of through holes 108 to form a wiring 122.

이때, 배선(122)은, 도 5에 도시된 바와 같이, 관통홀(108) 주변 부위에 관통홀(108)을 애워싸는 링(ring)형상의 메탈링(132)이 형성되고, 연장된 일부위에 볼랜드(124)가 형성되고, 메탈링과 볼랜드를 연결하는 메탈 트레이스(metal trace)가 형성된다.In this case, as shown in FIG. 5, as shown in FIG. 5, a ring-shaped metal ring 132 surrounding the through hole 108 is formed at a portion around the through hole 108, and an extended portion thereof. A ball land 124 is formed thereon, and a metal trace connecting the metal ring and the ball land is formed.

또한, 배선(122)의 볼랜드(124) 및 메탈링(132) 표면에 접착성을 높이기 위해, 다층으로 적층된 금속층을 코팅하며, 금속층으로는 Sn/Pb, Pd/Ni/Au, Cu/Ni/Au, Cu/Ni/Cr/Au, Cu, Ni/Co/Au, Cu/Ni/Co/Au, Cu/Ni/Au/TiN, Cu/Ni/Cr/Au/TiN 또는 Cu/Ni/Co/Au/Tin 등을 예로 들 수 있다.In addition, in order to increase the adhesion on the surface of the ball land 124 and the metal ring 132 of the wiring 122, a metal layer laminated in multiple layers is coated, and the metal layer is Sn / Pb, Pd / Ni / Au, Cu / Ni Cu / Ni / Cr / Au, Cu, Ni / Co / Au, Cu / Ni / Co / Au, Cu / Ni / Au / TiN, Cu / Ni / Cr / Au / TiN or Cu / Ni / Co / Au / Tin etc. are mentioned, for example.

그리고 메탈링(132) 및 볼랜드(124) 표면에, 도면에 도시되지 않았지만, 원, 삼각형 또는 사각형 형상의 단차부를 형성하여서 도전층(112) 및 이후 공정을 거쳐서 볼랜드(124)에 안착되도록 형성되는 도전성 볼 과의 접촉면적을 크게 하여 안정적으로 고정시킨다.Although not shown in the drawing, the metal ring 132 and the borland 124 are formed to form a stepped portion in a circle, triangle, or quadrangular shape so as to be seated on the conductive layer 112 and the borland 124 through a subsequent process. The contact area with the conductive balls is enlarged and fixed stably.

이때, 볼랜드(124)의 단차부는 직경이 300㎛ 이상, 메탈링(132)의 단차부는직경이 100㎛ ∼ 300㎛ 가 되도록 한다.At this time, the stepped portion of the borland 124 is 300㎛ or more in diameter, the stepped portion of the metal ring 132 so that the diameter is 100㎛ ~ 300㎛.

이 후, 배선(122) 상에 실리콘산화막을 증착한 다음, 볼랜드(124)를 노출시키도록 식각하여 보호막(136)을 형성한다.Thereafter, a silicon oxide film is deposited on the wiring 122 and then etched to expose the borland 124 to form a protective film 136.

이어서, 도 4c에 도시된 바와 같이, 접착층(104) 상에 상기 보호막(136) 형성 공정이 진행된 기판(120)을 부착시킨다. 이때, 기판(120)에 형성된 다수의 관통홀(108)과 범프볼(106)은 서로 대응된 위치에 있도록 배치된다.Subsequently, as shown in FIG. 4C, the substrate 120 having the protective film 136 forming process is adhered to the adhesive layer 104. In this case, the plurality of through holes 108 and the bump balls 106 formed in the substrate 120 are disposed to correspond to each other.

그 다음, 도 4d에 도시된 바와 같이, 보호막(136) 상에 관통홀(108)을 덮도록 솔더페이스트(solder paste)(미도시)를 도포한 다음, 상기 솔더페이스트를 보호막이 노출되는 시점까지 시각하여 도전층(112)을 형성한다. 이때, 도전층(112)은 범프볼(106)과 배선(122)의 메탈링(132)을 연결시키는 역할을 한다.Next, as shown in FIG. 4D, a solder paste (not shown) is applied on the passivation layer 136 to cover the through hole 108, and then the solder paste is applied until the passivation layer is exposed. The conductive layer 112 is formed by visually. At this time, the conductive layer 112 serves to connect the bump ball 106 and the metal ring 132 of the wiring 122.

이 후, 볼랜드(124)에 도전성 볼(134)을 안착시킨다. 다음, 개별적인 칩단위로 절단하여 도 3에 도시된 바와 같은 칩크기의 패키지 제조를 완료한다.Thereafter, the conductive balls 134 are seated on the ball lands 124. Next, cutting into individual chip units is completed to manufacture the package of the chip size as shown in FIG.

이상에서와 같이, 본 발명에서는 반도체 칩과 기판을 전기적으로 연결시키는 금속와이어의 본딩 공정을 생략할 수 있고, 별도의 몰딩 공정이 필요없어 제조공정을 단순화할 수 있다.As described above, in the present invention, the bonding process of the metal wire for electrically connecting the semiconductor chip and the substrate may be omitted, and the manufacturing process may be simplified since a separate molding process is not required.

또한, 본 발명에서는 금속와이어 대신 범프볼 및 도전성 볼을 이용함으로써, 금속와이어 사용에 의한 커패시턴스, 인덕턴스 및 레지스턴스의 증가를 방지할 수 있다.In addition, in the present invention, by using bump balls and conductive balls instead of metal wires, an increase in capacitance, inductance and resistance due to the use of metal wires can be prevented.

그리고 본 발명에서는 메탈링 및 볼랜드 표면에 단차부를 형성함에 따라, 메탈링과 범프볼 및 볼랜드와 도전성 볼 간의 접촉면적이 커지며, 또한, 메탈링 및 볼랜드 표면에 다층의 금속층을 코팅함에 따라, 메탈링과 도전층 및 볼랜드와 도전성 볼 간의 접착력이 우수해진다.In the present invention, as the stepped portion is formed on the surface of the metal ring and the borland, the contact area between the metal ring, the bump ball, and the borland and the conductive ball is increased, and the metal ring is coated by coating the multilayer metal layer on the surface of the metal ring and the borland. And the adhesion between the conductive layer and the ball land and the conductive ball are excellent.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (19)

다수의 칩패드가 형성된 반도체 칩과A semiconductor chip having a plurality of chip pads formed thereon 상기 칩패드에 부착된 각각의 범프볼과,Each bump ball attached to the chip pad, 상기 반도체 칩 상에 상기 범프볼을 노출시키도록 코팅된 접착층과,An adhesive layer coated to expose the bump balls on the semiconductor chip; 상기 접착층 상에 부착되며, 상기 범프볼과 대응된 위치에 관통홀이 형성된 기판과,A substrate attached to the adhesive layer and having a through hole formed at a position corresponding to the bump ball; 상기 기판을 덮되, 볼랜드 및 상기 관통홀을 애워싸는 메탈링을 갖는 배선과,A wiring covering the substrate, the wiring having a metal ring surrounding the borland and the through hole; 상기 배선을 덮되, 상기 관통홀 및 상기 볼랜드를 노출시킨 보호막과,A protective film covering the wiring and exposing the through hole and the ball land; 상기 관통홀을 덮으며, 상기 범프볼과 상기 배선을 연결시킨 도전층과,A conductive layer covering the through hole and connecting the bump ball and the wiring; 상기 볼랜드 상에 부착된 도전성 볼을 포함하여 구성되는 것을 특징으로 하는 칩크기 패키지 구조.Chip size package structure comprising a conductive ball attached to the ball land. 제 1항에 있어서, 상기 도전층은 솔더 페이스트인 것을 특징으로 하는 칩크기 패키지 구조.The chip size package structure of claim 1, wherein the conductive layer is solder paste. 제 1항에 있어서, 상기 접착층은 접착제 또는 접착테이프인 것은 특징으로하는 칩크기 패키지 구조.The chip size package structure of claim 1, wherein the adhesive layer is an adhesive or an adhesive tape. 제 3항에 있어서, 상기 접착제는 에폭시 계열의 수지 또는 폴리이미드 계열의 수지인 것을 특징으로 하는 칩크기 패키지 구조.4. The chip size package structure of claim 3, wherein the adhesive is an epoxy resin or a polyimide resin. 제 1항에 있어서, 상기 기판은 폴리이미드 계열의 플라스틱, 세라믹 또는 글라스인 것을 특징으로 하는 칩크기 패키지 구조.The chip size package structure of claim 1, wherein the substrate is polyimide-based plastic, ceramic, or glass. 제 1항에 있어서, 상기 볼랜드 및 상기 메탈링의 표면에는 단차부가 형성된 것을 특징으로 하는 칩크기 패키지 구조.The chip size package structure of claim 1, wherein a stepped portion is formed on surfaces of the borland and the metal ring. 제 6항에 있어서, 상기 볼랜드의 단차부는 직경이 300㎛ 이상인 것을 특징으로 하는 칩크기 패키지 구조.The chip size package structure according to claim 6, wherein the stepped portion of the borland has a diameter of 300 µm or more. 제 6항에 있어서, 상기 메탈링의 단차부는 직경이 100㎛ ∼ 300㎛ 인 것을특징으로 하는 칩크기 패키지 구조.7. The chip size package structure according to claim 6, wherein the stepped portion of the metal ring has a diameter of 100 µm to 300 µm. 제 6항에 있어서, 상기 단차부는 원, 삼각형 또는 사각형 형상을 갖는 것을 특징으로 하는 칩크기 패키지 구조.The chip size package structure of claim 6, wherein the stepped portion has a circular, triangular or square shape. 제 1항에 있어서, 상기 메탈링 및 볼랜드 표면에는 Sn/Pb, Pd/Ni/Au, Cu/Ni/Au, Cu/Ni/Cr/Au, Cu, Ni/Co/Au, Cu/Ni/Co/Au, Cu/Ni/Au/TiN, Cu/Ni/Cr/Au/TiN 또는 Cu/Ni/Co/Au/Tin 중에서 어느 하나가 코팅된 것을 특징으로 하는 칩크기 패키지 구조.According to claim 1, wherein the metal ring and borland surface Sn / Pb, Pd / Ni / Au, Cu / Ni / Au, Cu / Ni / Cr / Au, Cu, Ni / Co / Au, Cu / Ni / Co Chip size package structure characterized in that any one of / Au, Cu / Ni / Au / TiN, Cu / Ni / Cr / Au / TiN or Cu / Ni / Co / Au / Tin is coated. 웨이퍼에 형성된 다수의 칩패드에 각각의 범프볼을 부착하는 공정과,Attaching each bump ball to a plurality of chip pads formed on a wafer, 상기 웨이퍼 상에 상기 범프볼을 노출시키도록 접착층을 코팅하는 공정과,Coating an adhesive layer to expose the bump balls on the wafer; 상기 다수의 칩패드와 대응되도록 기판에 관통홀을 형성하는 공정과,Forming a through hole in the substrate to correspond to the plurality of chip pads; 상기 기판을 덮되, 볼랜드 및 상기 관통홀을 애워싸는 메탈링을 갖는 배선을 형성하는 공정과,Forming a wiring covering the substrate, the wiring having a metal ring surrounding the borland and the through hole; 상기 배선을 덮되, 상기 관통홀 및 상기 볼랜드를 노출시키는 보호막을 형성하는 공정과,Forming a protective film covering the wiring and exposing the through hole and the ball land; 상기 접착층에 상기 보호막이 형성된 기판을 부착시키는 공정과,Attaching a substrate having the protective film to the adhesive layer; 상기 관통홀을 덮어 상기 범프볼과 상기 배선을 연결시키도록 도전층을 형성하는 공정과,Forming a conductive layer covering the through hole to connect the bump ball and the wiring; 상기 볼랜드 상에 도전성 볼을 부착시키는 공정과,Attaching a conductive ball onto the ball land; 상기 결과물을 칩단위로 쏘잉하는 공정을 포함하여 이루어진 것을 특징으로 칩크기 패키지의 제조방법.And a step of sawing the resultant chip. 제 11항에 있어서, 상기 접착층은 상기 웨이퍼 상에 접착테이프를 열압착방식으로 부착하는 것을 특징으로 하는 칩크기 패키지의 제조방법.12. The method of claim 11, wherein the adhesive layer attaches an adhesive tape on the wafer by thermocompression bonding. 제 12항에 있어서, 상기 접착층은 상기 웨이퍼 상에 접착제를 실크 스크린 방식으로 부착하는 것을 특징으로 하는 칩크기 패키지의 제조방법.The method of claim 12, wherein the adhesive layer attaches an adhesive on the wafer in a silk screen manner. 제 11항에 있어서, 상기 접착제는 오븐에서 반경화하는 것을 특징으로 하는 하는 칩크기 패키지의 제조방법.12. The method of claim 11 wherein the adhesive is semi-cured in an oven. 제 11항에 있어서, 상기 볼랜드 및 상기 메탈링 표면에 단차부를 형성하는 공정을 추가하는 것을 특징으로 하는 칩크기 패키지의 제조방법.12. The method of claim 11, further comprising the step of forming a stepped portion on the borland and the metallization surface. 제 15항에 있어서, 상기 볼랜드의 단차부는 직경이 300㎛ 이상인 것을 특징으로 하는 칩크기 패키지의 제조방법.The method of claim 15, wherein the stepped portion of the borland has a diameter of 300 μm or more. 제 15항에 있어서, 상기 메탈링의 단차부는 직경이 100㎛ ∼ 300㎛ 인 것을 특징으로 하는 칩크기 패키지의 제조방법.The method of claim 15, wherein the stepped portion of the metal ring has a diameter of 100 μm to 300 μm. 제 15항에 있어서, 상기 단차부의 형상은 원, 삼각형 또는 사각형인 것을 특징으로 하는 칩크기 패키지의 제조방법.The method of claim 15, wherein the stepped portion has a circle, triangle, or quadrangular shape. 제 11항에 있어서, 상기 메탈링 및 볼랜드 표면에 Sn/Pb, Pd/Ni/Au, Cu/Ni/Au, Cu/Ni/Cr/Au, Cu, Ni/Co/Au, Cu/Ni/Co/Au, Cu/Ni/Au/TiN, Cu/Ni/Cr/Au/TiN 또는 Cu/Ni/Co/Au/Tin 에서 어느 하나를 선택하여 코팅하는 공정을 더 추가한 것을 특징으로 하는 칩크기 패키지의 제조방법.12. The method of claim 11, wherein the metal ring and the surface of the borland Sn / Pb, Pd / Ni / Au, Cu / Ni / Au, Cu / Ni / Cr / Au, Cu, Ni / Co / Au, Cu / Ni / Co Chip size package, characterized in that it further adds a coating process by selecting any one of / Au, Cu / Ni / Au / TiN, Cu / Ni / Cr / Au / TiN or Cu / Ni / Co / Au / Tin Manufacturing method.
KR10-2001-0022949A 2001-04-27 2001-04-27 chip scale package and method of fabricating the same KR100417854B1 (en)

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