KR20020070584A - Method of forming under bump metallurgy and structure thereof - Google Patents
Method of forming under bump metallurgy and structure thereof Download PDFInfo
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- KR20020070584A KR20020070584A KR1020010010733A KR20010010733A KR20020070584A KR 20020070584 A KR20020070584 A KR 20020070584A KR 1020010010733 A KR1020010010733 A KR 1020010010733A KR 20010010733 A KR20010010733 A KR 20010010733A KR 20020070584 A KR20020070584 A KR 20020070584A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05144—Gold [Au] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05164—Palladium [Pd] as principal constituent
Abstract
Description
본 발명은 웨이퍼 범핑 공정에 관한 것으로, 특히 솔더 범프의 형성전에 무전해 Ni/Au도금층의 언더 범프 메탈층을 형성시키기 위한 언더 범프 메탈의 제조방법 및 그 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer bumping process, and more particularly, to a method of manufacturing an under bump metal and a structure thereof for forming an under bump metal layer of an electroless Ni / Au plating layer prior to the formation of solder bumps.
반도체 칩의 구조에 있어서 현재 일반적으로 많이 사용되고 있는 칩과 리드 프레임과의 인터커넥션(interconnection) 방법으로는 와이어본딩방식이 있다. 이에 대해 최근에는 웨이퍼 상에 범핑을 하여 리드 프레임의 역할을 하는 솔더 범프(Solder Bump)를 형성하고 이를 직접 팩키지나 기판에 인터커넥션시키는 플립칩 본딩 방식이 많이 사용되고 있다. 이와 같은 플립칩 본딩 방식은 전기적 성질이 우수할 뿐 아니라, 제품의 크기를 줄일 수 있을 있고, 와이어의 단락의 염려도 없어 포터블 제품, 슈퍼 컴퓨터 등 다양한 분야에서 이용되고 있다.A wire bonding method is used as an interconnection method between a chip and a lead frame which are generally used in the structure of a semiconductor chip. Recently, a flip chip bonding method of bumping a wafer to form a solder bump serving as a lead frame and interconnecting the package or a substrate directly has been widely used. Such a flip chip bonding method is excellent in electrical properties, can reduce the size of the product, there is no fear of short circuit of the wire has been used in various fields such as portable products, super computers.
이와 같은 플립칩 본딩 방식은 웨이퍼 범핑 공정으로 이루어 지는 데, 웨이퍼 범핑 공정은 크게 언더 범프 메탈(Under Bump Metallurgy: 이하 UBM이라 한다.)제조공정과 솔더 범핑 공정으로 구분된다.The flip chip bonding method is a wafer bumping process, which is classified into an under bump metallurgy (UBM) manufacturing process and a solder bumping process.
현재 웨이퍼 범핑 공정 중에서 UBM 제조에 사용되는 기술은 크게 두 가지로 구분할 수 있다. 하나는 건식도금 방식인 스퍼터링을 이용한 방식이고, 다른 하나는 습식도금 방식인 무전해 도금을 이용한 기술이다. 스퍼터링을 이용하여 Al/NiV/Cu 층을 형성하는 방식은 고가이지만, 신뢰성이 우수하여 비교적 높은 핀수를 갖는 제품에 주로 적용되는 것이고, 무전해 도금을 이용하여 Al/Ni/Au 층을 형성하는 기술은 비용면에서는 저가라는 장점을 가지고 있으며, 고신뢰도를 요구하는 제품보다는 신뢰도가 떨어져 중, 저 핀수의 제품에 주로 사용되고 있다. 이후 제조공정인 솔더 범핑은 상기 공정에서 제조된 UBM상에 솔더 페이스트를 이용하여 스크린 프린팅 방식으로 일정한 크기로 도포한후 리플로우(Reflow) 공정을 거쳐 솔더볼을 형성하게 되는 데, 이렇게 형성된 솔더볼을 일명 솔더 범프라 명명한다. 본 발명에서의 UBM 제조공정은 상술한 방법 중 무전해 도금을 이용한 방법에 관한 것이다.Among the wafer bumping processes, UBM manufacturing technology can be classified into two categories. One is a method using sputtering, which is a dry plating method, and the other is a technique using electroless plating, which is a wet plating method. Although the method of forming Al / NiV / Cu layer by sputtering is expensive, it is mainly applied to products having a relatively high pin number due to its excellent reliability, and a technique of forming Al / Ni / Au layer using electroless plating. Silver has the advantage of low cost in terms of cost, and is less used than products requiring high reliability, and is mainly used for medium and low pin-count products. Since the solder bumping process is applied to the UBM manufactured in the process by using a solder paste to a certain size by screen printing method to form a solder ball through a reflow process, so-called solder ball formed Name the solder bumpers. UBM manufacturing process in the present invention relates to a method using the electroless plating of the above-described method.
무전해 도금을 이용한 UBM제조공정은 솔더 범프를 형성하기 전에 본딩패드상에 무전해 Ni/Au 도금층을 형성시키는 공정을 말한다.The UBM manufacturing process using electroless plating refers to a process of forming an electroless Ni / Au plating layer on a bonding pad before forming solder bumps.
일반적으로 알루미늄 또는 알루미늄 합금 소재의 본딩패드는 산화막 형성 속도가 매우 빠른 특성을 갖고 있어 도금 반응성 및 밀착성이 좋지 않은 것으로 알려져 있다. 따라서 이러한 알루미늄계 소재의 본딩패드 상에 무전해 니켈 도금을 할 때에는 통상적으로 징케이트(Zincate)라는 전처리 공정을 거치게 된다. 징케이트 공정은 알루미늄계 소재와 무전해 Ni/Au 도금층과의 밀착성을 부여하기 위한 것으로서, 알루미늄 소재와 징케이트 용액내의 아연과의 전위차를 이용하여 알루미늄 패드 표면에 아연핵을 치환시키는 공정이다. 이렇게 징케이트 공정을 통해 형성된 아연핵으로부터 무전해 니켈 도금 반응이 시작되고, 니켈 도금층을 일정 두께로 전착 후, 침적 금도금(Immersion Au)을 실시하여 Ni/Au 도금층을 형성하는 것이다. 그러나 징케이트 공정으로부터 형성된 무전해 Ni/Au 도금층은 전기화학적으로 내부식성에 약한 구조를 갖고 있다. 이는 패드 소재로 사용된 알루미늄과 그 위에 형성된 아연핵이 전기화학적으로 비(卑)한 금속이어서, 무전해 도금으로 형성된 Ni/Au층과 전기화학 포텐셜의 차이를 일으키게 되고, 이에 따라 부식 환경하에서 급격한 소재 부식을 발생시키기 때문이다.In general, a bonding pad made of aluminum or an aluminum alloy has a very fast oxide film formation rate and is known to have poor plating reactivity and adhesion. Therefore, when electroless nickel plating is performed on the bonding pad of the aluminum material, a pretreatment process called zincate is generally performed. The zinc gating step is to impart adhesion between the aluminum-based material and the electroless Ni / Au plating layer, and is a step of replacing the zinc nuclei on the surface of the aluminum pad by using a potential difference between the aluminum material and zinc in the zinc casting solution. The electroless nickel plating reaction is started from the zinc nucleus formed through the zinc casting process, and the nickel plating layer is electrodeposited to a predetermined thickness, followed by immersion gold plating (Immersion Au) to form a Ni / Au plating layer. However, the electroless Ni / Au plating layer formed from the gating process has an electrochemically weak structure against corrosion. This is because the aluminum used as the pad material and the zinc nucleus formed thereon are electrochemically incompatible metals, which causes a difference between the Ni / Au layer formed by the electroless plating and the electrochemical potential, and thus is abrupt in a corrosive environment. This is because it causes material corrosion.
본 발명은 상기와 같은 종래 징케이트 전처리에 의한 Ni/Au UBM 제조방법의 문제를 해결하기 위한 것으로, 전기화학적으로 비(卑)한 아연을 대신하여 전기화학적으로 귀(貴)한 팔라듐(Pd)을 사용하여 내식성을 개선시키고, 전체적인 패키지 신뢰도를 향상시킨 무전해 니켈/금 도금층의 제조 방법을 제공하는 데 그 목적이 있다.The present invention is to solve the problem of the Ni / Au UBM manufacturing method by the conventional jingkaate pretreatment as described above, palladium (Pd) which is electrochemically noble in place of the electrochemically zinc (Pd) The purpose of the present invention is to provide a method for producing an electroless nickel / gold plated layer, which improves corrosion resistance and improves overall package reliability.
도 1은 본 발명에 따라 언더 범프 메탈이 형성된 웨이퍼의 단면도.1 is a cross-sectional view of a wafer formed with an under bump metal according to the present invention.
※도면의 주요부분에 대한 부호의 설명※※ Explanation of symbols about main part of drawing ※
10: 웨이퍼12: 본딩 패드10: wafer 12: bonding pad
14: 패시베이션막16: 팔라듐 핵14 passivation film 16: palladium nucleus
18: Ni 도금층20: Au 도금층18: Ni plating layer 20: Au plating layer
상기와 같은 목적을 달성하기 위하여, 본 발명은 기판상에 금속 소재 혹은 알루미늄계 소재의 패드가 형성되어 있고, 상기 패드의 외곽 일부와 상기 기판의 잔부에 패시베이션막이 형성되어 있는 웨이퍼에 언더 범프 메탈을 제조하는 방법에 있어서, 클리닝 처리한 웨이퍼의 노출된 패드 상에 팔라듐 금속핵을 형성시키고, 그 위에 무전해 니켈 도금층 및 금 도금층을 형성시키는 것을 특징으로 하는 언더 범프 메탈의 제조방법 및 그 구조를 제공한다.In order to achieve the above object, in the present invention, a pad of a metal material or an aluminum material is formed on a substrate, and an under bump metal is formed on a wafer having a passivation film formed on an outer portion of the pad and the remainder of the substrate. A method of manufacturing an under bump metal, comprising: forming a palladium metal nucleus on an exposed pad of a cleaned wafer, and forming an electroless nickel plating layer and a gold plating layer thereon; do.
이하 첨부된 도면을 참고로 본 발명에 대해 보다 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따라 언더 범프 메탈이 형성된 웨이퍼의 단면을 도시한 그림이다. 그림에서 볼 수 있듯이 웨이퍼(10) 상에는 본딩 패드인 알루미늄 또는 알루미늄 합금(Al-Si, Al-Si-Cu)의 패드(12)가 노출되어 있고, 그 본딩패드(12)의 외곽 일부와 나머지 웨이퍼 부위에는 보호막인 패시베이션막(14)이 형성되어 있다. 패시베이션막(14)은 SiO2, Si3N4, Polyimide, BCB(Benzo-Cyclo-Butene)등으로 형성할 수 있다.1 is a cross-sectional view of a wafer on which an under bump metal is formed according to the present invention. As shown in the figure, a pad 12 of aluminum or aluminum alloy (Al-Si, Al-Si-Cu), which is a bonding pad, is exposed on the wafer 10, and the outer portion of the bonding pad 12 and the remaining wafers are exposed. The passivation film 14 which is a protective film is formed in the site | part. The passivation film 14 may be formed of SiO 2 , Si 3 N 4 , Polyimide, BCB (Benzo-Cyclo-Butene), or the like.
이렇게 형성된 웨이퍼(10)의 본딩패드(12) 중 보호막이 형성되지 않고 개방된 부위로 팔라듐(Pd) 막(16)이 형성된다. 이 팔라듐 막(16)은 UBM층인 니켈/금의 도금층과 알루미늄계 패드와의 도금 반응성 및 밀착성을 증대시키기 위한 것으로, UBM층의 내부식성을 증가시키는 역할을 한다. 팔라듐은 기존의 징케이트법에서 사용하는 아연에 비해 전기화학적으로 귀(貴)한 금속으로 알루미늄계 패드층(12)과UBM층 사이에 팔라듐 층을 형성시키므로서 습기나 외부의 부식환경하에서 산화반응속도를 줄여 전체적인 부식속도를 감소시키는 역할을 하게 된다. 또한 팔라듐은 종래에 사용되던 아연에 비해 밀착성 및 균일성이 우수한 특성을 가지고 있다.The palladium (Pd) film 16 is formed as an open portion of the bonding pad 12 of the wafer 10 thus formed without forming a protective film. The palladium film 16 is to increase the plating reactivity and adhesion between the nickel / gold plating layer, which is the UBM layer, and the aluminum pad, and increases the corrosion resistance of the UBM layer. Palladium is an electrochemically precious metal compared to zinc used in the conventional jinating method. Palladium forms an palladium layer between the aluminum pad layer 12 and the UMB layer to oxidize under moisture or external corrosive environments. By reducing the speed it plays a role in reducing the overall corrosion rate. In addition, palladium has excellent adhesiveness and uniformity compared to conventional zinc.
본 발명의 바람직한 일실시예에 의한 팔라듐층은 무전해 니켈 도금층의 용이한 형성을 위한 핵으로 작용하며, 그 두께는 10~1000Å, 바람직하게는 수백Å으로 형성하도록 하였다.The palladium layer according to a preferred embodiment of the present invention serves as a nucleus for easy formation of the electroless nickel plating layer, and the thickness thereof is 10 to 1000 kPa, preferably several hundred kcal.
이렇게 형성된 팔라듐 핵을 매개로 그 위에 UBM층을 형성한다. 본 발명에 있어서 UBM층은 무전해 Ni/Au 도금층으로 하였다. 본 발명의 바람직한 일실시예에서는 UBM층의 두께에 대해서 무전해 니켈 도금층을 1~50㎛로 형성하고, 그 위에 침적 금도금층을 10~1000Å로 형성하도록 하였다.The UBM layer is formed thereon through the palladium nucleus thus formed. In the present invention, the UBM layer was an electroless Ni / Au plating layer. In a preferred embodiment of the present invention, the electroless nickel plating layer was formed at 1 to 50 µm with respect to the thickness of the UBM layer, and the deposition gold plating layer was formed at 10 to 1000 mPa thereon.
이렇게 Ni/Au 도금층 상에 솔더 범프를 형성하게 된다.Thus, solder bumps are formed on the Ni / Au plating layer.
본 발명의 UBM제조방법에 대해 설명하면 다음과 같다.Referring to the manufacturing method of the UBM of the present invention.
알루미늄 또는 알루미늄 합금으로 이루어진 패드를 구비한 웨이퍼에 패시베이션막 공정이 종료되면, 이 웨이퍼를 통상의 전처리 방법으로 세정한다. 본 발명의 바람직한 일실시예에 있어, 이 웨이퍼 전처리 공정은 플라즈마 클리닝 단계를 거쳐, 탈지 및 수세 단계를 거치고, 50wt%의 HNO3용액에 수초간 침적 처리한다. 이렇게 산처리 공정을 거쳐 다시 수세처리한 후 팔라듐 처리공정을 실시하게 된다.When the passivation film process is completed on the wafer with pads made of aluminum or aluminum alloy, the wafer is cleaned by a conventional pretreatment method. In a preferred embodiment of the present invention, the wafer pretreatment process is followed by a plasma cleaning step, a degreasing and washing step, and a deposition process for several seconds in a 50 wt% HNO 3 solution. After washing with water again through the acid treatment process, the palladium treatment process is performed.
본 발명의 바람직한 일실시예에서 팔라듐 핵의 생성 공정은 PdCl22H2O 0.1g/ℓ와 35%의 HCl 1㎖/ℓ를 혼합한 용액에 수초간 침적시켜 팔라듐 핵을 형성시킨다.이때 형성되는 팔라듐 핵은 기존의 PCB 제조 공정 중 Through Hole 도금에 주로 사용되는 촉매와는 달리 웨이퍼의 본딩 패드인 금속에만 형성이 되고, 비금속재인 패시베이션막에는 형성되지 않는 특징이 있다. 따라서 별도의 마스크 없이 패드에만 팔라듐 핵을 형성시킬 수 있는 것이다.In a preferred embodiment of the present invention, the palladium nucleus formation step is deposited for several seconds in a solution containing 0.1 g / l PdCl 2 2H 2 O and 1 ml / l of 35% HCl to form a palladium nucleus. Unlike the catalyst mainly used for through hole plating in a conventional PCB manufacturing process, the palladium nucleus is formed only on a metal, which is a bonding pad of a wafer, and is not formed on a passivation film, which is a non-metal material. Therefore, palladium nuclei can be formed only in the pad without a separate mask.
이렇게 팔라듐 핵을 형성시킨 후 90~95wt%의 니켈(Ni)과 5~10wt%의 인(P)으로 무전해 니켈도금층을 전착시킨다. 이를 수세 처리 후 침적 금도금을 행하여 열탕으로 수세처리하여 Ni/Au UBM층을 형성시킨다.After the palladium nucleus is formed, the electroless nickel plated layer is electrodeposited with 90 to 95 wt% nickel (Ni) and 5 to 10 wt% phosphorus (P). This was washed with water and then immersed in gold plating to wash with hot water to form a Ni / Au UBM layer.
이상에서 설명한 것은 본 발명의 바람직한 실시예에 대해 기술한 것으로, 본 발명이 속하는 기술 분야에 있어서 통상의 지식을 가진 사람이라면, 본 발명의 정신과 범위를 벗어나지 않으면서 본 발명을 변경 또는 변형 사용할 수 있을 것이다. 따라서 본 발명의 기술적 보호 범위는 상술한 실시예에 한하지 않으며, 하기 특허청구범위의 기술적 사상에 의해 정해져야 할 것이다.What has been described above has been described with respect to the preferred embodiments of the present invention, those skilled in the art to which the present invention belongs, it is possible to change or modify the present invention without departing from the spirit and scope of the present invention. will be. Therefore, the technical protection scope of the present invention is not limited to the above-described embodiment, but should be determined by the technical spirit of the following claims.
상기와 같은 본 발명에 따르면, 전기화학적으로 귀(貴)한 금속인 팔라듐(Pd)핵을 사용하여 무전해 Ni/Au 도금층을 형성함으로서, 부식환경하에서 산화반응속도를 감소시켜 내식성을 증대시킬 수 있을 뿐 아니라, 전체적인 패키지 신뢰도의 향상에 큰 효과를 얻을 수 있다.According to the present invention as described above, by forming an electroless Ni / Au plating layer using an electrochemically precious metal palladium (Pd) nucleus, it is possible to increase the corrosion resistance by reducing the oxidation reaction rate in a corrosive environment. Not only that, but the overall package reliability can be greatly improved.
Claims (8)
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| KR1020010010733A KR20020070584A (en) | 2001-03-02 | 2001-03-02 | Method of forming under bump metallurgy and structure thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100910772B1 (en) * | 2005-07-05 | 2009-08-04 | 삼성테크윈 주식회사 | Flip-chip package for image sensor and compact camera module comprising the same |
| US9899584B2 (en) | 2014-11-10 | 2018-02-20 | Samsung Electronics Co., Ltd. | Semiconductor device and package including solder bumps with strengthened intermetallic compound |
| CN111742395A (en) * | 2018-02-22 | 2020-10-02 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
-
2001
- 2001-03-02 KR KR1020010010733A patent/KR20020070584A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100910772B1 (en) * | 2005-07-05 | 2009-08-04 | 삼성테크윈 주식회사 | Flip-chip package for image sensor and compact camera module comprising the same |
| US9899584B2 (en) | 2014-11-10 | 2018-02-20 | Samsung Electronics Co., Ltd. | Semiconductor device and package including solder bumps with strengthened intermetallic compound |
| CN111742395A (en) * | 2018-02-22 | 2020-10-02 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
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