KR20020052456A - Manufacturing method for transistor of semiconductor device - Google Patents
Manufacturing method for transistor of semiconductor device Download PDFInfo
- Publication number
- KR20020052456A KR20020052456A KR1020000081742A KR20000081742A KR20020052456A KR 20020052456 A KR20020052456 A KR 20020052456A KR 1020000081742 A KR1020000081742 A KR 1020000081742A KR 20000081742 A KR20000081742 A KR 20000081742A KR 20020052456 A KR20020052456 A KR 20020052456A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- epitaxial
- layer
- forming
- entire surface
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 18
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 43
- 238000005530 etching Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자의 트랜지스터 제조방법에 관한 것으로, 보다 상세하게 DRAM의 주변회로부에 형성되는 트랜지스터의 소오스/드레인영역에 에피택셜 Si층과 에피택셜 SiGe층의 적층층구조를 형성하여 소오스/드레인전극을 형성함으로써 콘택 저항을 감소시키고, 그에 따른 소자의 동작 특성을 향상시키는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device. More particularly, the source / drain electrode is formed by forming a stacked layer structure of an epitaxial Si layer and an epitaxial SiGe layer in a source / drain region of a transistor formed in a peripheral circuit portion of a DRAM. The present invention relates to a method for manufacturing a semiconductor device by reducing the contact resistance, thereby improving the operating characteristics of the device.
일반적으로, P형 또는 N형 반도체기판에 N 또는 P형 불순물로 형성되는 PN접합은 불순물을 반도체기판에 이온주입한 후, 열처리로 활성화시켜 확산영역을 형성한다.In general, a PN junction formed of an N or P-type impurity on a P-type or N-type semiconductor substrate is ion implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region.
따라서, 채널의 폭이 감소된 반도체소자에서는 확산영역으로부터의 측면확산에 의한 쇼트 채널 이펙트(short channel effect)를 방지하기 위하여 접합 깊이를 얕게 형성해야 한다.Therefore, in a semiconductor device having a reduced channel width, the junction depth must be shallow in order to prevent short channel effects due to side diffusion from the diffusion region.
이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 트랜지스터 제조방법에 대하여 설명한다.Hereinafter, a transistor manufacturing method of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 트랜지스터 제조방법에 의한 공정 단면도로서, DRAM의 주변회로영역에서 트랜지스터를 형성하는 경우를 도시한다.1A and 1B are cross-sectional views illustrating a process of manufacturing a transistor of a semiconductor device according to the prior art, and illustrate a case of forming a transistor in a peripheral circuit region of a DRAM.
먼저, 반도체기판(11)에서 활성영역을 정의하는 소자분리절연막(13)을 형성한다.First, an isolation layer 13 for defining an active region of a semiconductor substrate 11 is formed.
다음, 전체표면 상부에 게이트 절연막, 다결정실리콘층 및 마스크절연막을 형성한다.Next, a gate insulating film, a polysilicon layer, and a mask insulating film are formed over the entire surface.
그 다음, 게이트 전극 마스크를 식각마스크로 사용하여 상기 마스크절연막, 다결정실리콘층 및 게이트 절연막을 식각하여 마스크절연막패턴(19), 게이트 전극(17) 및 게이트절연막패턴(15)의 적층구조를 형성한다.Next, the mask insulating film, the polysilicon layer, and the gate insulating film are etched using a gate electrode mask as an etching mask to form a stacked structure of the mask insulating film pattern 19, the gate electrode 17, and the gate insulating film pattern 15. .
다음, 상기 적층구조의 양측 반도체기판(11)에 저농도의 불순물을 이온주입시켜 엘.디.디.(lightly doped drain, LDD)영역(21)을 형성한다.Next, a low concentration of impurities are implanted into both semiconductor substrates 11 of the stacked structure to form a lightly doped drain (LDD) region 21.
그리고, 전체표면 상부에 절연막을 형성한 다음, 전면식각하여 상기 적층구조의 측벽에 절연막 스페이서(23)를 형성한다.Then, an insulating film is formed on the entire surface and then etched to form an insulating film spacer 23 on the sidewall of the stacked structure.
그 후, 상기 절연막 스페이서(23)의 양쪽 반도체기판(11)에 고농도의 불순물을 이온주입시켜 소오스/드레인영역(25)을 형성한다. (도 1a 참조)Thereafter, a high concentration of impurities are ion implanted into both semiconductor substrates 11 of the insulating film spacer 23 to form the source / drain regions 25. (See Figure 1A)
그 후, 전체표면 상부에 상기 소오스/드레인영역(25)에서 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비되는 층간절연막(27)을 형성한다.Thereafter, an interlayer insulating film 27 having a contact hole for exposing a portion of the source / drain region 25 to be a contact in the source / drain region 25 is formed over the entire surface.
그 다음, 전체표면 상부에 금속층을 형성한 후 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP라 함)공정 또는 전면식각공정으로 상기 콘택홀을 매립하는 콘택플러그(29)를 형성한다. (도 1b 참조)Next, after forming a metal layer on the entire surface, a contact plug 29 for filling the contact hole is formed by a chemical mechanical polishing (CMP) process or an entire surface etching process. (See FIG. 1B)
도 2 는 종래기술에 의해 형성된 트랜지스터의 소오스/드레인영역 깊이에 따른 도핑농도를 도시하는 그래프로서, 소오스/드레인영역의 깊이가 깊을수록 도핑농도가 낮아지는 것을 도시한다. (도 2 참조)FIG. 2 is a graph showing the doping concentration according to the source / drain region depth of a transistor formed by the prior art, and the deeper the source / drain region, the lower the doping concentration. (See Figure 2)
그러나, 상기와 같이 종래기술에 따른 반도체소자의 트랜지스터 제조방법은, 반도체소자가 고집적화되어 감에 따라 쇼트 채널 이펙트(short channel effect)가 발생하는 것을 방지하기 위하여 반도체기판의 주변회로영역의 트랜지스터의 소오스/드레인영역을 얕은 접합(shallow junction)으로 형성하였다. 그러나, 낮은 에너지를 이용하여 이온주입공정을 실시하여 형성된 얕은 접합영역은 콘택홀을 형성하기 위한 식각공정 시 손상되기 때문에 고농도로 이온주입된 영역이 줄어들고, 금속배선 콘택플러그와의 콘택저항을 증가시켜 소자의 동작 특성 및 수율을 저하시키는 문제점이 있다.However, in the transistor manufacturing method of the semiconductor device according to the prior art as described above, the source of the transistor in the peripheral circuit region of the semiconductor substrate in order to prevent the short channel effect occurs as the semiconductor device is highly integrated Drain regions were formed with shallow junctions. However, since the shallow junction region formed by the ion implantation process using low energy is damaged during the etching process to form the contact hole, the region implanted at a high concentration is reduced, and the contact resistance with the metal wiring contact plug is increased. There is a problem of lowering the operation characteristics and the yield of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 게이트전극 양측의 반도체기판에 에피택셜 Si층과 에피택셜 SiGe층의 적층구조를 형성한 다음, 상기 적층구조에 고농도의 불순물을 이온주입하여 엘리베이티드 소오스/드레인영역을 형성함으로써 후속 콘택공정을 용이하고, 콘택저항을 감소시켜 소자의 동작 속도를 향상시키는 반도체소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, an epitaxial Si layer and an epitaxial SiGe layer are formed on a semiconductor substrate on both sides of a gate electrode, and then ion implantation is carried out with a high concentration of impurities in the laminated structure. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device that facilitates subsequent contact processes by forming a sourced / drain region, and reduces contact resistance to improve the operation speed of the device.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 트랜지스터 제조방법에 의한 공정 단면도.1A and 1B are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to the prior art.
도 2 는 종래기술에 의해 형성된 트랜지스터의 소오스/드레인영역 깊이에 따른 도핑농도를 도시하는 그래프.2 is a graph showing the doping concentration according to the source / drain region depth of a transistor formed by the prior art.
도 3a 내지 도 3e 는 본 발명에 따른 반도체소자의 트랜지스터 제조방법에 의한 공정 단면도.3A to 3E are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to the present invention.
도 4a 내지 도 4c 는 본 발명에 의해 형성된 트랜지스터의 전기적 특성을 도시한 그래프.4A-4C are graphs showing the electrical properties of a transistor formed by the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11, 31 : 반도체기판 13, 33 : 소자분리절연막11, 31: semiconductor substrate 13, 33: device isolation insulating film
15, 35 : 게이트절연막패턴 17, 37 : 게이트전극15, 35: gate insulating film pattern 17, 37: gate electrode
19, 39 : 마스크절연막패턴 21 : LDD영역19, 39: mask insulating film pattern 21: LDD region
23 : 절연막 스페이서 25, 40 : 소오스/드레인영역23: insulating film spacer 25, 40: source / drain region
27, 51 : 층간절연막 29, 53 : 콘택플러그27, 51: interlayer insulating film 29, 53: contact plug
41 : 제1절연막 스페이서 43 : 에피택셜 Si층41: first insulating film spacer 43: epitaxial Si layer
45 : 에피택셜 SiGe층 47 : 제2절연막 스페이서45 epitaxial SiGe layer 47 second insulating film spacer
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 게이트절연막패턴, 게이트전극 및 마스크절연막패턴의 적층구조를 형성하는 공정과,Forming a stacked structure of a gate insulating film pattern, a gate electrode, and a mask insulating film pattern on the semiconductor substrate;
상기 적층구조의 양측 기판에 LDD영역을 형성하는 공정과,Forming LDD regions on both substrates of the laminated structure;
전체표면 상부에 제1절연막을 형성한 후, 상기 제1절연막을 전면식각하여 상기 적층구조의 측벽에 제1절연막 스페이서를 형성하는 공정과,Forming a first insulating film spacer on the sidewall of the laminate structure by forming a first insulating film on the entire surface, and then etching the entire surface of the first insulating film;
상기 LDD영역에 에피택셜 Si층을 성장시키는 공정과,Growing an epitaxial Si layer in the LDD region;
상기 에피택셜 Si층 상부에 에피택셜 SiGe층을 형성시키는 공정과,Forming an epitaxial SiGe layer on the epitaxial Si layer;
전체표면 상부에 제2절연막을 형성하고, 상기 제2절연막을 전면식각하여 상기 제1절연막 스페이서 측벽에 제2절연막 스페이서를 형성하는 공정과,Forming a second insulating film on the entire surface, and etching the entire surface of the second insulating film to form a second insulating film spacer on sidewalls of the first insulating film spacer;
전체표면 상부에 고농도의 불순물을 이온주입하여 상기 에피택셜 SiGe층과 에피택셜 Si층을 엘리베이티드 소오스/드레인영역으로 형성하는 공정과,Forming an epitaxial SiGe layer and an epitaxial Si layer as an elevated source / drain region by implanting a high concentration of impurities onto the entire surface;
전체표면 상부에 상기 엘리베이티드 소오스/드레인영역에서 콘택으로 예정되는 부분에 접속되는 금속배선 콘택플러그가 구비된 층간절연막을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming an interlayer insulating film having a metal wiring contact plug connected to a portion of the elevated source / drain region that is to be contacted on the entire surface.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3e 는 본 발명에 따른 반도체소자의 트랜지스터 제조방법에 의한 공정 단면도로서, DRAM의 주변회로영역에서 트랜지스터를 형성하는 경우를 도시한다.3A to 3E are cross-sectional views illustrating a process of manufacturing a transistor of a semiconductor device according to the present invention, and illustrate a case of forming a transistor in a peripheral circuit region of a DRAM.
먼저, 반도체기판(31)에서 활성영역을 정의하는 소자분리절연막(33)을 형성한다.First, a device isolation insulating film 33 defining an active region in the semiconductor substrate 31 is formed.
다음, 전체표면 상부에 게이트 절연막, 다결정실리콘층 및 마스크절연막을 형성한다.Next, a gate insulating film, a polysilicon layer, and a mask insulating film are formed over the entire surface.
그 다음, 게이트 전극 마스크를 식각마스크로 사용하여 상기 마스크절연막,다결정실리콘층 및 게이트 절연막을 식각하여 마스크절연막패턴(39), 게이트 전극(37) 및 게이트절연막패턴(35)의 적층구조를 형성한다.Next, the mask insulating film, the polysilicon layer, and the gate insulating film are etched using a gate electrode mask as an etching mask to form a stacked structure of the mask insulating film pattern 39, the gate electrode 37, and the gate insulating film pattern 35. .
다음, 상기 적층구조의 양측 반도체기판(31)에 저농도의 불순물을 이온주입시켜 엘.디.디.(lightly doped drain, LDD)영역(40)을 형성한다.Next, a low concentration of impurities are implanted into both semiconductor substrates 31 of the stacked structure to form a lightly doped drain (LDD) region 40.
그리고, 전체표면 상부에 제1절연막을 형성한 다음, 전면식각하여 상기 적층구조의 측벽에 제1절연막 스페이서(41)를 형성한다.The first insulating layer is formed on the entire surface, and then etched to form a first insulating layer spacer 41 on the sidewall of the stacked structure.
다음, 상기 LDD영역(40), 즉 노출되는 반도체기판(31)에 에피택셜 Si층(43)을 소정 두께 성장시킨다. (도 3a 참조)Next, the epitaxial Si layer 43 is grown to a predetermined thickness in the LDD region 40, that is, the exposed semiconductor substrate 31. (See Figure 3A)
그 다음, 상기 에피택셜 Si층(43) 상부에 에피택셜 SiGe층(45)을 소정 두께 성장시킨다. (도 3b 참조)Next, an epitaxial SiGe layer 45 is grown on the epitaxial Si layer 43 by a predetermined thickness. (See Figure 3b)
다음, 전체표면 상부에 제2절연막을 형성하고, 상기 제2절연막을 전면식각하여 상기 제1절연막 스페이서(41)의 측벽에 제2절연막 스페이서(47)를 형성한다. 이때, 상기 제2절연막 스페이서(47)는 상기 제1절연막 스페이서(41)와 에피택셜 SiGe층(45) 사이의 노치(notch)를 감싸기 위하여 형성된다. (도 3c 참조)Next, a second insulating film is formed on the entire surface, and the second insulating film is etched entirely to form a second insulating film spacer 47 on sidewalls of the first insulating film spacer 41. In this case, the second insulating film spacer 47 is formed to surround the notch between the first insulating film spacer 41 and the epitaxial SiGe layer 45. (See Figure 3c)
그 다음, 상기 구조 상부에 고농도의 불순물을 이온주입하여 상기 에피택셜 SiGe층(45) 및 에피택셜 Si층(43)을 엘리베이티드(elevated) 소오스/드레인영역으로 사용한다. (도 3d 참조)Next, a high concentration of impurities are ion-implanted on the structure to use the epitaxial SiGe layer 45 and the epitaxial Si layer 43 as an elevated source / drain region. (See FIG. 3D)
다음, 전체표면 상부에 상기 에피택셜 SiGe층(45)에서 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비되는 층간절연막(51)을 형성한다.Next, an interlayer insulating film 51 having a contact hole exposing a portion of the epitaxial SiGe layer 45 to be a contact is formed on the entire surface.
그 다음, 전체표면 상부에 금속층을 형성한 후 CMP공정 또는 전면식각공정으로 상기 콘택홀을 매립하는 콘택플러그(53)를 형성한다.Next, after forming a metal layer on the entire surface, a contact plug 53 for filling the contact hole is formed by a CMP process or an entire surface etching process.
한편, 상기 에피택셜 SiGe층(45)은 상기 에피택셜 Si층(43)에 Ge를 이온주입하여 형성될 수 있으며, 상기 제2질화막 스페이서(47)는 상기 에피택셜 Si층(43)을 성장시킨 직후 형성될 수도 있다. (도 3e 참조)The epitaxial SiGe layer 45 may be formed by ion implantation of Ge into the epitaxial Si layer 43, and the second nitride layer spacer 47 may be formed by growing the epitaxial Si layer 43. It may be formed immediately. (See Figure 3E)
도 4a 내지 도 4c 는 본 발명에 의해 형성된 트랜지스터의 전기적 특성을 도시한 그래프이다.4A to 4C are graphs showing the electrical characteristics of the transistor formed by the present invention.
도 4a 및 도 4b 는 종래기술에 비해 콘택저항 및 면저항이 감소되는 것을 도시한다.4A and 4B show that the contact resistance and the sheet resistance are reduced compared to the prior art.
그리고, 도 4c 는 누적확률(cumulative probability)와 접합누설전류 간의 관계를 도시하는 것으로서, 에피택셜 Si막에 비하여 에피택셜 SiGe막의 누설전류가 크게 분포하는 것을 도시한다.4C shows the relationship between cumulative probability and junction leakage current, and shows that the leakage current of the epitaxial SiGe film is larger than that of the epitaxial Si film.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 트랜지스터 제조방법은, 반도체기판 상부에 게이트전극을 형성하고, 상기 게이트전극의 양측 반도체기판에 LDD영역을 저농도 접합영역을 형성한 다음, 상기 게이트전극의 측벽에 제1절연막 스페이서를 형성한 후, 상기 제1절연막 스페이서 양측 반도체기판에 에피택셜 Si층과 에피택셜 SiGe층의 적층구조를 형성한 다음, 상기 적층구조에 고농도의 불순물을 이온주입하여 상기 적층구조를 엘리베이티드 소오스/드레인영역으로 형성함으로써 쇼트 채널 이펙트를 개선하는 동시에 후속 콘택공정을 용이하여 콘택저항을 감소시키고, 트랜지스터의 전기적 특성을 향상시키고, 그로 인하여 소자의 동작속도를 향상시키는 이점이 있다.As described above, in the method of manufacturing a transistor of a semiconductor device according to the present invention, a gate electrode is formed on a semiconductor substrate, LDD regions are formed on both semiconductor substrates of the gate electrode, and a low concentration junction region is formed. After the first insulating film spacer is formed on the sidewalls, a lamination structure of an epitaxial Si layer and an epitaxial SiGe layer is formed on both semiconductor substrates of the first insulating film spacer, and a high concentration of impurities are ion implanted into the lamination structure to form the lamination structure. By forming the structure as an elevated source / drain region, the short channel effect can be improved, and subsequent contact processes can be easily reduced, thereby reducing contact resistance, improving transistor electrical characteristics, and thereby improving device operation speed. .
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000081742A KR100649821B1 (en) | 2000-12-26 | 2000-12-26 | Manufacturing method for transistor of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000081742A KR100649821B1 (en) | 2000-12-26 | 2000-12-26 | Manufacturing method for transistor of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020052456A true KR20020052456A (en) | 2002-07-04 |
| KR100649821B1 KR100649821B1 (en) | 2006-11-24 |
Family
ID=27685763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000081742A KR100649821B1 (en) | 2000-12-26 | 2000-12-26 | Manufacturing method for transistor of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100649821B1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100712535B1 (en) * | 2005-09-26 | 2007-04-27 | 삼성전자주식회사 | Semiconductor device having selective epitaxial layer suppressible lateral growth and method of manufacturing the same |
| KR100714401B1 (en) * | 2006-02-08 | 2007-05-04 | 삼성전자주식회사 | Semiconductor device having stacked transistors and method of forming the same |
| KR100876835B1 (en) * | 2007-07-03 | 2009-01-07 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR100968422B1 (en) * | 2008-04-18 | 2010-07-07 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR101006525B1 (en) * | 2008-09-19 | 2011-01-07 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR20160022936A (en) * | 2009-12-30 | 2016-03-02 | 인텔 코포레이션 | Self-aligned contacts |
-
2000
- 2000-12-26 KR KR1020000081742A patent/KR100649821B1/en not_active IP Right Cessation
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100712535B1 (en) * | 2005-09-26 | 2007-04-27 | 삼성전자주식회사 | Semiconductor device having selective epitaxial layer suppressible lateral growth and method of manufacturing the same |
| KR100714401B1 (en) * | 2006-02-08 | 2007-05-04 | 삼성전자주식회사 | Semiconductor device having stacked transistors and method of forming the same |
| KR100876835B1 (en) * | 2007-07-03 | 2009-01-07 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR100968422B1 (en) * | 2008-04-18 | 2010-07-07 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR101006525B1 (en) * | 2008-09-19 | 2011-01-07 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR20160022936A (en) * | 2009-12-30 | 2016-03-02 | 인텔 코포레이션 | Self-aligned contacts |
| US9508821B2 (en) | 2009-12-30 | 2016-11-29 | Intel Corporation | Self-aligned contacts |
| US9892967B2 (en) | 2009-12-30 | 2018-02-13 | Intel Corporation | Self-aligned contacts |
| KR20180108872A (en) * | 2009-12-30 | 2018-10-04 | 인텔 코포레이션 | Self-aligned contacts |
| US10141226B2 (en) | 2009-12-30 | 2018-11-27 | Intel Corporation | Self-aligned contacts |
| US10629483B2 (en) | 2009-12-30 | 2020-04-21 | Intel Corporation | Self-aligned contacts |
| US10930557B2 (en) | 2009-12-30 | 2021-02-23 | Intel Corporation | Self-aligned contacts |
| US11600524B2 (en) | 2009-12-30 | 2023-03-07 | Intel Corporation | Self-aligned contacts |
| US11887891B2 (en) | 2009-12-30 | 2024-01-30 | Intel Corporation | Self-aligned contacts |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100649821B1 (en) | 2006-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5937297A (en) | Method for making sub-quarter-micron MOSFET | |
| KR20030056604A (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR100649821B1 (en) | Manufacturing method for transistor of semiconductor device | |
| KR100540341B1 (en) | Fabricating method of semiconductor device | |
| KR100341182B1 (en) | Method of forming mos transistor in semiconductor device | |
| KR100419024B1 (en) | Method for manufacturing a transistor | |
| KR20040056953A (en) | Mehod for fabricating of semiconductor device | |
| US6720224B2 (en) | Method for forming transistor of semiconductor device | |
| KR100734259B1 (en) | Method for fabricating semiconductor devices | |
| KR100503745B1 (en) | Method for fabricating semiconductor device | |
| KR0161873B1 (en) | Method of manufacturing semiconductor device | |
| KR20030002519A (en) | Forming method for transistor of semiconductor device | |
| KR100254045B1 (en) | Method for manufacturing semiconductor device | |
| KR100625392B1 (en) | Manufacturing method for semiconductor device | |
| KR20010066328A (en) | A method for fabricating a transistor of a semiconductor device | |
| KR100832706B1 (en) | Semiconductor device and method of fabricating the same | |
| KR100274604B1 (en) | Method for fabricating semiconductor device | |
| KR100567030B1 (en) | Methood for manufacturing Transistor | |
| KR20090088677A (en) | Semiconductor device and method for manufacturing the same | |
| KR20040058832A (en) | Soi semiconductor device and method for manufacturing the same | |
| KR20030097344A (en) | Method for fabrication of cmos transistor | |
| KR19990009248A (en) | Transistors and manufacturing methods thereof | |
| KR19980060634A (en) | Manufacturing method of MOS field effect transistor | |
| KR20030001922A (en) | Method of manufacturing a semiconductor device | |
| KR20010058938A (en) | Method for manufacturing transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101025 Year of fee payment: 5 |
|
| LAPS | Lapse due to unpaid annual fee |