KR20020032115A - Preventing method of gate oxide damage in a semiconductor device - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 230000015556 catabolic process Effects 0.000 claims abstract description 19
- 230000005641 tunneling Effects 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 2
- 239000002019 doping agent Substances 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 5
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 101150098265 TDP2 gene Proteins 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 235000020030 perry Nutrition 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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Abstract
Description
본 발명은 반도체장치의 게이트산화막 손상방지방법에 관한 것으로서, 특히, 게이트산화막에서의 F-N(Fowler-Nordheim) 터널링이 일어나지 않도록 하기 위하여 게이트라인 단부에 항복전압이 낮은 다이오드를 형성하여 전자를 기판으로 빠져나가게 하므로서 길게 연장된 모스트랜지스터의 게이트라인에 의한 안테나효과에 의하여 게이트산화막이 손상되는 것을 방지하도록 한 반도체장치의 플라즈마에 의한 게이트산화막 손상방지방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for preventing damage to a gate oxide film of a semiconductor device. In particular, a diode having a low breakdown voltage is formed at an end of a gate line to prevent electrons from falling into a substrate in order to prevent Fowler-Nordheim (FN) tunneling from occurring in the gate oxide film. The present invention relates to a method of preventing gate oxide film damage by plasma of a semiconductor device which prevents the gate oxide film from being damaged by an antenna effect caused by a gate line of a long transistor having a long extension.
일반적으로 모스 트랜지스터 제조시 다단계로 이루어진 PECVD(plasma enhanced chemical vapor deposition) 공정 및 반응성이온식각(RIE, reactive ion etch)를 진행하게 된다. 이와 같이 플라즈마 또는 반응성이온을 사용하는 공정들은 얇은 게이트산화막에의 전기적 스트레스 및 손상의 원인이 되는 것으로 알려져 있다.In general, a multi-step plasma enhanced chemical vapor deposition (PECVD) process and reactive ion etching (RIE) are performed during the manufacture of a MOS transistor. As such, processes using plasma or reactive ions are known to cause electrical stress and damage to the thin gate oxide layer.
플라즈마를 사용하는 공정중에 게이트에 모인 전기적 차지에 의해 게이트산화막에 고전계(high electrical field)가 걸리면, 게이트산화막을 통하여 F-N 터널링 전류가 흐르게 되고, 이러한 현상은 계면트랩(interface trap) 또는 전자트랩(electron ttrap)의 원인이 된다. 이러한 트랩들은 게이트산화막의 특성을 열화시켜 트랜지스터의 신뢰성을 저하시킨다.If a high electrical field is applied to the gate oxide film due to the electrical charge collected in the gate during the process using plasma, the FN tunneling current flows through the gate oxide film, and this phenomenon is caused by an interface trap or an electronic trap ( electron ttrap). These traps deteriorate the characteristics of the gate oxide film and degrade the reliability of the transistor.
특히, MDL(Merged DRAM and Logic)소자 제조시, 게이트산화막의 두께가 40Å 이하로 얇아지면 게이트의 안테나 효과에 의한 게이트산화막의 열화는 심화된다.In particular, in the manufacture of MDL (Merged DRAM and Logic) devices, when the thickness of the gate oxide film becomes thinner than 40 mW, the degradation of the gate oxide film due to the antenna effect of the gate is intensified.
도 1a 와 도 1b는 각각 종래의 반도체장치의 플라즈마 손상 완화방법에 의하여 제조된 소자의 평면도와 단면도이다. 이때 단면도는 도 1a의 절단선 I-I에 의한 단면을 도시한 것이다.1A and 1B are a plan view and a cross-sectional view, respectively, of a device manufactured by a plasma damage mitigation method of a conventional semiconductor device. In this case, the cross-sectional view is a cross-sectional view taken by the cutting line I-I of FIG. 1A.
도 1a와 도 1b를 참조하면, 소자격리용 필드산화막(15)이 형성된 실리콘기판(11) 위에 모스 트랜지스터가 작동하는 게이트(17)와 그 주변부에 소스/드레인 활성영역(171)이 도시되어 있고 도면상 나타나지는 아니하였지만 게이트(17)와 활성영역(171)이 중첩되는 부위가 채널영역이 된다. 이때 게이트는 A 방향으로 길게 형성되어 전자를 집속하는 다양한 패턴의 안테나를 구성한다. 게이트(17) 형성을 위한 건식식각시 이러한 안테나의 주변길이에 비례하여 플라즈마로부터 많은 양의 전류가 집속되어 게이트 하단에 위치한 게이트산화막(16)으로 흐르게 된다. 이때 게이트산화막(16)의 두께가 60Å 이면, 게이트산화막(16)을 관통하는 전류는 F/N 터널링에 의하여 흐르게 된다.Referring to FIGS. 1A and 1B, a gate 17 on which a MOS transistor operates and a source / drain active region 171 are shown on a silicon substrate 11 on which a device isolation field oxide film 15 is formed. Although not shown in the drawing, a portion where the gate 17 and the active region 171 overlap is a channel region. At this time, the gate is formed long in the A direction to form an antenna of various patterns that focus electrons. In the dry etching process for forming the gate 17, a large amount of current is focused from the plasma in proportion to the peripheral length of the antenna and flows to the gate oxide layer 16 located at the bottom of the gate. At this time, when the thickness of the gate oxide film 16 is 60 kW, the current passing through the gate oxide film 16 flows by F / N tunneling.
도 2a 도 내지 도 2h는 종래의 기술에 의한 반도체장치의 플라즈마 손상 완화방법을 도시한 단면도이다.2A to 2H are cross-sectional views illustrating a plasma damage alleviation method of a semiconductor device according to the related art.
도 2a 를 참조하면, 실리콘기판(11) 위에 산화막(12)과 질화막(13)을 차례로 증착하여 형성한 다음 사진공정을 실시하여 질화막(13)의 상부 표면의 소정 부위에 활성영역 형성용 제 1 포토레지스트패턴(14)을 정의한다.Referring to FIG. 2A, an oxide film 12 and a nitride film 13 are sequentially formed on a silicon substrate 11, and then a photolithography process is performed to form an active region on a predetermined portion of an upper surface of the nitride film 13. The photoresist pattern 14 is defined.
도 2b를 참조하면, 제 1 포토레지스트패턴(14)을 식각마스크로이용한 건식식각을 실시하여 이로부터 보호되지 아니하는 부위의 질화막(13)과 산화막(12)을 제거한 다음 제 1 포토레지스트패턴(14)을 제거한다.Referring to FIG. 2B, dry etching using the first photoresist pattern 14 as an etch mask is performed to remove the nitride film 13 and the oxide film 12 from portions not protected from the first photoresist pattern 14, and then the first photoresist pattern ( 14) Remove.
그리고 잔류한 질화막(13)을 마스크로 이용하여 노출된 실리콘기판(11)을 300 nm 정도 제거한다.Then, the exposed silicon substrate 11 is removed by about 300 nm using the remaining nitride film 13 as a mask.
도 2c를 참조하면, 필드산화막(15)을 형성하기 위하여 기판(11)의 전면에 에이치디피 산화막(15)(high density plasma)을 증착하여 형성한 다음 씨엠피(chemical mechanical polishing)공정을 실시하여 전체 표면을 평탄화시킨다.Referring to FIG. 2C, in order to form the field oxide film 15, a high density plasma is deposited on the entire surface of the substrate 11, followed by a chemical mechanical polishing process. Plane the entire surface.
도 2d를 참조하면, 잔류한 질화막을 제거한 다음 모스 트랜지스터의 문턱전압을 조절하기 위한 채널이온 주입을 실시하여 잔류한 산화막(12) 하부의 실리콘층에 소정의 불순물 이온을 주입한다.Referring to FIG. 2D, after removing the remaining nitride film, a channel ion implantation is performed to control the threshold voltage of the MOS transistor to implant a predetermined impurity ion into the silicon layer under the remaining oxide film 12.
도 2e를 참조하면, 활성영역이 형성될 부위에 잔류한 산화막을 제거한 다음 노출된 기판(11) 표면에 게이트산화막(16)을 형성한다. 그리고 기판의 전면에 게이트전극(17)을 형성하기 위하여 기판의 전면에 폴리실리콘층(17)을 증착하여 형성한다.Referring to FIG. 2E, the oxide film remaining on the portion where the active region is to be formed is removed, and then the gate oxide film 16 is formed on the exposed surface of the substrate 11. The polysilicon layer 17 is deposited on the entire surface of the substrate to form the gate electrode 17 on the entire surface of the substrate.
그리고 게이트전극 형성용 제 2 포토레지스트패턴(18)을 폴리실리콘층(17) 위에 형성하고 이를 이용한 건식식각공정을 실시하여 게이트전극(17)을 패터닝한다.The gate electrode 17 is patterned by forming a second photoresist pattern 18 for forming a gate electrode on the polysilicon layer 17 and performing a dry etching process using the same.
이때, 경로 ①은 총 연장길이가 수만 ㎛에 달하는 안테나에 연결되어 많은 양의 전류가 집속되어 게이트산화막(16)을 통하여 기판(11)의 실리콘층으로 유입되는 한편, 게이트 종단 부위 방향인 경로 ②로 부터 들어오는 전류의 양은 무시할 수 있다.At this time, the path ① is connected to the antenna having a total extension length of tens of thousands of micrometers, and a large amount of current is focused and flows into the silicon layer of the substrate 11 through the gate oxide film 16, while the path ② is in the direction of the gate termination region. The amount of current coming from is negligible.
도 2f를 참조하면, 제 2 포토레지스트패턴을 제거하여 게이트전극(17)의 표면을 노출시킨다.Referring to FIG. 2F, the surface of the gate electrode 17 is exposed by removing the second photoresist pattern.
도 2g를 참조하면, 기판(11)의 전면에 콘택용 산화막(19)을 증착하여 형성한 다음, 콘택홀 형성용 제 3 포토레지스트 패턴(20)을 정의한 다음 이로부터 보호되지 아니하는 부위의 콘택용 산화막(19)을 건식식각으로 제거하여 게이트전극(17)의 일부표면을 다시 노출시킨다.Referring to FIG. 2G, a contact oxide film 19 is formed on the entire surface of the substrate 11, and then a third photoresist pattern 20 for forming a contact hole is defined, and then a contact of a portion that is not protected therefrom. The molten oxide film 19 is removed by dry etching to expose a part of the surface of the gate electrode 17 again.
이때에도 역시, 게이트 상부에 형성되는 콘택홀의 갯수에 비례하여 건식식각용 플라즈마로부터 많은 전류가 게이트전극(19)과 게이트산화막(16)을 통하여 기판(11)의 실리콘층으로 유입된다.In this case, too, a large amount of current flows from the dry etching plasma to the silicon layer of the substrate 11 through the gate electrode 19 and the gate oxide layer 16 in proportion to the number of contact holes formed on the gate.
도 2h를 참조하면, 제 3 포토레지스트 패턴(20)을 제거한 다음, 금속배선(21)을 기판(11)의 전면에 증착하고 제 4 포토레지스트 패턴(22)을 정의하고 이를 이용한 건식식각을 실시하여 금속배선(21)을 패터닝한다. 이때에도 역시, 전술한 동일한 현상으로 많은 양의 전류가 실리콘층으로 침투한다.Referring to FIG. 2H, after removing the third photoresist pattern 20, the metal wiring 21 is deposited on the entire surface of the substrate 11, the fourth photoresist pattern 22 is defined, and dry etching using the same is performed. The metal wiring 21 is patterned. At this time, too, a large amount of current penetrates into the silicon layer by the same phenomenon described above.
상술한 종래의 기술에 따른 건식식각시에는 게이트전극이 안테나로 작용하여 플라즈마로 부터 전류를 집속하여 이를 모스 트랜지스터의 게이트산화막을 F/N 터널링에 의하여 관통시켜 실리콘층으로 유입시키는 작용을 하므로서 게이트산화막에 전하가 저장되는 트랩(trap)의 수를 증가시키므로, 게이트산화막의 특성을 열화시켜 모스 소자의 문턱전압 및 동작전류를 변화시키고 소자의 내구성을 악화시키는 문제점이 있다.In the dry etching process according to the related art described above, the gate electrode acts as an antenna to focus current from the plasma, and passes the gate oxide film of the MOS transistor through F / N tunneling to flow into the silicon layer. Since the number of traps in which charges are stored is increased, there is a problem in that the characteristics of the gate oxide film are deteriorated, thereby changing the threshold voltage and operating current of the MOS device and deteriorating the durability of the device.
또한, 안테나 효과에 의하여 게이트에 전하가 축적되는 경우 F-N 터널링 전류가 발생하여 게이트 특성이 열화되는 것을 방지하기 위하여 게이트라인의 단부에 다이오드를 연결하는 경우, 종래 기술에서는 소스/드레인 형성시 다이오드를 동시에 형성하므로, 다이오드에 역방향 바이어스가 걸리면 F-N 터널링이 일어나는 전압보다 다이오드의 졍션항복전압(junction breakdown voltage)이 더 높아지게 되어 다이오드의 역할을 기대할 수 없게되므로, 결국, 게이트산화막을 통하여 F-N 터널링이 발생하게 되는 문제점이 있다.In addition, when a diode is connected to the end of the gate line to prevent the deterioration of the gate characteristics by generating an FN tunneling current when charge is accumulated in the gate due to the antenna effect, in the prior art, the diode is simultaneously formed when forming a source / drain. Therefore, if the reverse bias is applied to the diode, the junction breakdown voltage of the diode is higher than the voltage at which the FN tunneling occurs, so that the role of the diode cannot be expected. Consequently, FN tunneling occurs through the gate oxide. There is a problem.
따라서, 본 발명의 목적은 게이트산화막에서의 F-N(Fowler-Nordheim) 터널링이 일어나지 않도록 하기 위하여 게이트라인 단부에 항복전압이 낮은 다이오드를 형성하여 전자를 기판으로 빠져나가게 하므로서 길게 연장된 모스트랜지스터의 게이트라인에 의한 안테나효과에 의하여 게이트산화막이 손상되는 것을 방지하도록 한 반도체장치의 플라즈마에 의한 게이트산화막 손상방지방법을 제공하는데 있다.Accordingly, an object of the present invention is to form a diode having a low breakdown voltage at the gate line end in order to prevent FN (Fowler-Nordheim) tunneling in the gate oxide film to exit electrons to the substrate to extend the gate line of the long transistor The present invention provides a method of preventing damage to a gate oxide film caused by a plasma of a semiconductor device to prevent the gate oxide film from being damaged by an antenna effect.
상술한 목적을 달성하기 위하여 본 발명은 소자격리막에 의한 소자격리영역에 의하여 다이오드형성영역과 소자활성영역이 정의된 제 1 도전형 반도체 기판 위에 형성된 게이트산화막, 소스/드레인 및 게이트라인이 형성된 상기 기판의 상기 다이오드형성영역에 빗장형태의 다수개의 다이오드들을 형성하여 상기 게이트라인의 일단과 상기 다수개의 다이오드를 전기적으로 연결시키는 것을 포함하여 이루어진다. 바람직하게는, 상기 다이오드들은 상기 게이트산화막의 F-N터널링이 일어나는 전압보다 낮은 항복전압을 갖도록 형성하고, 또한, 상기 다이오드형성영역의 주변영역을 문턱전압 이온주입시의 에너지와 1E12 - 10E12 ions/㎤의 농도로 도핑시킨다.In order to achieve the above object, the present invention provides a substrate including a gate oxide film, a source / drain, and a gate line formed on a first conductive semiconductor substrate in which a diode formation region and a device active region are defined by a device isolation region by a device isolation layer. And forming a plurality of diodes in the form of a latch in the diode forming region of to electrically connect one end of the gate line to the plurality of diodes. Preferably, the diodes are formed to have a breakdown voltage lower than the voltage at which the FN tunneling of the gate oxide film occurs, and the peripheral region of the diode forming region is formed at a threshold voltage of 1E12-10E12 ions / cm3 Doping to concentration
도 1a 와 도 1b는 각각 종래의 반도체장치의 플라즈마 손상 완화방법에 의하여 제조된 소자의 평면도와 단면도1A and 1B are a plan view and a cross-sectional view, respectively, of a device manufactured by a plasma damage mitigation method of a conventional semiconductor device.
도 2a 도 내지 도 2h는 종래의 기술에 의한 반도체장치의 플라즈마 손상 완화방법을 도시한 단면도2A to 2H are cross-sectional views illustrating a plasma damage alleviation method of a semiconductor device according to the related art.
도 3은 본 발명에 따른 다이오드 형성영역과 소자활성영역이 도시된 반도체기판의 레이아웃3 is a layout of a semiconductor substrate showing a diode forming region and a device active region according to the present invention;
도 4는 본 발명에 따른 반도체장치의 게이트산화막 손상을 방지하기 위한 반도체장치의 레이아웃4 is a layout of a semiconductor device for preventing damage to a gate oxide film of the semiconductor device according to the present invention.
도 5는 본 발명에 따른 반도체장치의 게이트산화막 손상을 방지하기 위한 구조의 도 4의 절단선 Ⅱ-Ⅱ'에 따른 단면도FIG. 5 is a cross-sectional view taken along line II-II ′ of FIG. 4 of a structure for preventing gate oxide film damage of a semiconductor device according to the present invention.
도 6은 본 발명에 따른 반도체장치의 게이트산화막 손상을 방지하기 위한 구조의 도 4의 절단선 Ⅲ-Ⅲ'에 따른 단면도6 is a cross-sectional view taken along line III-III ′ of FIG. 4 of a structure for preventing damage to a gate oxide film of a semiconductor device according to the present invention.
본 발명에서는 F-N터널링이 일어나기 전에 다이오드의 파괴(breaskdpwn)가 먼저 발생하도록 하기 위하여 졍션 다이오드의 주변영역 누설량(peri region leakage)을 증가시키므로서, 종래의 다이오드에 비하여 항복전압(breakdown voltage)이 낮아지므로서 F-N 터널링 이전에 다이오드를 통해 게이트에 집속된 차지가 기판으로 흐르게되어 게이트산화막의 열화를 방지할 수 있는 것이다.In the present invention, the breakdown voltage of the junction diode is increased in order to increase the peri region leakage of the diode so that the breakdown of the diode occurs before the FN tunneling occurs, so that the breakdown voltage is lower than that of the conventional diode. Therefore, the charge focused on the gate through the diode before the FN tunneling flows to the substrate to prevent deterioration of the gate oxide film.
즉, 본 발명에서는 게이트를 다이오드에 연결하여 F-N 터널링이 발생하기 이전에 게이트에 모이는 차지(charge)를 다이오드를 통하여 기판으로 흐르게 한다.That is, in the present invention, the gate is connected to the diode so that a charge that collects in the gate flows to the substrate through the diode before F-N tunneling occurs.
만약, 소스/드레인 형성시 다이오드를 형성하게 되면 다이오드의 항복전압이 F-N 터널링이 일어나는 전압(대략 게이트산화막 항복전압의 1/2 수준임)보다 높기 때문에 역 바이어스가 걸리는 경우에 다이오드의 역할을 기대할 수 없게 되므로, 다이오드 형성시 다이오드의 항복전압을 낮추는 방법이 요구된다.If a diode is formed during source / drain formation, the diode's breakdown voltage is higher than the voltage at which FN tunneling occurs (approximately 1/2 of the gate oxide breakdown voltage). Therefore, a method of lowering the breakdown voltage of the diode when forming the diode is required.
현재, 0.18㎛급 MDL 소자제조공정에서 소자격리방법으로 STI(shallow trench isolation)을 사용하는 경우, 졍션 다이오드의 누설량은 다이오드 형성영역에 비하여 페리영역에서 101-102배정도 크게 나타난다. 따라서, 다이오드 형성시, 주변영역의 누설성분이 다이오드형성영역에서보다 커지도록 패터닝하면 졍션다이오드의 항복전압을 낮출 수 있다.Currently, 0.18㎛ class MDL device When using the STI (shallow trench isolation) in the manufacturing process as the device isolation method, the amount of leakage of the junction diode 10 is shown greatly 1-10 twice in Perry area than the diode forming region. Therefore, when the diode is formed, the breakdown voltage of the junction diode can be lowered by patterning the leakage component of the peripheral region to be larger than that of the diode forming region.
또한, 졍션 항복전압이 충분히 낮아지지 않으면 다이오드형성영역의 표면부위의 웰 농도를 증가시켜 페리영역의 누설량을 증가시키는 방법을 사용한다. 이때, 표면부위의 웰농도를 증가시키기 위해서는 다이오드형성영역을 개방시켜 문턱전압조절용 이온주입시의 에너지로 -1015ions/㎤의 도우즈로 이온주입을 실시한다. 이때, LDD(lightly doped drain) 형성용 도우즈 및 할로이온주입량에 따라 페리영역의 누설량이 변화할 수 있으므로 다이오드형성영역에 대한 이온주입은 LDD 및 할로이온주입조건에 따라 적절히 조절하여야 한다.In addition, when the junction breakdown voltage is not sufficiently lowered, a method of increasing the leakage concentration of the ferry region by increasing the well concentration of the surface portion of the diode forming region is used. At this time, in order to increase the well concentration of the surface portion, the diode formation region is opened, and ion implantation is carried out with a dose of -10 15 ions / cm 3 as energy at the time of ion implantation for threshold voltage regulation. At this time, since the amount of leakage of the ferry region may vary according to the dose of lightly doped drain (LDD) forming and the halo ion implantation, the ion implantation into the diode forming region should be appropriately adjusted according to the LDD and halo ion implantation conditions.
이하 본 발명에 대하여 첨부한 도면을 통하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 다이오드 형성영역과 소자활성영역이 도시된 반도체기판의 레이아웃이다.3 is a layout of a semiconductor substrate in which a diode forming region and a device active region are shown in accordance with the present invention.
도 3을 참조하면, 반도체기판인 실리콘 기판(30)에 소자격리막(34)인 필드산화막(34)에 의하여 게이트 형성부위인 소자활성영역(31)과 서로 이격된 다수개의 다이오드형성영역(32)이 정의되어 있다. 이때, 다이오드형성영역(32)은 STI(shallow trench isolation)에 의하여 소자격리막(34)을 형성하고 소정의 도전형을 갖는 웰을 형성한 다음 형성한 것이다. 본 발명의 실시예에서는, 페리영역 성분을 증가시키기 위하여 다수개의 다이오드를 빗장형태로 형성한다. 이때, 페리영역(33)의 항복전압이 충분히 낮지 않으면 다이오드형성영역에 문턱전압조절용 이온주입시의 에너지와 수 1012ions/㎤의 농도로 이온주입을 실시한다.Referring to FIG. 3, a plurality of diode forming regions 32 are spaced apart from the device active region 31, which is a gate forming portion, by a field oxide layer 34, which is a device isolation layer 34, on a silicon substrate 30, which is a semiconductor substrate. Is defined. In this case, the diode forming region 32 is formed by forming a device isolation film 34 by shallow trench isolation (STI) and forming a well having a predetermined conductivity type. In an embodiment of the present invention, a plurality of diodes are formed in the form of a latch in order to increase the ferry region component. At this time, if the breakdown voltage of the ferry region 33 is not low enough, ion implantation is performed at a concentration of 10 12 ions / cm 3 and energy at the time of ion implantation for threshold voltage regulation in the diode forming region.
따라서, 페리영역(33)의 웰농도를 높이므로 졍션다이오드의 항복전압을 낮춘다.Therefore, the well concentration of the ferry region 33 is increased, thereby lowering the breakdown voltage of the junction diode.
도 4는 본 발명에 따른 반도체장치의 게이트산화막 손상을 방지하기 위한 반도체장치의 레이아웃이고, 도 5는 본 발명에 따른 반도체장치의 게이트산화막 손상을 방지하기 위한 구조의 도 4의 절단선 Ⅱ-Ⅱ'에 따른 단면도이고, 도 6은 본 발명에 따른 반도체장치의 게이트산화막 손상을 방지하기 위한 구조의 도 4의 절단선 Ⅲ-Ⅲ'에 따른 단면도이다.4 is a layout of a semiconductor device for preventing gate oxide film damage of the semiconductor device according to the present invention, and FIG. 5 is a cut line II-II of FIG. 4 of a structure for preventing gate oxide film damage of the semiconductor device according to the present invention. 6 is a cross-sectional view taken along line III-III of FIG. 4 of a structure for preventing damage to a gate oxide film of a semiconductor device according to the present invention.
도 4 내지 도 6을 참조하면, 소자격리영역인 필드산화막(34)에 의하여 소자활성영역과 다이오드형성영역이 정의된 제 1 도전형 반도체 기판인 실리콘 기판(30)의 다이오드형성영역에 제 2 도전형 불순물로 도핑된 제 1 내지 제 4다이오드(320,321,322,323)가 소정의 간격으로 이격되어 도면상 수직방향으로 평행하게 배열되어 있다.4 to 6, a second conductivity is applied to the diode formation region of the silicon substrate 30, which is the first conductivity type semiconductor substrate in which the device active region and the diode formation region are defined by the field oxide film 34 as the device isolation region. The first to fourth diodes 320, 321, 322, and 323 doped with a type impurity are spaced at predetermined intervals and arranged in parallel in the vertical direction.
소자활성영역은 다이오드형성영역과 소정의 간격을 가지며 수평방향으로 이격되어 위치하고 게이트라인(35)과 중첩되지 않는 기판(30) 부위가 제 2 도전형 불순물로 도핑되어 트랜지스터 소자의 소스/드레인(40)을 형성한다.The device active region is spaced apart from the diode forming region and spaced apart in the horizontal direction, and the portion of the substrate 30 that is not overlapped with the gate line 35 is doped with a second conductivity type impurity so that the source / drain 40 of the transistor device is formed. ).
그리고,And,
제 1 내지 제 4 다이오드(320,321,322,323)의 상부에는 제 1 배선(390)이 중첩되도록 위치하며, 각각 제 1 내지 제 4 콘택플러그(380,381,382,383)를 통하여 제 1 배선(390)과 전기적으로 연결된다.The first wires 390 overlap the upper portions of the first to fourth diodes 320, 321, 322, and 323, and are electrically connected to the first wires 390 through the first to fourth contact plugs 380, 381, 382, and 383, respectively.
한편, 소자활성영역과 소자격리영역에 걸친 기판(30)상에는 게이트라인(35)이 길게 달리는 형태로 위치하며, 게이트라인(35)은 기판(30)과의 사이에 게이트절연막(36)을 개재하고 있다.On the other hand, the gate line 35 is disposed on the substrate 30 between the device active region and the device isolation region in a long running shape, and the gate line 35 is interposed between the substrate 30 and the gate insulating film 36. Doing.
게이트라인(35)의 일단과 제 1 금속배선(390)은 제 5 콘택플러그(384)를 통하여 전기적으로 연결된다. 그리고, 게이트라인(35)의 타단은 제 2 배선(391)과 제 6 콘택플러그(385)를 통하여 전기적으로 연결된다.One end of the gate line 35 and the first metal wire 390 are electrically connected to each other through the fifth contact plug 384. The other end of the gate line 35 is electrically connected to the second wire 391 through the sixth contact plug 385.
또한, 기판(30)과 제 1 내지 제 2 배선(390,391)사이에는 산화막 등으로 이루어진 층간절연층(37)이 개재되어 있다.In addition, an interlayer insulating layer 37 made of an oxide film or the like is interposed between the substrate 30 and the first to second wirings 390 and 391.
따라서, 트랜지스터의 게이트라인(35)과 제 1 내지 제 4 다이오드(320,321,322,323)는 제 1 배선(390)과 전기적으로 연결되어, 안테나 효과에 의하여 게이트라인(35)에 집속된 차지를 다이오드들(320,321,322,323)을 통하여기판(30) 벌크로 바이패스시킨다.Accordingly, the gate line 35 of the transistor and the first to fourth diodes 320, 321, 322, and 323 are electrically connected to the first wiring 390, so that the charges focused on the gate line 35 due to the antenna effect are occupied by the diodes 320, 321, 322, and 323. Bypass through the substrate 30 in bulk.
도 6에 도시된 바와 같이, 졍션다이오드인 제 1 내지 제 4 다이오드들(320,321,322,323)이 필드산화막(34)에 의하여 각각 격리되어 빗장형태로 배열되어 있으므로, 다이오드의 페리영역이 차지하는 영역이 다이오드형성영역에 비하여 커지므로 하나의 평판형태의 다이오드에 비하여 다이오드의 항복전압이 낮아진다.As shown in FIG. 6, since the first to fourth diodes 320, 321, 322, and 323, which are junction diodes, are separated from each other by the field oxide layer 34 and arranged in a latch shape, a region occupied by the ferry region of the diode is a diode forming region. Since it is larger than the diode, the breakdown voltage of the diode is lower than that of a single flat diode.
본 발명은 상술한 바와 같이, 게이트를 다이오드에 연결하므로 게이트의 차지-엎(charge-up)에 의하여 게이트산화막을 통한 F-N 터널링을 방지한다. 이때, 다이오드를 다수개의 빗장형태로 구성하여 페리영역의 비율을 높여 졍션다이오드의 항복전압을 낮추는 방법으로 게이트산화막의 열화를 방지하므로 소자의 게이트산화막에 미치는 영향이 최소화하여 문턱전압 및 동작전류의 안정성이 보장되며 소자의 신뢰성이 향상되는 장점이 있다.As described above, since the gate is connected to the diode, the present invention prevents F-N tunneling through the gate oxide layer by charge-up of the gate. At this time, the diode is composed of a plurality of bars to increase the ratio of the ferry region to lower the breakdown voltage of the junction diode, thereby preventing the gate oxide from deteriorating, thereby minimizing the effect on the gate oxide of the device, thereby reducing the threshold voltage and operating current stability. This is guaranteed and the reliability of the device is improved.
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| KR102065242B1 (en) * | 2018-04-17 | 2020-01-13 | 한국과학기술원 | The local thermal annealing method for curing of gate oxide damage utilizing punchthrough current in mosfet |
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| US7439590B2 (en) | 2005-12-30 | 2008-10-21 | Hynix Semiconductor Inc. | Semiconductor device |
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