KR20020013142A - Method for Forming Metal Line of Semiconductor Device - Google Patents

Method for Forming Metal Line of Semiconductor Device Download PDF

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Publication number
KR20020013142A
KR20020013142A KR1020000046593A KR20000046593A KR20020013142A KR 20020013142 A KR20020013142 A KR 20020013142A KR 1020000046593 A KR1020000046593 A KR 1020000046593A KR 20000046593 A KR20000046593 A KR 20000046593A KR 20020013142 A KR20020013142 A KR 20020013142A
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KR
South Korea
Prior art keywords
metal
trench
semiconductor substrate
layer
via hole
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KR1020000046593A
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Korean (ko)
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이병주
심규철
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000046593A priority Critical patent/KR20020013142A/en
Publication of KR20020013142A publication Critical patent/KR20020013142A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to improve a barrier characteristic by performing an electron beam treatment in a nitrogen atmosphere regarding a tantalum layer so that a tantalum nitride layer of a uniform thickness is formed, and to improve reliability by preventing a defect like a void or key hole in the metal interconnection. CONSTITUTION: The first insulation layer and the second insulation layer are stacked on a semiconductor substrate(41) having a lower interconnection(42) and a predetermined circuit pattern. The second insulation layer and the first insulation layer formed on the lower interconnection are removed by a predetermined depth to form a trench. A partial region of the first insulation layer under the trench is eliminated to expose the lower interconnection so that a via hole is formed. An adhesion layer(46) is deposited on the semiconductor substrate having the via hole and the trench. An electron beam treatment is performed in an atmosphere of nitrogen gas to nitridize the surface of the adhesion so that a barrier metal layer(47) is formed. Metal is deposited on the semiconductor substrate including the via hole and the trench. The metal is selectively removed to be left only in the via hole and the trench so that the metal interconnection is formed. A capping layer(49) is formed on the semiconductor substrate.

Description

반도체 소자의 금속 배선 형성방법{Method for Forming Metal Line of Semiconductor Device}Method for Forming Metal Line of Semiconductor Device {Method for Forming Metal Line of Semiconductor Device}

본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 베리어 금속층의 스텝 커버리지(Step Coverage) 및 베리어(Barrier) 특성을 향상시키는데 적합한 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wirings in a semiconductor device suitable for improving step coverage and barrier characteristics of a barrier metal layer.

최근, 반도체 소자가 고집적화됨에 따라서 비아 크기가 감소되고 종횡비(Aspect ratio)가 증가됨에 따라서 점점 열악해지는 접착층과 베리어 금속층의 단차 도포성 즉, 스텝 커버리지를 향상시키고자하는 방안이 연구 개발중이다.Recently, research is being conducted to improve step coverage, that is, step coverage, of an adhesive layer and a barrier metal layer, which are gradually worsened as a via size is reduced and an aspect ratio is increased as a semiconductor device is highly integrated.

현재, 베리어 금속층의 스퍼터링 증착의 경우 컬럼에이터(Collimator)를 사용하여 박막의 스텝 커버리지를 향상시키거나 IMP(Ionized Metal Plasma) 방법에 의한 증착법이 널리 사용되고 있으며 간혹, 화학기상증착(Chemical Mechanical Polishing : CMP) 방법에 의하여 금속을 증착하기도 한다.Currently, in sputtering deposition of barrier metal layers, the step coverage of the thin film is improved by using a collimator, or the deposition method by an ionized metal plasma (IMP) method is widely used. The metal may be deposited by the method.

이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 배선 형성방법을 설명하면 다음과 같다.Hereinafter, a wiring forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1은 종래의 이중-상감 기술에 따른 반도체 소자의 배선 형성 플로우 차트이고, 도 2a 내지 도 2c는 종래의 이중-상감 기술에 따른 반도체 소자의 배선 형성방법을 설명하기 위한 단면도이다.FIG. 1 is a flow chart of a semiconductor device according to a conventional double- damascene technique, and FIGS. 2A to 2C are cross-sectional views illustrating a method of forming a wire of a semiconductor device according to a conventional double- damascene technique.

도 2a에 도시된 바와 같이, 하부 배선(22) 및 소정의 회로 패턴들(도시하지 않음)이 형성되어 있는 반도체 기판(21)상에 제 1 층간 절연막(23a)을 형성하고, 상기 제 1 층간 절연막(23a)상에 절연물질, 예컨대 산화막을 증착하여 제 2 층간 절연막(23b)을 형성한다(도 1의 1a).As shown in FIG. 2A, a first interlayer insulating film 23a is formed on the semiconductor substrate 21 on which the lower wiring 22 and predetermined circuit patterns (not shown) are formed, and the first interlayer is formed. An insulating material, for example, an oxide film, is deposited on the insulating film 23a to form a second interlayer insulating film 23b (1 a in FIG. 1).

그리고, 금속배선을 형성하기 위하여 포토 및 식각 공정으로 상기 하부배선(22) 상부의 상기 제 2 층간 절연막(23b)과 제 1 층간 절연막(23a)을 소정깊이로 제거하여 트렌치(24)를 형성한다.In order to form a metal wiring, the trench 24 is formed by removing the second interlayer insulating film 23b and the first interlayer insulating film 23a on the lower wiring 22 to a predetermined depth by a photo and etching process. .

이후, 상기 반도체 기판(21)의 전면에 포토레지스트(도시하지 않음)를 도포하고 노광 및 현상 공정으로 상기 트렌치(24) 하부의 상기 제 1 층간 절연막(23a)의 일영역이 노출되도록 상기 포토레지스트를 패터닝한다.Thereafter, a photoresist (not shown) is coated on the entire surface of the semiconductor substrate 21, and the photoresist is exposed to expose one region of the first interlayer insulating layer 23a under the trench 24 by an exposure and development process. Pattern.

그리고, 상기 패터닝된 포토레지스트를 식각 마스크로 이용하여 상기 하부 배선(22)이 노출되도록 상기 제 1 층간 절연막(23a)을 제거하여 비아홀(25)을 형성하고, 상기 포토레지스트를 제거한다(도 1의 1b).Then, using the patterned photoresist as an etching mask, the first interlayer insulating layer 23a is removed to expose the lower wiring 22 to form a via hole 25, and the photoresist is removed (FIG. 1). 1b).

이어, 상기 비아홀(25) 및 트렌치(24)가 형성된 반도체 기판(21)을 세정한다(도 1의 1c).Subsequently, the semiconductor substrate 21 on which the via holes 25 and the trenches 24 are formed is cleaned (1c in FIG. 1).

그리고, 도 2b에 도시된 바와 같이 상기 트렌치(24) 및 비아홀(25)을 포함한 반도체 기판(21)의 전면에 접착층(26)과 베리어 금속층(27)을 적층하여 형성한다(도 1의 1d, 1e).As shown in FIG. 2B, the adhesive layer 26 and the barrier metal layer 27 are stacked on the entire surface of the semiconductor substrate 21 including the trench 24 and the via hole 25 (1D of FIG. 1). 1e).

이때, 상기 접착층(26)은 탄탈륨(Ta)을 스퍼터링(Sputtering) 방법으로 증착하고. 베리어 금속층(27)은 질화 탄탈륨(TaN)을 스퍼터링(Sputtering) 방법으로 증착하여 형성한다.At this time, the adhesive layer 26 is deposited by the sputtering method (Ta). The barrier metal layer 27 is formed by depositing tantalum nitride (TaN) by a sputtering method.

또한, 상기 증착 공정에서 스퍼터링 방법이외에 IMP(Ionized Metal Plasma) 또는 화학기상증착(Chemical Vapor Deposition : 이하 'CVD'라고 한다) 방법 등을 이용하여도 무방하다.In addition, in the deposition process, in addition to the sputtering method, an ionized metal plasma (IMP) or chemical vapor deposition (Chemical Vapor Deposition) method may be used.

그리고, 상기 바이홀(25)의 크기가 작고 종횡비(Aspect ratio)가 클 경우에는 상기 베리어 금속층(27)의 스텝 커버리지(Step coverage)가 좋지 않게 된다.When the size of the bi-hole 25 is small and the aspect ratio is large, the step coverage of the barrier metal layer 27 is not good.

즉, 비아홀(25)의 바닥 및 구석 부위에는 상기 질화 탄탈륨(TaN)의 증착이 잘 되지 않게 되며, 그로 인하여 베리어(Barrier) 특성도 저하된다.That is, the deposition of the tantalum nitride (TaN) is difficult to be deposited on the bottom and corners of the via hole 25, thereby deteriorating barrier characteristics.

이어, 도 2c에 도시된 바와 같이 스퍼터링이나 CVD 방법으로 상기 비아홀(25) 및 트렌치(24)를 포함한 반도체 기판(21)의 전면에 구리(Cu)를 증착한다(도 1의 1f).Subsequently, as illustrated in FIG. 2C, copper (Cu) is deposited on the entire surface of the semiconductor substrate 21 including the via hole 25 and the trench 24 by sputtering or CVD (FIG. 1F).

이때, 상기 베리어 금속층(27)의 스텝 커버리지 불량으로 인하여 상기 비아홀(25) 및 트렌치(24)내부에 매립되는 구리에 보이드(Void) 내지 키홀(Key hole)이 발생되게 된다.At this time, voids or key holes are generated in the copper embedded in the via hole 25 and the trench 24 due to the poor step coverage of the barrier metal layer 27.

그리고, 화학적 기계적 연마(Chemical Mechanical Polishing : 이하 'CMP' 라고 한다) 공정 혹은 에치백(Etch-back)공정으로 상기 제 2 층간 절연막(23b)이 노출되도록 상기 구리와 베리어 금속층(27)과 접착층(26)을 제거하여 상기 비아홀(25) 및 트렌치(24)의 내부에만 구리를 잔류시키어 구리배선(28)을 형성한다(도 1의 1g).In addition, the copper and barrier metal layer 27 and the adhesive layer may be exposed to the second interlayer insulating layer 23b by a chemical mechanical polishing (CMP) process or an etch-back process. 26 is removed to leave copper only in the via hole 25 and the trench 24 to form a copper wiring 28 (1g in FIG. 1).

이어, 상기 구리배선(28)의 구리 원자가 상기 제 1 , 제 2 층간 절연막(23a, 23b)으로 확산하는 것을 방지하기 위하여 상기 반도체 기판(21)의 전면에 실리콘질화막(SiN)을 증착하여 캡핑층(29)을 형성하므로써 종래의 반도체 소자의 배선을 완성한다(도 1의 1h).Subsequently, in order to prevent the copper atoms of the copper wiring 28 from diffusing into the first and second interlayer insulating films 23a and 23b, a silicon nitride film SiN is deposited on the entire surface of the semiconductor substrate 21 to form a capping layer. The wiring of the conventional semiconductor element is completed by forming (29) (1H in Fig. 1).

그러나, 상기와 같은 종래의 반도체 소자의 금속 배선 형성방법은 다음과 같은 문제점이 있다.However, the metal wiring formation method of the conventional semiconductor device as described above has the following problems.

첫째, 베리어 금속층을 증착하여 형성하므로 단차 도포성 즉, 스텝 커버리지가 좋지 않음으로 인하여 구리의 매립이 불량해져 구리 배선 내부에 보이드 내지 키홀이 발생된다.First, since the barrier metal layer is formed by depositing, because the step coverage, that is, the step coverage is poor, the embedding of the copper is poor and voids or keyholes are generated in the copper wiring.

둘째, 베리어 금속층의 스텝 커버지지가 좋지 않으므로 베리어 금속층의 베리어 특성이 열화되어 배선의 비저항이 증가되고 배선 연결이 단락된다.Second, since the step cover support of the barrier metal layer is poor, the barrier property of the barrier metal layer is deteriorated, so that the resistivity of the wiring is increased and the wiring connection is shorted.

셋째, 배선의 비저항의 증가로 인하여 RC 지연시간이 증가되어 소자의 동작 속도가 저하되고, 소자의 신뢰성이 저하된다.Third, the RC delay time is increased due to an increase in the resistivity of the wiring, thereby reducing the operation speed of the device and reducing the reliability of the device.

넷째, 불량한 베리어 금속층을 통하여 구리 원자가 층간 절연막으로 확산되어 소자의 누설 전류가 증가된다.Fourth, copper atoms diffuse into the interlayer insulating film through the poor barrier metal layer, thereby increasing the leakage current of the device.

다섯째, 베리어 금속층을 증착하여 형성하기 때문에 집적도가 증가되면 단차 도포성 및 베리어 특성이 더욱더 열화되므로 소자의 집적도가 저하된다.Fifth, since the barrier metal layer is formed by depositing, the degree of integration increases, and thus the degree of integration of the device is lowered because the step coverage and barrier properties are further deteriorated.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 고집적 소자의 특성 및 신뢰성을 향상시키는데 적합한 반도체 소자의 금속 배선 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method for forming a metal wiring of a semiconductor device suitable for improving the characteristics and reliability of the highly integrated device.

도 1은 종래 기술에 따른 반도체 소자의 금속 배선 형성 플로우 차트1 is a flow chart forming a metal wiring of a semiconductor device according to the prior art

도 2a 내지 도 2c는 종래의 반도체 소자의 금속 배선 형성 공정을 설명하기 위한 단면도2A to 2C are cross-sectional views illustrating a metal wiring forming process of a conventional semiconductor device.

도 3은 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 플로우 차트3 is a metal wiring formation flowchart of a semiconductor device according to an embodiment of the present invention.

도 4a 내지 도 4d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 공정을 설명하기 위한 단면도4A through 4D are cross-sectional views illustrating a metal wiring forming process of a semiconductor device in accordance with an embodiment of the present invention.

도면의 주요 부분에 대한 부호설명Explanation of Signs of Major Parts of Drawings

41 : 반도체 기판 42 : 하부 배선41 semiconductor substrate 42 lower wiring

43a : 제 1 층간 절연막 43b : 제 2 층간 절연막43a: first interlayer insulating film 43b: second interlayer insulating film

44 : 트렌치 45 : 비아홀44: trench 45: via hole

46 : 접착층 47 : 베리어 금속층46: adhesive layer 47: barrier metal layer

48 : 구리배선 49 : 캡핑층48: copper wiring 49: capping layer

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성방법은 하부 배선 및 소정의 회로 패턴이 형성된 반도체 기판상에 제 1 절연막과 제 2 절연막을 적층 형성하는 단계와, 상기 하부 배선 상부에 형성된 상기 제 2 절연막과 제 1 절연막을 소정 깊이로 제거하여 트렌치를 형성하는 단계와, 상기 하부배선이 노출되도록 상기 트렌치 하부의 상기 제 1 절연막의 일영역을 제거하여 비아홀을 형성하는 단계와, 상기 비아홀 및 트렌치가 형성된 상기 반도체 기판의 전면에 접착층을 증착하는 단계와, 질화가스 분위기에서 전자빔 처리하여 상기 접착층의 표면을 질화시키어 베리어 금속층을 형성하는 단계와, 상기 비아홀 및 트렌치를 포함한 반도체 기판의 전면에 금속을 증착하고, 상기 비아홀 및 트렌치 내부에만 남도록 이를 선택적으로 제거하여 금속 배선을 형성하는 단계와, 상기 반도체 기판의 전면에 캡핑막을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The metal wiring forming method of the semiconductor device of the present invention for achieving the above object comprises the steps of forming a first insulating film and a second insulating film on the semiconductor substrate on which the lower wiring and the predetermined circuit pattern is formed; Forming a trench by removing the second insulating film and the first insulating film formed at a predetermined depth, forming a via hole by removing a region of the first insulating film under the trench so that the lower wiring is exposed; Depositing an adhesive layer on an entire surface of the semiconductor substrate on which the via holes and trenches are formed, forming a barrier metal layer by nitriding the surface of the adhesive layer by electron beam treatment in a nitride gas atmosphere, and forming a barrier metal layer in the semiconductor substrate including the via holes and trenches. Deposits metal on the front surface and optionally so that it remains only inside the via holes and trenches And removing the metal wires to form metal wires, and forming a capping film on the entire surface of the semiconductor substrate.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하면 다음과 같다.Hereinafter, a metal wire forming method of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

도 3은 본 발명의 실시예에 따른 반도체 소자의 배선 형성 플로우 차트이고, 도 4a 내지 도 4d는 본 발명의 실시예에 따른 이중-상감 구조의 반도체 소자의 배선 형성 공정을 설명하기 위한 단면도이다.FIG. 3 is a flow chart of forming a wiring of a semiconductor device according to an exemplary embodiment of the present invention, and FIGS. 4A to 4D are cross-sectional views illustrating a wiring forming process of a semiconductor device having a double damascene structure according to an embodiment of the present invention.

도 4a에 도시된 바와 같이, 하부 배선(42) 및 소정의 회로 패턴들(도시하지 않음)이 형성되어 있는 반도체 기판(41)상에 제 1 층간 절연막(43a)을 형성하고, 상기 제 1 층간 절연막(43a)상에 절연물질, 예컨대 실리콘 산화막(SiO2) 내지 FSG(SiOF)를 증착하여 제 2 층간 절연막(43b)을 형성한다(도 3의 3a).As shown in FIG. 4A, a first interlayer insulating film 43a is formed on the semiconductor substrate 41 on which the lower wiring 42 and predetermined circuit patterns (not shown) are formed, and the first interlayer is formed. An insulating material, for example, silicon oxide film (SiO 2 ) to FSG (SiOF), is deposited on the insulating film 43a to form a second interlayer insulating film 43b (FIG. 3A).

그리고, 금속배선을 형성하기 위하여 포토 및 식각 공정으로 상기 하부 배선(42) 상부의 상기 제 2 층간 절연막(43b)과 제 1 층간 절연막(43a)을 소정깊이로 제거하여 트렌치(44)를 형성한다.Then, the trench 44 is formed by removing the second interlayer insulating film 43b and the first interlayer insulating film 43a above the lower wiring 42 to a predetermined depth in order to form a metal wiring by a photo and etching process. .

이후, 상기 반도체 기판(41)의 전면에 포토레지스트(도시하지 않음)를 도포하고 노광 및 현상 공정으로 상기 트렌치(44) 하부의 상기 제 1 층간 절연막(43a)의 일영역이 노출되도록 상기 포토레지스트를 패터닝한다.Thereafter, a photoresist (not shown) is coated on the entire surface of the semiconductor substrate 41, and the photoresist is exposed to expose one region of the first interlayer insulating layer 43a below the trench 44 by an exposure and development process. Pattern.

그리고, 상기 패터닝된 포토레지스트를 식각 마스크로 이용하여 상기 하부 배선(42)이 노출되도록 상기 제 1 층간 절연막(43a)을 제거하여 비아홀(45)을 형성하고, 상기 포토레지스트를 제거한다(도 1의 1b).Then, using the patterned photoresist as an etching mask, the first interlayer insulating layer 43a is removed to expose the lower interconnection 42 to form a via hole 45, and the photoresist is removed (FIG. 1). 1b).

이어, 세정 공정으로 비아홀(45) 및 트렌치(44)가 형성된 반도체 기판(41)을 세정한 후, 300∼400℃에서 약 100초 이내로 유지시키어 탈가스(Degas)시킨다(도 3의 3c).Subsequently, the semiconductor substrate 41 on which the via holes 45 and the trench 44 are formed is cleaned by a cleaning process, and then maintained at 300 to 400 ° C. for about 100 seconds to degas (FIG. 3C).

상기 세정 공정은 NF3세정, 습식(Wet) 세정, RF 식각(etch) 세정 등의 방법을 이용하여 실시한다.The cleaning process is performed using a method such as NF 3 cleaning, wet cleaning, RF etch cleaning, or the like.

그리고, 도 4b에 도시된 바와 같이 스퍼터링 방법에 의하여 300∼1000Å의 두께로 탄탈륨을 증착하여 접착층(46)을 형성한다(도 3의 3d).As shown in Fig. 4B, tantalum is deposited to a thickness of 300 to 1000 mm by the sputtering method to form an adhesive layer 46 (3d in Fig. 3).

이때, 상기 비아홀(45)의 종횡비(Aspect ratio)가 큰 경우에는 상기 탄탈륨의 스퍼터링 증착시에 스텝 커버리지를 향상시킬 수 있는 칼럼에이트(Collimated) 방식 또는 이온화 물리 증착(Ionized PVD(Physical Vapor Disposition)) 방식을 이용한다.In this case, when the aspect ratio of the via hole 45 is large, a column-lime method or ionized physical vapor deposition (PVD), which may improve step coverage during sputter deposition of tantalum, may be used. Use the method.

그리고, 4c에 도시된 바와 같이 질소(N2) 가스 분위기에서 전자빔(Electron Beam) 처리 공정을 실시하여 상기 탄탈륨(Ta)으로 구성된 접착층(46)의 표면을 질화시키어 균일한 두께를 갖는 베리어 금속층(47)을 형성한다.(도 3의 3e)As shown in 4c, a barrier metal layer having a uniform thickness is formed by nitriding the surface of the adhesive layer 46 formed of tantalum (Ta) by performing an electron beam treatment process in a nitrogen (N 2 ) gas atmosphere. 47) (3e in FIG. 3).

이때, 상기 베리어 금속층(47)의 구성 물질은 질화 탄탈륨(TaN)이고, 상기 전자빔의 처리 온도는 300∼400℃이며, 질소(N2)의 플로우량은 50∼200sccm이고, 처리 시간은 10분 이내로 한다.At this time, the constituent material of the barrier metal layer 47 is tantalum nitride (TaN), the processing temperature of the electron beam is 300 ~ 400 ℃, the flow amount of nitrogen (N 2 ) is 50 ~ 200sccm, the processing time is 10 minutes Within

여기에서 상기 전자빔 처리 온도는 300∼400℃ 정도로 일반 공정의 진행온도와 비슷한 수준이므로, 상기 반도체 기판(41)에 써멀 스트레스(Thermal Stress)에 의한 열충격이 유발되지 않는다.Here, the electron beam treatment temperature is about 300 to 400 ° C., which is similar to the progress temperature of a general process, and thus thermal shock due to thermal stress does not occur on the semiconductor substrate 41.

그리고, 상기 베리어 금속층(47)은 질화 탄탈륨을 증착하여 형성하지 않고, 탄탈륨(Ta)을 증착한 후에 그 상부표면을 질화시키어 질화 탄탈륨(TaN)을 형성하므로써 균일한 두께의 베리어 금속층(47)을 얻을 수 있었다.In addition, the barrier metal layer 47 is formed by depositing tantalum (Ta) instead of depositing tantalum nitride, and forming a tantalum nitride (TaN) by nitriding the upper surface thereof to form a barrier metal layer 47 having a uniform thickness. Could get

그리고, 도 4d에 도시된 바와 같이 상기 비아홀(45) 및 트렌치(44)를 포함한 반도체 기판(41)의 전면에 구리(Cu)를 증착한다(도 3의 3f).As shown in FIG. 4D, copper (Cu) is deposited on the entire surface of the semiconductor substrate 41 including the via hole 45 and the trench 44 (3f in FIG. 3).

상기 구리는 무전해도금, 전해도금, 스퍼터링, CVD 방법 등을 이용하여 증착할 수 있으나, 매립 특성이 우수한 전해도금이나 CVD 방법을 사용하여 증착하는 것이 바람직하다.The copper may be deposited using electroless plating, electroplating, sputtering, CVD, or the like, but is preferably deposited using electroplating or CVD with excellent buried characteristics.

그리고, CMP 혹은 전해 폴리싱 공정으로 상기 제 2 층간 절연막(43b)이 노출되도록 상기 구리와 베리어 금속층(47) 및 접착층(46)을 제거하여 상기 비아홀(45) 및 트렌치(44)의 내부에만 구리를 잔류시키어 구리배선(48)을 형성한다(도 3의 3g).In addition, the copper and the barrier metal layer 47 and the adhesive layer 46 are removed to expose the second interlayer insulating layer 43b by a CMP or electrolytic polishing process so that only copper is formed inside the via hole 45 and the trench 44. It is left to form copper wiring 48 (3g of FIG. 3).

이어, 구리배선(48)의 구리 원자가 상기 제 1, 제 2 층간 절연막(43a, 43b)으로 확산하는 것을 방지하기 위하여 상기 반도체 기판(41)의 전면에 실리콘질화막(SiN)을 증착하여 캡핑층(49)을 형성하므로써 종래의 반도체 소자의 금속 배선을 완성한다(도 3의 3h).Subsequently, in order to prevent the copper atoms of the copper wiring 48 from diffusing into the first and second interlayer insulating layers 43a and 43b, a silicon nitride film SiN is deposited on the entire surface of the semiconductor substrate 41 to form a capping layer ( 49), the metal wiring of the conventional semiconductor element is completed (3h in FIG. 3).

상기와 같은 본 발명의 반도체 소자의 금속 배선 형성방법은 다음과 같은 효과가 있다.The metal wiring forming method of the semiconductor device of the present invention as described above has the following effects.

첫째, 탄탈륨막을 증착한 후에 질소 분위기에서 전자빔 처리하여 균일한 두께의 질화 탄탈륨막을 얻을 수 있으므로 베리어 특성을 향상시킬 수 있다.First, since a tantalum nitride film having a uniform thickness can be obtained by electron beam treatment in a nitrogen atmosphere after the deposition of the tantalum film, the barrier property can be improved.

둘째, 베리어 금속막의 커버리지 특성이 우수하여 배선 금속에 보이드나 키홀과 같은 불량이 발생되지 않으므로 반도체 소자의 신뢰성을 향상시킬 수 있다.Second, since the barrier metal film has excellent coverage characteristics, defects such as voids and keyholes do not occur in the wiring metal, thereby improving reliability of the semiconductor device.

셋째, 비아홀 및 트렌치의 크기가 감소하고 종횡비가 증가하는 경우에도 균일한 두께의 질화 탄탈륨막을 형성할 수 있으므로 고집적 반도체 소자에 적용할 수 있다.Third, even when the size of the via hole and the trench is reduced and the aspect ratio is increased, the tantalum nitride film having a uniform thickness can be formed and thus can be applied to a highly integrated semiconductor device.

넷째, 배선 금속 물질로 저항이 낮은 구리를 사용하고, 베리어 특성을 향상시키어 배선 금속의 저항을 낮출 수 있으므로 반도체 소자의 성능 및 신뢰성을 향상시킬 수 있다.Fourth, since copper having low resistance is used as the wiring metal material and barrier properties are improved, the resistance of the wiring metal can be lowered, thereby improving performance and reliability of the semiconductor device.

Claims (4)

하부 배선 및 소정의 회로 패턴이 형성된 반도체 기판상에 제 1 절연막과 제 2 절연막을 적층 형성하는 단계;Stacking a first insulating film and a second insulating film on a semiconductor substrate on which lower wirings and predetermined circuit patterns are formed; 상기 하부 배선 상부에 형성된 상기 제 2 절연막과 제 1 절연막을 소정 깊이로 제거하여 트렌치를 형성하는 단계;Forming a trench by removing the second insulating film and the first insulating film formed on the lower wiring to a predetermined depth; 상기 하부 배선이 노출되도록 상기 트렌치 하부의 상기 제 1 절연막의 일영역을 제거하여 비아홀을 형성하는 단계;Forming a via hole by removing a region of the first insulating layer under the trench to expose the lower wiring; 상기 비아홀 및 트렌치가 형성된 상기 반도체 기판의 전면에 접착층을 증착하는 단계;Depositing an adhesive layer on an entire surface of the semiconductor substrate on which the via holes and trenches are formed; 질화가스 분위기에서 전자빔 처리하여 상기 접착층의 표면을 질화시키어 베리어 금속층을 형성하는 단계;Electron beam treatment in a nitride gas atmosphere to nitride the surface of the adhesive layer to form a barrier metal layer; 상기 비아홀 및 트렌치를 포함한 반도체 기판의 전면에 금속을 증착하고, 상기 비아홀 및 트렌치 내부에만 남도록 이를 선택적으로 제거하여 금속 배선을 형성하는 단계;Depositing a metal on an entire surface of the semiconductor substrate including the via hole and the trench, and selectively removing the metal to remain only in the via hole and the trench to form a metal wiring; 상기 반도체 기판의 전면에 캡핑막을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 금속 배선 형성방법.And forming a capping film over the entire surface of the semiconductor substrate. 제 1항에 있어서, 베리어 금속층은 50∼200sccm의 유량의 질소가스 분위기에서 300∼400℃의 전자빔을 10분 이내로 처리하여 형성함을 특징으로 하는 반도체소자의 금속 배선 형성방법.The method of claim 1, wherein the barrier metal layer is formed by treating an electron beam at 300 to 400 ° C. within 10 minutes in a nitrogen gas atmosphere at a flow rate of 50 to 200 sccm. 제 1항에 있어서, 상기 접착층은 스퍼터링 방법으로 300∼1000Å의 탄탈륨막을 증착하여 형성함을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the adhesive layer is formed by depositing a tantalum film of 300 to 1000 GPa by a sputtering method. 제 1항에 있어서, 상기 금속인 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of forming a metal wiring of a semiconductor device according to claim 1, wherein the metal is a metal.
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