KR20020010773A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20020010773A KR20020010773A KR1020000044238A KR20000044238A KR20020010773A KR 20020010773 A KR20020010773 A KR 20020010773A KR 1020000044238 A KR1020000044238 A KR 1020000044238A KR 20000044238 A KR20000044238 A KR 20000044238A KR 20020010773 A KR20020010773 A KR 20020010773A
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- Prior art keywords
- source
- gate electrode
- drain
- forming
- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 25
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- XUIMIQQOPSSXEZ-OUBTZVSYSA-N silicon-29 atom Chemical compound [29Si] XUIMIQQOPSSXEZ-OUBTZVSYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66515—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned selective metal deposition simultaneously on the gate and on source or drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 듀얼 게이트전극(Dual-gate electrode)의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a dual-gate electrode.
일반적으로 CMOS SRAM 셀에서 게이트길이(Gate length)가 스케일다운(Scale down)시 현재의 단일 폴리실리콘게이트(Single Polysilicon gate)가 매몰채널 (Buried channel)이므로 숏채널(Short channel)로 인한 누설(Leakage)을 방지할 수 없다. 그러므로 N/P형 표면채널 즉, 듀얼 게이트로 전환하여야 하나, 상호 확산 (Inter diffusion)이 발생하여 티타늄/코발트(Ti/Co)의 실리사이드 (Silicide)나 메탈게이트(Metal gate)를 사용하게 된다.In general, when a gate length is scaled down in a CMOS SRAM cell, the current leakage rate due to a short channel is reduced because a single polysilicon gate is a buried channel. ) Can not be prevented. Therefore, the N / P type surface channel, that is, the dual gate should be switched, but interdiffusion occurs, so that a silicide or a metal gate of titanium / cobalt (Ti / Co) is used.
도 1은 종래기술에 따른 티타늄실리사이드를 적용한 게이트전극의 형성 방법을 도시한 도면으로서, 반도체기판(11)상에 게이트산화막(12), 게이트전극(13)용 폴리실리콘을 형성한 다음, 상기 폴리실리콘, 게이트산화막(12)을 선택적으로 패터닝하여 게이트전극(13)을 형성한다.1 is a view illustrating a method of forming a gate electrode using titanium silicide according to the related art, in which a polysilicon for a gate oxide film 12 and a gate electrode 13 is formed on a semiconductor substrate 11, and then the poly The gate electrode 13 is formed by selectively patterning the silicon and gate oxide film 12.
이어 상기 게이트전극(13)을 마스크로 이용한 저농도 불순물 이온주입으로 LDD영역(14)을 형성하고, 전면에 측벽용 절연막을 형성한 후 전면식각하여 상기 게이트전극(13)의 양측벽에 접하는 스페이서(15)를 형성한다.Subsequently, the LDD region 14 is formed by the implantation of low concentration impurity ions using the gate electrode 13 as a mask, the insulating layer for sidewalls is formed on the front side, and the surface is etched to contact the both side walls of the gate electrode 13. 15).
이어 상기 게이트전극(13) 및 스페이서(15)를 마스크로 이용한 고농도 불순물 이온주입으로 소스/드레인(16)을 형성한 후, 전면에 티타늄을 증착하고 열처리하여 상기 게이트전극(13)의 상면과 소스/드레인(16)의 표면에 티타늄실리사이드 (Ti-silicide)(17)를 형성한다.Subsequently, the source / drain 16 is formed by the implantation of high concentration impurity ions using the gate electrode 13 and the spacer 15 as a mask, and then titanium is deposited on the entire surface of the gate electrode 13 to heat the source and the source. Titanium silicide 17 is formed on the surface of the drain 16.
상기와 같은 티타늄실리사이드의 경우, 티타늄실리사이드 결합이 충분히 이루어지지 않아 불균일한 실리사이드를 얻게되어 FNWE(Fine Narrow Width Effect)와트랜지스터의 배리에이션(Variation)을 갖게 되는 문제점이 있다.In the case of the titanium silicide as described above, there is a problem that the titanium silicide bond is not sufficiently made to obtain a non-uniform silicide to have a variation of the FNWE (Fine Narrow Width Effect) and the transistor (Variation).
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 게이트전극의 모서리와 중심부분의 티타늄실리사이드가 불균일하게 형성되는 것을 방지하는데 적합한 반도체소자의 제조 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method of manufacturing a semiconductor device suitable for preventing the non-uniform formation of titanium silicide at the edge and the center portion of the gate electrode.
도 1은 종래기술에 따른 반도체소자의 제조 방법을 도시한 도면,1 is a view showing a method of manufacturing a semiconductor device according to the prior art;
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체소자의 제조 방법을 도시한 도면.2A to 2E illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 산화막21 semiconductor substrate 22 oxide film
23 : 감광막 24 : 저농도 소스/드레인23: photosensitive film 24: low concentration source / drain
25 : 질화막스페이서 26 : 고농도 소스/드레인25: nitride spacer 26: high concentration source / drain
27a : 소스/드레인 패드 28 : 게이트산화막27a: source / drain pad 28: gate oxide film
29 : 게이트전극 30 : 티타늄실리사이드29 gate electrode 30 titanium silicide
상기의 목적을 달성하기 위한 본 발명의 반도체소자의 제조 방법은 반도체기판상에 산화막을 형성하는 제 1 단계; 상기 산화막을 선택적으로 제거하여 후속 소스/드레인이 형성될 반도체기판을 노출시키는 제 2 단계; 상기 노출된 반도체기판에 불순물이온주입을 실시하여 소스/드레인을 형성하는 제 3 단계; 상기 소스/드레인이 접속되는 소스/드레인패드를 형성하는 제 4 단계; 상기 산화막을 선택적으로 제거하여 후속 게이트전극이 형성될 상기 반도체기판의 소정부분을 노출시키는 제 5 단계; 상기 제 5 단계의 결과물상에 게이트산화막, 게이트전극용 폴리실리콘을 형성하는 제 6 단계; 상기 게이트전극용 폴리실리콘을 선택적으로 제거하여 상면과 측면이 노출되는 게이트전극을 형성함과 동시에 상기 소스/드레인패드를 노출시키는 제 7 단계; 및 상기 게이트전극 및 소스/드레인패드의 표면에 실리사이드막을 형성하는 제 8 단계를 포함하여 이루어짐을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object comprises a first step of forming an oxide film on a semiconductor substrate; Selectively removing the oxide film to expose a semiconductor substrate on which a subsequent source / drain is to be formed; A third step of forming a source / drain by implanting impurity ions into the exposed semiconductor substrate; A fourth step of forming a source / drain pad to which the source / drain is connected; Selectively removing the oxide film to expose a predetermined portion of the semiconductor substrate on which a subsequent gate electrode is to be formed; A sixth step of forming a gate oxide film and a polysilicon for the gate electrode on the resultant of the fifth step; Selectively removing the polysilicon for the gate electrode to form a gate electrode exposing top and side surfaces thereof and simultaneously exposing the source / drain pad; And an eighth step of forming a silicide film on the surfaces of the gate electrode and the source / drain pad.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .
도 2a 내지 도 2e는 본 발명의 실시예에 따른 듀얼 게이트전극의 형성 방법을 도시한 도면이다.2A to 2E illustrate a method of forming a dual gate electrode according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 웰(도시 생략) 및 문턱전압 이온주입 공정까지 완료된 반도체기판(21)상에 산화막(22)을 형성하고, 상기 산화막(22)상에 감광막 (23)을 도포한 다음, 노광 및 현상으로 후속 소스/드레인 영역이 형성될 부분을 패터닝한다. 이어 상기 패터닝된 감광막(23)을 마스크로 이용하여 하부의 산화막(22)을 소정 두께만큼 부분식각한다.As shown in FIG. 2A, an oxide film 22 is formed on a semiconductor substrate 21 completed by a well (not shown) and a threshold voltage ion implantation process, and a photosensitive film 23 is coated on the oxide film 22. Next, exposure and development pattern the portion where the subsequent source / drain regions will be formed. Subsequently, the lower oxide layer 22 is partially etched by a predetermined thickness using the patterned photoresist 23 as a mask.
도 2b에 도시된 바와 같이, 상기 감광막(23)을 제거한 후, 구조 전면에 측벽용 질화막을 형성한 다음, 전면식각하여 상기 부분식각된 산화막(22)의 양측벽에 접하는 질화막스페이서(24)를 형성한다. 이어 상기 질화막스페이서(24)를 마스크로 이용하여 NMOS의 LDD나 PMOS의 포켓 이온주입(Pocket implant)를 실시하여 저농도 소스/드레인(25)을 형성한다.As shown in FIG. 2B, after the photosensitive film 23 is removed, a nitride film for sidewall is formed on the entire surface of the structure, and then the entire surface is etched to form a nitride film spacer 24 in contact with both side walls of the partially etched oxide film 22. Form. Subsequently, a low concentration source / drain 25 is formed by performing an LDMOS of an NMOS or a pocket implant of a PMOS using the nitride film spacer 24 as a mask.
도 2c에 도시된 바와 같이, 상기 질화막스페이서(24)를 마스크로 이용하여 상기 저농도 소스/드레인(25)의 상부에 잔류하는 산화막(22)을 제거하여 상기 저농도 소스/드레인(25)의 표면을 노출시킨다. 여기서, 도면부호 22a는 노출된 후 잔류하는 산화막을 나타낸다.As shown in FIG. 2C, the surface of the low concentration source / drain 25 is removed by removing the oxide layer 22 remaining on the low concentration source / drain 25 using the nitride layer spacer 24 as a mask. Expose Here, reference numeral 22a denotes an oxide film remaining after exposure.
이어 상기 질화막스페이서(24)를 마스크로 이용한 고농도 불순물 이온주입으로 상기 저농도 소스/드레인(25)에 접하는 고농도 소스/드레인(26)을 형성한 다음,상기 고농도 소스/드레인(25)을 포함한 전면에 폴리실리콘(27)을 형성한다.Subsequently, a high concentration source / drain 26 in contact with the low concentration source / drain 25 is formed by high concentration impurity ion implantation using the nitride film spacer 24 as a mask, and then the front surface including the high concentration source / drain 25 is formed. Polysilicon 27 is formed.
도 2d에 도시된 바와 같이, 상기 폴리실리콘(27)을 화학적기계적연마 (Chemical Mechanical Polishing; CMP)하거나 플러그 식각(Plug etch)을 실시하여 소스/드레인패드(27a)를 형성한다. 이 때, 하부의 질화막스페이서(24)도 소정 두께만큼 제거하여 직사각형 형태의 질화막스페이서(24a)을 형성한다.As shown in FIG. 2D, the polysilicon 27 is subjected to chemical mechanical polishing (CMP) or plug etching to form a source / drain pad 27a. At this time, the lower nitride film spacer 24 is also removed by a predetermined thickness to form a rectangular nitride film spacer 24a.
상기와 같이, 저농도 소스/드레인(25)을 형성하기 위한 얕은 이온주입을 실시했을 때도 소스/드레인패드(27a)를 형성하므로써 반도체기판(21)의 손실뿐만 아니라 후속 배리어메탈(Barrier metal)에 의한 티타늄실리사이드로 인하여 발생할 수 있는 누설(Leakage)을 방지할 수 있다.As described above, even when shallow ion implantation for forming the low concentration source / drain 25 is performed, not only the loss of the semiconductor substrate 21 but also the subsequent barrier metal is formed by forming the source / drain pad 27a. It is possible to prevent leakage caused by titanium silicide.
이어 상기 소스/드레인 패드(27a) 및 질화막스페이서(24a)를 마스크로 이용하여 상기 산화막(22a)을 제거하므로써 후속 게이트전극이 형성될 반도체기판(21)을 노출시킨다. 이 때, 상기 질화막스페이서(24a)의 하부에는 소정 두께의 산화막 (22b)이 잔류한다.Subsequently, the oxide film 22a is removed using the source / drain pad 27a and the nitride film spacer 24a as a mask to expose the semiconductor substrate 21 on which a subsequent gate electrode is to be formed. At this time, an oxide film 22b having a predetermined thickness remains below the nitride film spacer 24a.
도 2e에 도시된 바와 같이, 상기 노출된 반도체기판(21)상게 게이트산화막 (28), 게이트전극용 폴리실리콘(도시 생략)을 형성한 다음, 상기 폴리실리콘과 게이트산화막(28)을 선택적으로 식각하여 게이트전극(29)을 형성한다. 이 때, 상기 게이트전극(29)의 양측면과 모서리부분이 노출된다.As shown in FIG. 2E, a gate oxide layer 28 and a polysilicon (not shown) for a gate electrode are formed on the exposed semiconductor substrate 21, and then the polysilicon and the gate oxide layer 28 are selectively etched. The gate electrode 29 is formed. At this time, both side surfaces and corner portions of the gate electrode 29 are exposed.
이어 상기 게이트전극(29)을 포함한 전면에 티타늄을 형성한 후, 열처리하여 상기 게이트전극(29)의 표면에 티타늄실리사이드(30)를 형성한다. 이 때, 상기 게이트전극(29)의 양측 하부에 소정 폭만큼 노출된 질화막스페이서(24a)의 상부에는티타늄이 반응하지 않으므로 실리사이드막이 형성되지 않는다.Subsequently, titanium is formed on the entire surface including the gate electrode 29 and then heat-treated to form titanium silicide 30 on the surface of the gate electrode 29. At this time, since the titanium does not react on the upper portion of the nitride film spacer 24a exposed to the lower portion of both sides of the gate electrode 29 by a predetermined width, no silicide film is formed.
상술한 바와 같이, 게이트전극(29)의 모서리부분을 노출시키므로 티타늄실리사이드(30) 형성시 게이트전극(29)의 중심부분과 모서리 부분의 실리사이드화율을 동일하게 하여 즉, 모서리부분의 실리사이드화율(Silicidation rate)을 증가시키므로써 티타늄과 실리콘의 공급이 잘 이루어져 균일한 결합을 갖는 티타늄실리사이드 (30)를 형성한다.As described above, since the corner portion of the gate electrode 29 is exposed, the silicide rate of the center portion and the corner portion of the gate electrode 29 is the same when the titanium silicide 30 is formed, that is, the silicide rate of the edge portion (Silicidation). By increasing the rate, titanium and silicon are well supplied to form titanium silicide 30 having a uniform bond.
도 3은 본 발명의 다른 실시예에 따라 형성된 반도체소자를 도시한 도면으로서, 도 2a 내지 도 2d에 따라 소스/드레인 패드(27a)를 형성한 후, 노출된 반도체기판(21)상에 게이트산화막(28), 게이트전극용 폴리실리콘을 형성한다.3 is a diagram illustrating a semiconductor device formed according to another exemplary embodiment of the present invention. After forming the source / drain pads 27a according to FIGS. 2A to 2D, the gate oxide layer is exposed on the exposed semiconductor substrate 21. (28) Polysilicon for gate electrode is formed.
이어 상기 게이트전극용 폴리실리콘을 마스크없이 플러그에치백하거나 화학적기계적연마하여 게이트전극(29)을 형성하고 질화막스페이서(24b) 및 게이트산화막(28)을 선택적으로 식각하여 게이트전극(29)의 측면 및 모서리 부분을 노출시킨 다음, 상기 노출된 게이트전극(29)을 포함한 전면에 티타늄을 형성한다. 이어 실리사이드반응을 위한 열처리를 실시하여 상기 게이트전극(29)의 상면에 소정 두께의 티타늄실리사이드(30)를 형성한다.Subsequently, the gate silicon 29 is formed by plugging back the polysilicon for the gate electrode without a mask or by chemical mechanical polishing, and selectively etching the nitride film spacer 24b and the gate oxide film 28 to form the gate electrode 29. After exposing the edge portion, titanium is formed on the entire surface including the exposed gate electrode 29. Subsequently, a heat treatment for silicide reaction is performed to form titanium silicide 30 having a predetermined thickness on the top surface of the gate electrode 29.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 듀얼 게이트전극 형성시 게이트전극의 측면 및 모서리 부분을 노출시키므로써 게이트전극의 모서리에서의 티타늄실리사이드화율을 높여 균일한 실리사이드를 구현할 수 있으며, 소스/드레인 패드를 이용하므로써 얕은 접합 형성시 반도체기판의 손실이나 티타늄실리사이드의 손실을 감소시킬 수 있는 효과가 있다.In the present invention as described above, when the dual gate electrode is formed, the side and edge portions of the gate electrode are exposed to increase the titanium silicide rate at the edge of the gate electrode, thereby realizing uniform silicide, and using the source / drain pad When the junction is formed, there is an effect of reducing the loss of the semiconductor substrate or the loss of titanium silicide.
Claims (14)
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