KR20010096353A - Structure For Forming The Registance Using Active Region - Google Patents
Structure For Forming The Registance Using Active Region Download PDFInfo
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- KR20010096353A KR20010096353A KR1020000020450A KR20000020450A KR20010096353A KR 20010096353 A KR20010096353 A KR 20010096353A KR 1020000020450 A KR1020000020450 A KR 1020000020450A KR 20000020450 A KR20000020450 A KR 20000020450A KR 20010096353 A KR20010096353 A KR 20010096353A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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Abstract
Description
본 발명은, 반도체소자의 활성영역을 이용하여 저항을 형성하는 방법에 관한 것으로서, 특히, 반도체기판상의 활성영역을 저항으로 사용하면서도 층간절연막을 평탄화할 때, 폴리1이 어택을 받아서 손상을 입는 것을 방지하도록 하는 활성영역을 이용한 저항 형성구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a resistor using an active region of a semiconductor device, and more particularly, to prevent poly1 from being attacked and damaged when planarizing an interlayer insulating film while using an active region on a semiconductor substrate as a resistor. It relates to a resistance forming structure using an active region to prevent.
일반적으로, 전압 발생기(Voltage Generator)에서 처럼 N+ 활성영역을 저항을 사용할 때는 주어진 좁은 면적을 최대한으로 활용하기 위하여 소자분리막을 연속적인 패턴(Continuity Pattern)으로 구불구불하게 형성하도록 한다.In general, when using a resistance in the N + active region as in a voltage generator (Voltage Generator), to form the device separator in a continuous pattern (Continuity Pattern) in order to make the best use of a given small area.
도 1(a)은 종래의 일실시예에 따른 반도체소자의 패턴구조를 보인 평면도이고, 도 1(b)는 도 1(a)의 A-A선 단면을 보인 도면이다.FIG. 1A is a plan view illustrating a pattern structure of a semiconductor device according to an exemplary embodiment, and FIG. 1B is a cross-sectional view taken along line A-A of FIG. 1A.
반도체기판(1)에 소자분리막 공정으로 소자분리막(3)을 일정 간격으로 형성하여서 저항으로 사용되는 활성영역(Active Region)을 구불구불하게 형성하도록 한다.The device isolation film 3 is formed on the semiconductor substrate 1 by a device isolation film process at regular intervals so as to form an active region used as a resistance.
그 후 폴리1을 형성하고 임플랜테이션(Implantation)을 진행하여 N+ 활성영역을 형성한다.Thereafter, poly 1 is formed and implantation is performed to form an N + active region.
그리고, 상기 결과물 상에 층간절연막을 적층한 후, CMP연마(Chemical Mechanical Polishing)공정으로 평탄화하게 되면 도 1(b)에 도시된 상태로 형성되어진다.After the interlayer insulating film is laminated on the resultant, the interlayer insulating film is formed and then planarized by a chemical mechanical polishing (CMP) polishing process to form a state shown in FIG.
그러나, 상기 폴리1(4) 사이의 간격이 매우 넓기 때문에 층간절연막(5)의 중간부위가 심하게 연마되는 문제를 유발하게 되고, 그로 인하여 폴리1(4)의 상측부분에 치명적인 어택부위(6)가 발생되어져서 소자의 특성을 나쁘게 하는 문제점을 지닌다.However, since the spacing between the poly 1 (4) is very wide, the middle portion of the interlayer insulating film 5 is severely polished, thereby causing a fatal attack portion 6 on the upper portion of the poly 1 (4). Is generated to deteriorate the characteristics of the device.
상기한 문제를 해결하기 위하여 다른 실시예를 제시하고 있다.In order to solve the above problem, another embodiment is presented.
도 2(a)는 종래의 다른 실시예에 따른 반도체소자의 패턴구조를 보인 도면이고, 도 2(b)는 도 2(b)의 B-B선 단면을 보인 도면이다.FIG. 2A is a view showing a pattern structure of a semiconductor device according to another exemplary embodiment, and FIG. 2B is a cross-sectional view taken along the line B-B of FIG. 2B.
다른 실시에의 경우에는 상기한 일실시예의 패턴구조를 그대로 사용하면서, 중심부분에 형성된 소자분리막(3) 상에 더미폴리1(7)을 형성한 후, 층간절연막을 CMP연마공정으로 평탄화하도록 하는 상태를 도시하고 있다.In another embodiment, the dummy poly 1 (7) is formed on the device isolation film 3 formed at the center portion while using the pattern structure of the above embodiment as it is, and then the interlayer insulating film is planarized by a CMP polishing process. The state is shown.
한편, 다른 실시예의 경우에는, 더미폴리(7)로 인하여 일실시예에서 어택을 받던 폴리1(4)이 층간절연막(7)에 형성되는 더미폴리(7)로 인하여 함몰되는 것이 방지되므로 인하여 정상적인 상태로 형성되어지는 장점을 지닌 반면에 소자분리막(3) 상에 더미폴리1(7)이 적층되어지므로 접착성(Adhesion)이 나빠지는 문제점을 지닌다.On the other hand, in the case of another embodiment, since the poly 1 (4) under attack in one embodiment due to the dummy poly (7) is prevented from sinking due to the dummy poly (7) formed in the interlayer insulating film (7) is normal On the other hand, since the dummy poly 1 (7) is laminated on the device isolation layer 3, the adhesion is deteriorated.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판 상에 소자분리막을 형성한 후, 저항으로 사용하는 활성영역 상에 더미 폴리1라인을 형성하고 임프랜테이션(Implantation)을 진행하여 셀프얼라인(Self-Align) N+ 활성영역을 형성한 후 층간절연막을 적층하여 CMP연마공정을 진행하므로 N+ 활성영역을 저항으로 사용하면서도 층간절연막을 평탄화할 때, 폴리1이 어택을 받아서 손상을 입는 것을 방지하도록 하는 것이 목적이다.The present invention has been made in view of this point, and after forming an isolation layer on a semiconductor substrate, a dummy poly 1 line is formed on an active region to be used as a resistance and an implantation is performed to perform self-alignment. (Self-Align) CMP polishing process is performed by stacking the interlayer insulating film after forming the N + active area so that when the interlayer insulating film is planarized while using the N + active area as a resistance, the poly1 is attacked to prevent damage. The purpose is to.
도 1(a)은 종래의 일실시예에 따른 반도체소자의 패턴구조를 보인 평면도이고,1 (a) is a plan view showing a pattern structure of a semiconductor device according to a conventional embodiment,
도 1(b)는 도 1(a)의 A-A선 단면을 보인 도면이고,Figure 1 (b) is a cross-sectional view taken along the line A-A of Figure 1 (a),
도 2(a)는 종래의 다른 실시예에 따른 반도체소자의 패턴구조를 보인 도면이고,2 (a) is a view showing a pattern structure of a semiconductor device according to another conventional embodiment;
도 2(b)는 도 2(b)의 B-B선 단면을 보인 도면이고,Figure 2 (b) is a cross-sectional view taken along the line B-B of Figure 2 (b),
도 3(a)는 본 발명에 따른 반도체소자의 패턴구조를 보인 도면이고,3 (a) is a view showing a pattern structure of a semiconductor device according to the present invention,
도 3(b)는 도 3(b)의 C-C선 단면을 보인 도면이다.FIG. 3B is a cross-sectional view taken along the line C-C in FIG. 3B.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 15 : 활성영역10: semiconductor substrate 15: active region
20 : 소자분리막 25 : 층간절연막20 device isolation layer 25 interlayer insulating film
30 : 더미폴리1 35 : 폴리130: dummy poly 1 35: poly 1
이러한 목적은 반도체기판 상에 소자분리막 및 활성영역을 형성하는 소자구조에 있어서, 상기 활성영역을 저항으로 사용하고, 상기 활성영역 상에 더미폴리1 (Dummy Poly1)을 형성하여 CMP연마공정으로 평탄화하여 이루어진 활성영역을 이용한 저항 형성구조를 제공함으로써 달성된다.This purpose is to use the active region as a resistance in the device structure for forming an isolation layer and an active region on the semiconductor substrate, and to form a dummy poly 1 on the active region to planarize by a CMP polishing process It is achieved by providing a resistance forming structure using the active region.
그리고, 상기 더미폴리1은 N+ 혹은 P+임플랜트 전에 활성영역 상에 형성하는 것이 바람직 하다.In addition, the dummy poly 1 is preferably formed on the active region before the N + or P + implant.
상기 활성영역을 이용하여 소자의 신호전달 및 응답속도를 조절하는 것이 바람직 하다.It is preferable to control the signal transmission and response speed of the device using the active region.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 3(a)는 본 발명에 따른 반도체소자의 패턴구조를 보인 도면이고, 도 3(b)는 도 3(b)의 C-C선 단면을 보인 도면이다.FIG. 3 (a) is a view showing a pattern structure of a semiconductor device according to the present invention, and FIG. 3 (b) is a view showing a C-C cross section of FIG. 3 (b).
본 발명에 따른 구조를 살펴 보면, 반도체기판(10) 상에 소자분리막(20) 및 활성영역(15)을 형성하는 소자구조에 있어서, 상기 활성영역(15) 상에 더미폴리1 (30)을 형성한 후, 임플랜테이션(Implantation)을 진행하여 활성영역을 (N+/P+)활성영역으로 만든 뒤 층간절연막(25)을 적층한 후 CMP연마공정으로 평탄화하여 이루어진다.Referring to the structure according to the present invention, in the device structure for forming the isolation layer 20 and the active region 15 on the semiconductor substrate 10, the dummy poly 1 (30) on the active region 15 After the formation, implantation is performed to make the active region into (N + / P +) active region, and the interlayer insulating layer 25 is laminated and planarized by a CMP polishing process.
그리고, 상기 더미폴리1(30)은 N+ 혹은 P+임플랜트(Implant) 전에 활성영역 (15) 상에 형성하도록 한다.In addition, the dummy poly 1 (30) is formed on the active region 15 before the N + or P + implant (Implant).
상기 활성영역을 이용하여 소자의 신호전달 및 응답속도를 조절하도록 한다.The signal transmission and response speed of the device are controlled using the active region.
상기 더미폴리1(30)으로 인하여 층간절연층(25)이 평탄하게 연마되므로 폴리1(35)의 과도 연마로 인하여 어택(Attack)을 받게 되는 것을 방지하게 된다.Since the interlayer insulating layer 25 is polished flat due to the dummy poly 1 30, it is prevented from being attacked due to excessive polishing of the poly 1 35.
한편, N+ 액티브의 저항은 R =L/A 이므로 더미폴리1(30)의 콘택을 제어함으로 (N+/P+)활성영역(15)의 면적과 길이를 조절하여 제어할 수 있다.On the other hand, the resistance of N + active is R = Since L / A, the contact of the dummy poly 1 30 may be controlled to control the area and the length of the (N + / P +) active region 15.
상기한 바와 같이, 본 발명에 따른 활성영역을 이용한 저항 형성구조을 이용하게 되면, 반도체기판 상에 소자분리막을 형성한 후, 저항으로 사용하는 활성영역 상에 더미 폴리1라인을 형성하고 임프랜테이션(Implantation)을 진행하여 셀프얼라인(Self-Align) N+ 활성영역을 형성한 후 층간절연막을 적층하여 CMP연마공정을 진행하므로 N+ 활성영역을 저항으로 사용하면서도 층간절연막을 평탄화할 때, 폴리1이 어택을 받아서 손상을 입는 것을 방지하도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the resistance forming structure using the active region according to the present invention is used, an isolation layer is formed on the semiconductor substrate, and then a dummy poly 1 line is formed on the active region to be used as a resistor. Self-Align N + active region is formed by implantation and CMP polishing process is carried out by stacking the interlayer insulating film. Therefore, when the interlayer insulating film is planarized while using the N + active area as a resistance, poly1 attacks It is a very useful and effective invention that can prevent damage to the product.
즉 종래의 구불구불한 활성영역을 사용하는 대신에 본 발명의 경우에는 더미폴리라인을 사용하여 종래의 활성영역과 같이 주어진 면적을 최대한으로 이용할 수있을 뿐만아니라 폴리1의 어택을 방지하여 공정마아진을 충분하게 확보하도록 하는 장점을 지닌다.In other words, instead of using a conventional twisted active area, in the present invention, a dummy polyline can be used to maximize the area given as in the conventional active area, and also prevents the attack of poly 1 to reduce process margins. It has the advantage of securing enough.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100607806B1 (en) * | 2004-12-31 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method for improving the output gain uniformity |
US8482100B2 (en) | 2010-09-03 | 2013-07-09 | Samsung Electronics Co., Ltd. | Resistor array and semiconductor device including the same |
US8962422B2 (en) | 2012-06-14 | 2015-02-24 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor devices |
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- 2000-04-18 KR KR1020000020450A patent/KR20010096353A/en not_active Application Discontinuation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100607806B1 (en) * | 2004-12-31 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method for improving the output gain uniformity |
US8482100B2 (en) | 2010-09-03 | 2013-07-09 | Samsung Electronics Co., Ltd. | Resistor array and semiconductor device including the same |
US8962422B2 (en) | 2012-06-14 | 2015-02-24 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor devices |
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