KR20010078576A - Isolation area forming method of semiconductor device - Google Patents
Isolation area forming method of semiconductor device Download PDFInfo
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- KR20010078576A KR20010078576A KR1020000005944A KR20000005944A KR20010078576A KR 20010078576 A KR20010078576 A KR 20010078576A KR 1020000005944 A KR1020000005944 A KR 1020000005944A KR 20000005944 A KR20000005944 A KR 20000005944A KR 20010078576 A KR20010078576 A KR 20010078576A
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000002955 isolation Methods 0.000 title abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 격리영역 형성방법에 관한 것으로, 특히 트랜치를 이용하여 격리영역을 형성하면서 트랜치 상단 모서리부분의 손실을 방지하도록 함으로서 험프 특성을 개선하고, 후속 공정에서 게이트간 브릿지 발생을 방지하기에 적당하도록 한 반도체소자의 격리영역 형성방법에 관한 것이다.The present invention relates to a method for forming an isolation region of a semiconductor device, and in particular, by forming a isolation region using a trench to prevent loss of the top edge of the trench to improve hump characteristics, and to prevent the formation of bridges between gates in a subsequent process. The present invention relates to a method for forming an isolation region of a semiconductor device suitable for use.
종래 반도체소자의 격리영역 형성방법의 일실시예를 도 1a 내지 도 1d의 수순단면도를 참고하여 설명하면 다음과 같다.An embodiment of a method of forming an isolation region of a conventional semiconductor device will be described below with reference to the procedure cross-sectional view of FIGS. 1A to 1D.
반도체기판(1) 상부에 차례로 버퍼산화막(2), 질화막(3)을 형성하는 제 1공정과; 상기 형성한 질화막(3)을 비활성 영역부분만 오픈되도록 패터닝하고, 상기 질화막(3)을 하드마스크로 반도체기판(1)을 식각하여 트랜치(4)를 형성하는 제 2공정과; 상기 형성한 구조 상부전면에 절연막(5)을 증착하고, 이를 상기 질화막(3) 상부가 드러나도록 평탄화 하는 제 3공정과; 상기 드러난 질화막(3)을 습식식각하여 제거한 후 버퍼산화막(2)을 제거하는 제 4공정으로 이루어진다.A first step of forming a buffer oxide film (2) and a nitride film (3) on top of the semiconductor substrate (1); A second process of patterning the formed nitride film 3 so that only an inactive region is opened, and etching the semiconductor substrate 1 using the nitride film 3 as a hard mask to form a trench 4; A third step of depositing an insulating film (5) on the upper surface of the formed structure and planarizing it so that the upper portion of the nitride film (3) is exposed; A fourth process is performed by wet etching the exposed nitride film 3 and removing the buffer oxide film 2.
먼저, 도 1a에 도시한 바와 같이 반도체기판(1) 상부에 차례로 버퍼산화막(2), 질화막(3)을 형성한다.First, as shown in FIG. 1A, a buffer oxide film 2 and a nitride film 3 are sequentially formed on the semiconductor substrate 1.
이때, 상기 질화막(3)과 반도체기판(1)의 격자구조가 틀리기 때문에 반도체기판(1) 상에 질화막(3)을 직접 형성하면 반도체기판(1) 표면이 손상되므로 이를 방지하기위해 버퍼산화막(2)을 그 사이에 형성한다.At this time, since the lattice structure of the nitride film 3 and the semiconductor substrate 1 is different, if the nitride film 3 is directly formed on the semiconductor substrate 1, the surface of the semiconductor substrate 1 is damaged. 2) is formed between them.
그 다음, 도 1b에 도시한 바와 같이 상기 형성한 질화막(3)을 비활성 영역부분만 오픈되도록 패터닝하고, 상기 질화막(3)을 하드마스크로 반도체기판(1)을 식각하여 트랜치(4)를 형성한다.Next, as shown in FIG. 1B, the formed nitride film 3 is patterned to open only an inactive region, and the semiconductor substrate 1 is etched using the nitride film 3 as a hard mask to form a trench 4. do.
그 다음, 도 1c에 도시한 바와 같이 상기 형성한 구조 상부전면에 절연막(5)을 증착하고, 이를 상기 질화막(3) 상부가 드러나도록 평탄화 한다.Next, as illustrated in FIG. 1C, an insulating film 5 is deposited on the upper surface of the formed structure, and planarized so that the upper portion of the nitride film 3 is exposed.
그 다음, 도 1d에 도시한 바와 같이 상기 드러난 질화막(3)을 습식식각하여 제거한 후 버퍼산화막(2)을 제거한다.Then, as shown in FIG. 1D, the exposed nitride film 3 is removed by wet etching, and then the buffer oxide film 2 is removed.
이때, 상기 질화막(3)을 습식식각을 통해 제거하므로 이 과정에서 상기 절연막(5)또한 식각이 진행되고, 상기 질화막(3)과 접하는 계면부분(a)의 절연막(5)이 과다식각 된다.At this time, since the nitride film 3 is removed by wet etching, the insulating film 5 is also etched in this process, and the insulating film 5 of the interface portion a in contact with the nitride film 3 is overetched.
상기한 바와 같은 종래 반도체소자의 격리영역 형성방법은 질화막을 습식식각을 통해 제거하므로 그 과정에서 절연막 또한 그 영향으로 식각이 진행되고, 상기 질화막과 접하는 계면부분 절연막이 과다식각되어 험프 특성이 나빠지고, 후속공정에서 그 과다식각 부분에 폴리실리콘이 잔류하여 게이트간 브릿지를 유발하는 문제점이 있었다.Since the method of forming the isolation region of the conventional semiconductor device as described above removes the nitride film by wet etching, the insulating film is also etched under the influence of the nitride film, and the interface portion insulating film in contact with the nitride film is excessively etched, resulting in poor hump characteristics. In the subsequent process, polysilicon remains in the overetched portion, causing a bridge between gates.
본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 절연막과 질화막이 접하는 계면의 위치를 변경함으로써 과다식각부분 없이 평탄한 격리영역을 형성할 수 있어 소자의 전기적 신뢰성 및 후속공정에서 게이트간 브릿지발생을 방지할 수 있도록 한 반도체소자의 격리영역 형성방법을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to change the position of the interface between the insulating film and the nitride film to form a flat isolation region without an excessive etching portion, thereby providing electrical reliability of the device. And a method of forming an isolation region of a semiconductor device to prevent the occurrence of bridges between gates in a subsequent process.
도 1은 종래 반도체소자의 격리영역 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a method of forming an isolation region of a conventional semiconductor device.
도 2는 본 발명 일실시예의 수순단면도.Figure 2 is a cross-sectional view of the procedure of an embodiment of the present invention.
*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***
21 : 반도체기판 22 : 버퍼산화막21 semiconductor substrate 22 buffer oxide film
23 : 질화막 24 : 제 1절연막23 nitride film 24 first insulating film
25 : 트랜치 26 : 제 2절연막25 trench 26 second insulating film
PR : 감광막PR: Photosensitive Film
상기한 바와 같은 본 발명의 목적을 달성하기 위한 반도체소자의 격리영역 형성방법은 반도체기판 상부에 차례로 버퍼산화막, 질화막을 형성하고, 상기 질화막을 비활성영역부분보다 약간 크게 오픈되도록 패터닝한 후, 상기 구조 상부전면에 제 1절연막을 형성하는 제 1공정과; 상기 제 1절연막을 식각하여 상기 질화막의 측면에 측벽을 형성하여 비활성영역을 정의하고, 웨이퍼 상부 전면에 감광막을 형성하는 제 2공정과; 상기 감광막을 상기 비활성영역만 오픈되도록 패터닝한 후 이를 마스크로 상기 반도체기판을 식각하여 트랜치를 형성하는 제 3공정과; 상기 감광막 및 제 1절연막을 제거하고, 상기 형성한 구조 상부전면에 제 2절연막을 증착한 후 이를 상기 질화막 상부가 드러나도록 평탄화 하는 제 4공정과; 상기 드러난 질화막을 습식식각하여 제거한 후 버퍼산화막을 제거하는 제 5공정으로 이루어지는 것을 특징으로한다.According to the method of forming an isolation region of a semiconductor device as described above, a buffer oxide film and a nitride film are sequentially formed on an upper portion of a semiconductor substrate, and the patterned nitride film is opened slightly larger than an inactive region portion. Forming a first insulating film on an upper surface thereof; Etching the first insulating film to form sidewalls on the side surfaces of the nitride film to define an inactive region, and forming a photosensitive film on the entire upper surface of the wafer; A third process of patterning the photoresist to open only the inactive region and then etching the semiconductor substrate with a mask to form a trench; A fourth process of removing the photosensitive film and the first insulating film, depositing a second insulating film on the entire upper surface of the formed structure, and then planarizing the upper surface of the nitride film to expose the nitride film; And a fifth process of removing the buffer oxide layer by wet etching the exposed nitride layer.
상기한 바와 같은 본 발명에의한 반도체소자의 격리영역 형성방법을 도 2a 내지 도 2d에 도시한 수순단면도를 일 실시예로하여 상세히 설명하면 다음과 같다.A method of forming an isolation region of a semiconductor device according to the present invention as described above will be described in detail with reference to a cross-sectional view of the procedure shown in FIGS. 2A to 2D as an example.
먼저, 도 2a에 도시한 바와 같이 반도체기판(21) 상부에 차례로 버퍼산화막(22), 질화막(23)을 형성하고, 상기 질화막(23)을 비활성영역부분보다 약간 크게 오픈되도록 패터닝한 후, 상기 구조 상부전면에 제 1절연막(24)을 형성한다.First, as shown in FIG. 2A, a buffer oxide film 22 and a nitride film 23 are sequentially formed on the semiconductor substrate 21, and the nitride film 23 is patterned to open slightly larger than the inactive region. The first insulating film 24 is formed on the upper surface of the structure.
이때, 상기 질화막(23)과 반도체기판(21)의 격자구조가 틀리기 때문에 반도체기판(21) 상에 질화막(23)을 직접 형성하면 반도체기판(21) 표면이 손상되므로 이를 방지하기위해 버퍼산화막(22)을 그 사이에 형성한다.In this case, since the lattice structures of the nitride film 23 and the semiconductor substrate 21 are different, the formation of the nitride film 23 directly on the semiconductor substrate 21 damages the surface of the semiconductor substrate 21, so that the buffer oxide film ( 22) is formed therebetween.
그리고, 상기 질화막(23)을 패터닝할 경우 비활성영역의 크기에서 후속공정을 통해 형성할 측벽의 두께만큼 더 크게 오픈되도록 패터닝한다.When the nitride layer 23 is patterned, the nitride layer 23 is patterned so as to be opened larger by the thickness of the sidewall to be formed through a subsequent process in the size of the inactive region.
그 다음, 도 2b에 도시한 바와 같이 상기 제 1절연막(24)을 식각하여 상기 질화막(23)의 측면에 측벽을 형성하여 비활성영역을 정의하고, 웨이퍼 상부 전면에 감광막(PR)을 형성한다.Next, as shown in FIG. 2B, the first insulating layer 24 is etched to form sidewalls on the side of the nitride layer 23 to define an inactive region, and to form the photoresist layer PR on the entire upper surface of the wafer.
그 다음, 도 2c에 도시한 바와 같이 상기 감광막(PR)을 상기 비활성영역만 오픈되도록 패터닝한 후 이를 마스크로 상기 반도체기판(21)을 식각하여 트랜치(25)를 형성한다.Next, as shown in FIG. 2C, the photoresist film PR is patterned to open only the inactive region, and then the semiconductor substrate 21 is etched using a mask to form a trench 25.
그 다음, 도 2d에 도시한 바와 같이 상기 감광막(PR) 및 제 1절연막(24)을 제거하고, 상기 형성한 구조 상부전면에 제 2절연막(26)을 증착한 후 이를 상기 질화막(23) 상부가 드러나도록 평탄화 한다.Next, as shown in FIG. 2D, the photoresist film PR and the first insulation film 24 are removed, and a second insulation film 26 is deposited on the entire upper surface of the formed structure, and then the upper portion of the nitride film 23 is formed. Flatten to reveal.
이때, 상기 질화막(23)의 측벽역할을 하던 제 1절연막(24)이 제거됨으로 인해 트랜치(25) 주변의 반도체기판(21) 표면이 드러나게되고, 이부분에 제 2절연막(26)이 형성되므로 평탄화과정 후 트랜치(25)를 채우는 제 2절연막(26)은 T자 형상이 된다.In this case, the surface of the semiconductor substrate 21 around the trench 25 is exposed due to the removal of the first insulating layer 24 serving as a sidewall of the nitride layer 23, and the second insulating layer 26 is formed therein. After the planarization process, the second insulating layer 26 filling the trench 25 becomes T-shaped.
그 다음, 도 2e에 도시한 바와 같이 상기 드러난 질화막(23)을 습식식각하여 제거한 후 버퍼산화막(22)을 제거한다.Next, as shown in FIG. 2E, the exposed nitride layer 23 is removed by wet etching, and then the buffer oxide layer 22 is removed.
이때, 상기 질화막(23)을 습식식각을 통해 제거하므로 그 과정에서 절연막또한 그 영향으로 식각이 진행되고, 이에따라 상기 질화막(23)과 제 2절연막(26)이 접하는 계면부분에서 제 2절연막(26)이 과다식각 되더라도 격리영역을 형성하는 트랜치(25)외부에서 발생하며, 식각을 통해 제거되는 부분이므로 소자 특성에 영향을 주지 않게 된다.At this time, since the nitride film 23 is removed by wet etching, etching is performed under the influence of the insulating film in the process, and accordingly, the second insulating film 26 is formed at the interface portion between the nitride film 23 and the second insulating film 26. ) Is excessively etched outside the trench 25 forming the isolation region, and is removed by etching, and thus does not affect device characteristics.
따라서, 상부가 평탄한(b) 격리영역을 형성할 수 있다.Therefore, it is possible to form an isolation region with a flat top.
상기한 바와 같은 본 발명 반도체소자의 격리영역 형성방법은 절연막 측벽을 사용함으로써 절연막과 질화막이 접하는 계면의 위치를 트랜치의 외부로 변경하여 과다식각 부분 없이 평탄한 격리영역을 형성할 수 있으므로 소자의 전기적 신뢰성 및 후속공정에서 게이트간 브릿지발생을 방지할 수 있는 효과가 있다.As described above, the method for forming an isolation region of a semiconductor device according to the present invention can change the position of the interface between the insulation layer and the nitride layer to the outside of the trench by forming the isolation region outside the trench, thereby forming a flat isolation region without excessive etching. And there is an effect that can prevent the gate-to-gate bridge in the subsequent process.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980073666A (en) * | 1997-03-18 | 1998-11-05 | 문정환 | Semiconductor Device Isolation Method |
| KR0151051B1 (en) * | 1995-05-30 | 1998-12-01 | 김광호 | Method of forming insulation film for semiconductor device |
| KR0174659B1 (en) * | 1996-01-27 | 1999-02-01 | 서욱승 | Method for polluted water treatment using high-concentrated aeration |
| KR20000004532A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Method for manufacturing an isolation layer of semiconductor devices |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0151051B1 (en) * | 1995-05-30 | 1998-12-01 | 김광호 | Method of forming insulation film for semiconductor device |
| KR0174659B1 (en) * | 1996-01-27 | 1999-02-01 | 서욱승 | Method for polluted water treatment using high-concentrated aeration |
| KR19980073666A (en) * | 1997-03-18 | 1998-11-05 | 문정환 | Semiconductor Device Isolation Method |
| KR20000004532A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Method for manufacturing an isolation layer of semiconductor devices |
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