KR20010046832A - Chip Scale Package - Google Patents

Chip Scale Package Download PDF

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Publication number
KR20010046832A
KR20010046832A KR1019990050754A KR19990050754A KR20010046832A KR 20010046832 A KR20010046832 A KR 20010046832A KR 1019990050754 A KR1019990050754 A KR 1019990050754A KR 19990050754 A KR19990050754 A KR 19990050754A KR 20010046832 A KR20010046832 A KR 20010046832A
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KR
South Korea
Prior art keywords
chip
semiconductor chip
solder mask
solder
conductive pattern
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KR1019990050754A
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Korean (ko)
Inventor
최신
Original Assignee
박종섭
주식회사 하이닉스반도체
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Priority to KR1019990050754A priority Critical patent/KR20010046832A/en
Publication of KR20010046832A publication Critical patent/KR20010046832A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A chip scale semiconductor package is provided to be adapted for a multi-pin package by overcoming the limit of a ribbon bonding process to correspond to a fine pitch pad even when a semiconductor chip is smaller than a solder ball array. CONSTITUTION: A semiconductor chip(201) has an insulating layer(210) where respective windows(c) exposing a chip pad to an upper surface of the insulating layer is patterned. A solder mask(204) has a plurality of penetration holes and solder balls(205), covering the semiconductor chip. A metal foil(212) covering the penetration holes is formed in an outer portion covering the semiconductor chip, formed on the back surface of the solder mask having the solder ball. A conductive pattern(214) is interposed between the solder mask and the semiconductor chip. One side of the conductive pattern covers the respective windows on the insulating layer to be connected to the chip pad. The other side of the conductive pattern is coupled to the metal foil to be connected to the solder ball through the penetration hole formed in the outer portion. A molding compound(206) seals the side surface of the semiconductor chip, including the conductive pattern.

Description

칩규모의 반도체패키지{Chip Scale Package}Chip Scale Package {Chip Scale Package}

본 발명은 반도체패키지(semiconductor package)에 관한 것으로, 특히, 반도체소자가 고집적화됨에 따라, 소형화된 반도체칩의 미세 피치패드에 대응하도록 칩규모의 형태로 제조함으로써 크기를 최소화하기에 용이한 칩규모의 반도체패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and in particular, as semiconductor devices are highly integrated, chip size is easy to minimize the size by manufacturing in the form of chip size to correspond to the fine pitch pad of the miniaturized semiconductor chip. It relates to a semiconductor package.

반도체소자가 고집적화됨에 따라, 개별적인 칩단위로 절단되는 반도체칩의 크기도 점점 소형화되어가는 추세이다. 따라서, 소형화된 반도체칩을 이용하여 반도체패키지 제조 시에는 패키지 크기가 작은 CSP(Chip Scale Package)타입이 적합하다.As semiconductor devices are highly integrated, the size of semiconductor chips cut into individual chip units is also becoming smaller. Therefore, a chip scale package (CSP) type having a small package size is suitable for manufacturing a semiconductor package using a miniaturized semiconductor chip.

도 1은 종래기술에 따른 CSP타입의 반도체패키지의 단면도이다.1 is a cross-sectional view of a CSP type semiconductor package according to the prior art.

종래의 반도체패키지는 도 1과 같이, 다 수개의 솔더볼(solder ball)(105) 및 관통홀(h1)이 형성된 솔더마스크(solder mask)(104)와, 다 수개의 칩패드(미도시)가 형성된 반도체칩(101)과, 반도체칩(101)과 솔더마스크(104)에 개재되어, 일측은 솔더마스크(104)와 연결되고 타측에는 반도체칩 상의 다 수개의 칩패드와 연결되는 도전패턴(103)과, 솔더마스크(104)의 각각의 관통홀(h1)을 채우면서 도전패턴(103)을 포함하여 반도체칩(101)의 측면을 밀봉시키는 몰딩컴파운드(106)로 구성된다.The conventional semiconductor package, as shown in FIG. 1, includes a solder mask 104 having a plurality of solder balls 105 and a through hole h1, and a plurality of chip pads (not shown). Interposed between the formed semiconductor chip 101, the semiconductor chip 101 and the solder mask 104, one side is connected to the solder mask 104, the other side is connected to a plurality of chip pads on the semiconductor chip 103 ) And a molding compound 106 which seals the side surface of the semiconductor chip 101 including the conductive pattern 103 while filling each through hole h1 of the solder mask 104.

도면에는 도시되어 있지 않지만, 솔더볼(105)이 형성된 솔더마스크(104) 이면에 구리 등의 금속포일이 실장되어 있다.Although not shown in the figure, a metal foil such as copper is mounted on the back surface of the solder mask 104 on which the solder balls 105 are formed.

상기 구성을 갖는 종래의 칩규모의 반도체패키지의 제작과정을 알아본다.The fabrication process of a conventional chip-scale semiconductor package having the above configuration will be described.

먼저, 웨이퍼를 개별적인 칩단위로 쏘잉(sawing)하여 패키징할 반도체칩(101)을 준비한다.First, the semiconductor chip 101 to be packaged is prepared by sawing the wafer in individual chip units.

솔더마스크(104)는 반도체칩(101)과의 리본본딩을 위한 다 수개의 관통홀(h1)이 형성되어 있고, 솔더볼(105)이 형성된 솔더마스크(104) 이면에 구리 등의 금속포일이 실장되어 있다.The solder mask 104 includes a plurality of through holes h1 for ribbon bonding with the semiconductor chip 101, and a metal foil such as copper is mounted on the back surface of the solder mask 104 on which the solder balls 105 are formed. It is.

이 후, 반도체칩(101)과 솔더마스크(104) 사이에 메탈에칭을 통해 도전패턴(103)이 형성된다.Thereafter, a conductive pattern 103 is formed between the semiconductor chip 101 and the solder mask 104 through metal etching.

도전패턴(103)은 일측에는 절연테이프(102)를 개재시키어 반도체칩(101)의 칩패드와 접촉되고, 타측에는 솔더마스크(105)의 저면, 즉, 솔더볼(105)이 형성된 이면과 접촉된다.The conductive pattern 103 is in contact with the chip pad of the semiconductor chip 101 with an insulating tape 102 on one side thereof, and the bottom of the solder mask 105, that is, with the back surface on which the solder ball 105 is formed. .

따라서, 도전패턴(103)은 반도체칩(101)의 칩패드 및 솔더마스크(104)의 솔더볼(105)과 전기적으로 연결된다.Therefore, the conductive pattern 103 is electrically connected to the chip pad of the semiconductor chip 101 and the solder ball 105 of the solder mask 104.

그리고 솔더마스크(104)의 관통홀(h1)을 통하여 반도체칩(101)과 도전패턴(103)의 리본본딩이 진행된다.Then, ribbon bonding of the semiconductor chip 101 and the conductive pattern 103 is performed through the through hole h1 of the solder mask 104.

리본본딩이 진행된 후, 솔더마스크의 관통홀(h1) 내부에 에폭시(epoxy) 등을 주입함으로써 도전패턴(103)을 포함하여 반도체칩(101)의 측면을 밀봉시키는 몰딩컴파운드(106)를 형성한다.After the ribbon bonding is performed, a molding compound 106 is formed to seal the side surface of the semiconductor chip 101 including the conductive pattern 103 by injecting epoxy or the like into the through-hole h1 of the solder mask. .

그러나, 종래의 기술에서는 반도체칩이 솔더볼 어레이보다 작아지는 경우(fan out)에 대응하지 못하고, 또한, 본딩된 리본이 불안정하여 쉽게 끊어질 뿐만 아니라, 리본본딩을 위한 별도의 영역이 필요하므로 패키지의 다핀화에 적합하지 못하였다.However, in the related art, the semiconductor chip does not cope with fan out of the solder ball array, and because the bonded ribbon is unstable and easily broken, a separate area for ribbon bonding is required. Not suitable for polyfinization.

즉, 종래의 기술에서는 고밀도 다핀화되는 추세에 맞춰 미세 피치패드(pitch pad)에 대응하지 못한 문제점이 있었다.That is, in the related art, there is a problem in that it cannot cope with the fine pitch pad in accordance with the trend of high density multi-pinning.

상기의 문제점을 해결하고자, 본 발명의 목적은 반도체칩의 미세 피치패드에 대응할 수 있는 최소 규모의 반도체패키지를 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to provide a semiconductor package of the minimum size that can correspond to the fine pitch pad of the semiconductor chip.

상기 목적을 달성하고자, 본 발명의 칩규모의 반도체패키지는 상면에 칩패드를 노출시키는 각각의 창이 패터닝된 절연막을 갖는 반도체칩과, 반도체칩을 커버링하며 다 수개의 관통홀 및 솔더볼이 형성된 솔더마스크와, 솔더볼이 형성된 솔더마스크의 이면에 형성되며, 반도체칩을 커버링하는 외곽 부위에 형성된 관통홀을 덮는 금속포일과, 솔더마스크와 반도체칩 사이에 개재되며, 일측은 절연막 상에서 각각의 창을 덮어 칩패드와 연결되고 타측은 금속포일을 덮어 외곽부위에 형성된 관통홀을 통해 솔더볼과 연결되는 도전패턴과, 도전패턴을 포함하여 반도체칩의 측면을 밀봉시키는 몰딩컴파운드를 구비한 것이 특징이다.In order to achieve the above object, the chip-scale semiconductor package of the present invention includes a semiconductor chip having an insulating film patterned on each window exposing chip pads on an upper surface thereof, and a solder mask covering a semiconductor chip and formed with a plurality of through holes and solder balls. And a metal foil covering the through hole formed on the outer surface of the solder mask on which the solder ball is formed, and interposed between the solder mask and the semiconductor chip, and one side covering each window on the insulating film. The pad is connected to the pad and the other side includes a conductive pattern connected to the solder ball through a through hole formed at an outer portion of the metal foil, and a molding compound sealing the side surface of the semiconductor chip including the conductive pattern.

도 1은 종래기술에 따른 칩규모의 반도체패키지의 단면도이고,1 is a cross-sectional view of a chip-scale semiconductor package according to the prior art,

도 2는 본 발명에 따른 칩규모의 반도체패키지의 단면도이고,2 is a cross-sectional view of a chip-scale semiconductor package according to the present invention,

도 3 내지 도 7은 본 발명에 따른 칩규모의 반도체패키지의 제작과정을 보인 도면이다.3 to 7 are diagrams illustrating a manufacturing process of a chip-scale semiconductor package according to the present invention.

*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

101, 201. 반도체칩 104, 204. 솔더마스크101, 201. Semiconductor chip 104, 204. Solder mask

105, 205. 솔더볼 106, 206. 몰딩컴파운드105, 205. Solder balls 106, 206. Molding compound

h1, h2. 관통홀 c. 창(window)h1, h2. Through-hole c. Window

212. 금속포일 210. 절연막212. Metal foil 210. Insulation film

214. 도전패턴214. Challenge pattern

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2는 본 발명에 따른 칩규모의 반도체패키지의 단면도이고, 도 3 내지 도 7은 본 발명에 따른 칩규모의 반도체패키지의 제작과정을 보인 도면이다.2 is a cross-sectional view of a chip-scale semiconductor package according to the present invention, Figures 3 to 7 is a view showing a manufacturing process of a chip-scale semiconductor package according to the present invention.

본 발명의 칩규모의 반도체패키지는 도 2와 같이, 상면에 칩패드(미도시)를 노출시키는 각각의 창(c)이 패터닝된 절연막(210)을 갖는 반도체칩(201)과, 반도체칩(201)을 커버링하며, 다 수개의 관통홀(h2) 및 솔더볼(205)이 형성된 솔더마스크(204)와, 솔더볼(205)이 형성된 솔더마스크(204)의 이면에 형성되며, 반도체칩(201)을 커버링하는 외곽 부위에 형성된 관통홀(h2)을 덮는 금속포일(metal foil)(212)과, 솔더마스크와 반도체칩 사이에 개재되며, 일측은 절연막(210) 상에서 각각의 창을 덮어 칩패드와 연결되고 타측은 금속포일(212)을 덮어 외곽부위에 형성된 관통홀(h2)을 통해 솔더볼(205)과 연결되는 도전패턴(214)과, 도전패턴을 포함하여 반도체칩(201)의 측면을 밀봉시키는 몰딩컴파운드(206)로 구성된다.As shown in FIG. 2, the chip-scale semiconductor package of the present invention includes a semiconductor chip 201 having an insulating film 210 patterned with respective windows c exposing chip pads (not shown), and a semiconductor chip ( 201, which is formed on the back surface of the solder mask 204 having the plurality of through holes h2 and the solder balls 205 and the solder mask 204 having the solder balls 205 formed thereon, and the semiconductor chip 201. The metal foil 212 covering the through hole h2 formed in the outer portion covering the gap is interposed between the solder mask and the semiconductor chip, and one side of the chip pad covers each window on the insulating film 210. The other side is sealed to the side surface of the semiconductor chip 201 including a conductive pattern 214 and the conductive pattern connected to the solder ball 205 through the through hole (h2) formed on the outer portion covering the metal foil 212 It is composed of a molding compound (206).

솔더마스크(204)은 절연필름으로, 일면에는 다 수개의 솔더볼(205)이 형성되고, 타면에는 도 3과 같이, 반도체칩(201)을 커버링하는 외곽부위에 관통홀(h2)을 덮도록 구리성분인 금속포일(212)이 부착되어 있다.The solder mask 204 is an insulating film, and a plurality of solder balls 205 are formed on one surface, and copper is formed on the other surface of the solder mask 204 to cover the through hole h2 on the outer portion covering the semiconductor chip 201. A metal foil 212 as a component is attached.

상기 구성을 갖는 본 발명의 칩규모의 반도체패키지의 제작과정을 알아본다.It looks at the manufacturing process of the chip-scale semiconductor package of the present invention having the above configuration.

먼저, 웨이퍼를 개별적인 칩단위로 쏘잉하여 패키징할 반도체칩(201)을 준비한다.First, a semiconductor chip 201 to be packaged is prepared by sawing wafers individually.

이 반도체칩(201) 상에는 도 4에서와 같이, 칩패드를 노출시키는 다 수개의 창(c)을 갖는 절연막(210)이 형성되어져 있으며, 이 절연막(210)에는 다 수개의 창(c)을 덮는 도전패턴(214)이 형성되어져 있다. 절연막(210)은 스트레스 완충막(SBL:Stress Buffer Layer) 역할을 하며, 재질로는 일레스토머(elastomer) 등이 사용된다.On this semiconductor chip 201, as shown in Fig. 4, an insulating film 210 having a plurality of windows c exposing the chip pads is formed, and the plurality of windows c are formed on the insulating film 210. A covering conductive pattern 214 is formed. The insulating layer 210 serves as a stress buffer layer (SBL), and an elastomer or the like is used as a material.

도 3 및 도 4와 같이, 솔더마스크(204)에는 다 수개의 관통홀(h2)이 패터닝되어져 있고, 이 후의 공정을 거쳐 솔더볼(205)이 형성되는 면의 이면에는 반도체칩(201)을 커버링하는 외곽 부위에 형성된 관통홀(h2)을 덮도록 구리포일(212)이 패터닝되어 부착되어져 있다.3 and 4, the plurality of through holes h2 are patterned in the solder mask 204, and the semiconductor chip 201 is covered on the back surface of the surface where the solder balls 205 are formed through the subsequent process. The copper foil 212 is patterned and attached to cover the through hole h2 formed in the outer portion.

이 때, 솔더마스크(204)의 young`s module은 1Gpa 정도로 강도가 높으며, 구리포일(212)은 접착성이 좋은 폴리머(polymer)가 사용되고 그 두께는 10㎛ 가량된다.At this time, the young`s module of the solder mask 204 has a high strength of about 1 Gpa, and the copper foil 212 has a good adhesive polymer and its thickness is about 10 μm.

도 5와 같이, 도전패턴(214)이 형성된 반도체칩(201)을 금속포일(212)을 포함한 솔더마스크(204)에 부착시킨다.As illustrated in FIG. 5, the semiconductor chip 201 having the conductive pattern 214 is attached to the solder mask 204 including the metal foil 212.

즉, 금속포일(212)과 도전패턴(214)을 일부 겹친 상태에서, 토치(torch)(230)를 이용하여 이 겹친 부위에 400℃ 이상의 온도를 가함으로써 결선된다.That is, in a state where the metal foil 212 and the conductive pattern 214 are partially overlapped, the torch 230 is connected by applying a temperature of 400 ° C. or higher to the overlapped portion.

도 6과 같이, 노즐(232)을 이용하여 도전패턴(214)을 포함하여 반도체칩(201)의 측면을 밀봉시키어 몰딩컴파운드(206)를 형성한다.As shown in FIG. 6, the molding compound 206 is formed by sealing the side surface of the semiconductor chip 201 including the conductive pattern 214 using the nozzle 232.

도 7과 같이, 솔더볼(205)을 솔더마스크(204)의 관통홀(h2)을 통해 노출된 금속포일(212) 표면에 플럭스(flux) 처리하고, 리플로우(reflow)하여 마운트(mount)시킨다.As shown in FIG. 7, the solder ball 205 is fluxed to the surface of the metal foil 212 exposed through the through hole h2 of the solder mask 204, and then reflowed and mounted. .

이 후, 솔더마스크(204)를 싱귤레이션(singulation)하여 낱개의 패키지단위로 분리한다.Thereafter, the solder mask 204 is singulated and separated into individual package units.

상술한 바와 같이, 본 발명의 칩규모의 반도체패키지에서는 리본본딩의 한계를 극복하여 미세 피치패드에 대응되도록 다핀화에 적합함에 따라, 반도체칩이 솔더볼 어레이보다 작아지는 경우에도 대응 가능하다.As described above, the chip-scale semiconductor package of the present invention is suitable for multipinning so as to overcome the limitation of ribbon bonding and correspond to the fine pitch pad, so that the semiconductor chip may be smaller than the solder ball array.

또한, 신뢰성에 가장 큰 문제가 되는 최외곽 솔더볼이 열팽창계수가 PCB에 가까운 솔더마스크에 붙어있기 때문에 높은 수준의 신뢰성을 갖는 잇점이 있다.In addition, since the outermost solder ball, which is the biggest problem of reliability, is attached to a solder mask close to the PCB, the thermal expansion coefficient has an advantage of having a high level of reliability.

Claims (4)

상면에 칩패드를 노출시키는 각각의 창이 패터닝된 절연막을 갖는 반도체칩과,A semiconductor chip having an insulating film patterned on each window for exposing the chip pads on an upper surface thereof; 상기 반도체칩을 커버링하며, 다 수개의 관통홀 및 솔더볼이 형성된 솔더마스크와,A solder mask covering the semiconductor chip and having a plurality of through holes and solder balls formed therein; 상기 솔더볼이 형성된 솔더마스크의 이면에 형성되며, 상기 반도체칩을 커버링하는 외곽 부위에 형성된 상기 관통홀을 덮는 금속포일과,A metal foil formed on a rear surface of the solder mask on which the solder ball is formed, and covering the through hole formed in an outer portion of the solder mask; 상기 솔더마스크와 상기 반도체칩 사이에 개재되며, 일측은 상기 절연막 상에서 각각의 창을 덮어 상기 칩패드와 연결되고 타측은 상기 금속포일과 결선되어 상기 외곽부위에 형성된 상기 관통홀을 통해 상기 솔더볼과 연결되는 도전패턴과,Interposed between the solder mask and the semiconductor chip, one side is connected to the chip pad by covering each window on the insulating film, and the other side is connected to the metal foil and connected to the solder ball through the through hole formed in the outer portion. Conductive patterns, 상기 도전패턴을 포함하여 상기 반도체칩의 측면을 밀봉시키는 몰딩컴파운드를 구비한 칩규모의 반도체패키지.A chip scale semiconductor package including a molding compound for sealing the side surface of the semiconductor chip including the conductive pattern. 청구항 1에 있어서,The method according to claim 1, 상기 금속포일은 구리성분이 이용된 것이 특징인 칩규모의 반도체패키지.The metal foil is a chip-scale semiconductor package, characterized in that the copper component is used. 청구항 1에 있어서,The method according to claim 1, 상기 절연막은 SBL(Stress Buffer Layer)로 일레스토머(elastomer) 재질인 것이 특징인 칩규모의 반도체패키지.The insulating film is a SBL (Stress Buffer Layer) is a chip-scale semiconductor package, characterized in that the elastomer (elastomer) material. 청구항 1에 있어서,The method according to claim 1, 상기 도전패턴은 토치(torch)에 의해 상기 금속포일과 결선된 것이 특징인 칩규모의 반도체패키지.The conductive pattern is a chip-scale semiconductor package, characterized in that connected to the metal foil by a torch (torch).
KR1019990050754A 1999-11-16 1999-11-16 Chip Scale Package KR20010046832A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7327032B2 (en) 2005-04-13 2008-02-05 Samsung Electronics Co., Ltd. Semiconductor package accomplishing fan-out structure through wire bonding

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7327032B2 (en) 2005-04-13 2008-02-05 Samsung Electronics Co., Ltd. Semiconductor package accomplishing fan-out structure through wire bonding
US7550830B2 (en) 2005-04-13 2009-06-23 Samsung Electronics Co., Ltd. Stacked semiconductor package having fan-out structure through wire bonding

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