KR20010019763A - Printed circuit board - Google Patents

Printed circuit board Download PDF

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Publication number
KR20010019763A
KR20010019763A KR1019990036347A KR19990036347A KR20010019763A KR 20010019763 A KR20010019763 A KR 20010019763A KR 1019990036347 A KR1019990036347 A KR 1019990036347A KR 19990036347 A KR19990036347 A KR 19990036347A KR 20010019763 A KR20010019763 A KR 20010019763A
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KR
South Korea
Prior art keywords
layer
printed circuit
circuit board
copper foil
wiring
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Application number
KR1019990036347A
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Korean (ko)
Inventor
설재천
Original Assignee
윤종용
삼성전자 주식회사
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Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1019990036347A priority Critical patent/KR20010019763A/en
Publication of KR20010019763A publication Critical patent/KR20010019763A/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE: A printed circuit board is provided to prevent from bending caused by irregular heat deformation between copper foils. CONSTITUTION: The printed circuit board(1) has a plurality of copper foils having wiring patterns for transmitting electrical signals. The copper foil has a printed wiring board(6) to mount the elements, and a copper pattern board having a dummy pattern corresponding to the mount area. The dummy patterns formed on the contacting board(7) and printed wiring board(6) provide the constant heat distension rate and block the irregular heat deformation.

Description

인쇄회로기판{PRINTED CIRCUIT BOARD}Printed Circuit Board {PRINTED CIRCUIT BOARD}

본 발명은 인쇄회로기판에 관한 것으로서, 보다 상세하게는, 복수의 층간의 동박의 양에 균형을 주어 열에 의한 변형을 감소시킬 수 있도록 하는 인쇄회로기판에 관한 것이다.The present invention relates to a printed circuit board, and more particularly, to a printed circuit board to balance the amount of copper foil between a plurality of layers to reduce the deformation caused by heat.

인쇄회로기판 중 다층 인쇄회로기판이나 빌드 인쇄회로기판은, 복수의 동박 패턴층을 가지며, 최상층에는 부품이 직접 실장되는 한층이나 두층 정도의 배선층이 형성되어 있고, 배선층의 하부에는 접지를 위한 접지층과, 전원신호를 인가하기 위한 전원층이 형성되어 있다.Among printed circuit boards, a multilayer printed circuit board or a build printed circuit board has a plurality of copper foil pattern layers, and one or two wiring layers on which the components are directly mounted are formed on the uppermost layer, and a ground layer for grounding is provided below the wiring layer. And a power supply layer for applying a power signal.

그리고, 이러한 다층 인쇄회로기판에는 배선층과 접지층, 배선층과 전원층 등 각 층간의 전기적 신호를 전달하기 위해 비아홀이 형성되어 있다. 비아홀은 인쇄회로기판의 제작공정중 동박에 배선패턴을 형성할 때 일체로 형성되며, 비아홀에는 금박으로 코팅되어 있다. 이러한 비아홀은 그 위치나 길이에 따라 브라인드(Blind) 비아홀, 3층 브라인드 비아홀, 드루(Through) 비아홀, 이너(Inner) 블라인드 비아홀 등으로 분류할 수 있다.In addition, via holes are formed in the multilayer printed circuit board to transmit electrical signals between respective layers such as a wiring layer, a ground layer, a wiring layer, and a power supply layer. The via holes are integrally formed when the wiring pattern is formed on the copper foil during the manufacturing process of the printed circuit board, and the via holes are coated with gold foil. Such via holes may be classified into a blind via hole, a three-layer blind via hole, a through via hole, an inner blind via hole, and the like, according to a location or a length thereof.

근래에는 인쇄회로기판을 고밀도 고집적화하기 위해 다층 인쇄회로기판의 사용이 증대되고 있으며, 다층 인쇄회로기판에는 층간의 신호 전달을 위해 비아홀은 이웃하는 층간의 신호뿐만 아니라, 이격된 층간의 신호를 전달하기 위해 단층분만 아니라 3층 블라인드 비아홀이나 드루 비아홀이 형성되기 때문에 인쇄회로기판의 휨이 쉽게 발생하게 된다.In recent years, the use of multilayer printed circuit boards has been increased for high density and high density of printed circuit boards. In order to transmit signals between layers, via-holes not only transmit signals between adjacent layers but also signals between spaced layers. For example, since three-layer blind via holes or draw via holes are formed as well as a single layer, warpage of a printed circuit board is easily generated.

한편, 이러한 다층 인쇄회로기판은 각 동박층간에 배선패턴이 상이하며, 특히, 도 3에 도시된 바와 같이, 부품이 실장되는 영역에서는 배선층(56)에는 복잡한 배선패턴이 형성되어 있는 경우라도, 전원층이나 접지층(57)에는 별도의 배선패턴이 형성되지 아니한 동박판이 형성되어 있는 경우가 많다. 이런 경우, 부품의 실장영역에서 배선패턴이 적은 접지층(57)이나 전원층은 열에 의한 변형이 크고, 배선패턴이 복잡한 배선층(56)에서는 열에 의한 변형이 작다. 따라서, 동박층마다 열변형량이 상이하기 때문에, 인쇄회로기판(51)에 부품 실장공정에서 바이메탈 현상이 발생하여 인쇄회로기판(51)의 열 변형이 심하게 발생한다. 이에 따라, 배선층(56)에 실장된 부품의 쇼트나 오픈불량이 발생할 염려가 있다.On the other hand, such multilayer printed circuit boards have different wiring patterns between the copper foil layers, and in particular, as shown in FIG. 3, even when a complicated wiring pattern is formed in the wiring layer 56 in a region where components are mounted, The layer or the ground layer 57 is often formed with a copper foil on which no separate wiring pattern is formed. In this case, the ground layer 57 or the power supply layer having a small wiring pattern in the component mounting area has a large deformation by heat, and the wiring layer 56 having a complicated wiring pattern has a small deformation by heat. Therefore, since the amount of thermal deformation is different for each copper foil layer, a bimetal phenomenon occurs in the component mounting process on the printed circuit board 51, and thermal deformation of the printed circuit board 51 occurs severely. Accordingly, there is a possibility that short or open defects of components mounted on the wiring layer 56 may occur.

특히, BGA(Ball grid array)패키지(55)나 리드를 패키지의 하면에 노출시킨 CSP(Chip Scale Package)등과 같이 다수의 접속접들을 가지는 부품의 경우에는, 각 동박층의 배선패턴 양의 상이함에 따라 인쇄회로기판(51)에 휨이 발생하게 되면, 다른 부품에 비해 쇼트나 오픈 등의 불량이 빈번하게 발생된다.In particular, in the case of a component having a plurality of connection contacts, such as a ball grid array (BGA) package 55 or a chip scale package (CSP) in which leads are exposed on the bottom surface of the package, the amount of wiring pattern of each copper foil layer is different. Accordingly, when the printed circuit board 51 is warped, defects such as shorting and opening are more frequently generated than other parts.

따라서 본 발명의 목적은, 부품이 실장되는 영역에서 동박층간의 열변형의 차에 따른 휨을 방지할 수 있도록 하는 인쇄회로기판을 제공하는 것이다.Accordingly, an object of the present invention is to provide a printed circuit board which can prevent warpage due to the difference in thermal deformation between copper foil layers in a region where a component is mounted.

도 1은 본 발명에 따른 인쇄회로기판의 단면도,1 is a cross-sectional view of a printed circuit board according to the present invention;

도 2는 도 1의 인쇄회로기판의 접지층의 더미패턴을 보인 평면도,2 is a plan view showing a dummy pattern of the ground layer of the printed circuit board of FIG. 1;

도 3은 종래의 인쇄회로기판의 단면도이다.3 is a cross-sectional view of a conventional printed circuit board.

<도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

1 : 인쇄회로기판 5 : BGA패키지1: printed circuit board 5: BGA package

6 : 배선층 7 : 접지층6: wiring layer 7: ground layer

10 : 더미패턴10: dummy pattern

상기 목적은, 본 발명에 따라, 상호 전기적 신호의 전달이 가능한 배선패턴이 형성된 복수의 동박층을 가지며, 조밀하게 배치된 다수의 접점을 갖는 부품이 실장되는 인쇄회로기판에 있어서, 상기 동박층은, 상기 부품이 실장되는 배선층과, 상기 배선층의 부품 실장영역에 대응되는 영역에 소정의 더미패턴이 형성된 동박패턴층을 포함하는 것을 특징으로 하는 인쇄회로기판에 의해 달성된다.The above object is, according to the present invention, a printed circuit board having a plurality of copper foil layer formed with a wiring pattern capable of transmitting electrical signals, and the component having a plurality of densely arranged contacts are mounted, the copper foil layer is And a copper foil pattern layer having a predetermined dummy pattern formed in a region corresponding to the component mounting region of the wiring layer.

여기서, 상기 동박패턴층은 상기 부품의 접지를 위한 접지층 또는 전원 공급을 위한 전원층인 것이 바람직하다.Here, the copper foil pattern layer is preferably a ground layer for grounding the component or a power layer for power supply.

이하, 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the drawings.

인쇄회로기판 중 다층 인쇄회로기판이나 빌드 인쇄회로기판은, 복수의 동박 패턴층을 가지며, 통상적으로 8층으로 형성된다.Among the printed circuit boards, a multilayer printed circuit board or a build printed circuit board has a plurality of copper foil pattern layers, and is usually formed of eight layers.

이러한 인쇄회로기판의 제작은 기본적으로 수십 미크론의 두께를 갖는 동박을 에폭시로 형성된 적층판에 접착시킨 다음, 레지스트를 도포하고, 노광 및 현상공정으로 소정의 배선패턴을 형성하여 배선층을 형성한다. 그리고, 에칭하여 불필요한 부분의 동박을 제거한 다음, 남은 레지스트를 용제나 알카리 용액으로 제거하게 되며, 배선패턴 형성시 비아홀도 동시에 형성하게 된다. 이렇게 배선패턴이 형성된 동박에 다시 절연막과 동박을 접착하고, 배선패턴의 레지스트를 프린트한 다음, 에칭하는 작업을 복수회 거쳐 복수의 또 다른 배선층이나 부품의 접지를 위한 접지층, 전원공급을 위한 전원층 등을 형성하여 다층의 배선기판(Printed Wiring Board:PWB)을 완성하게 된다.In the manufacture of such a printed circuit board, a copper foil having a thickness of several tens of microns is basically bonded to a laminate formed of epoxy, and then a resist is applied, and a wiring pattern is formed by forming a predetermined wiring pattern by an exposure and development process. Then, the copper foil of the unnecessary portion is removed by etching, and the remaining resist is removed with a solvent or an alkali solution, and via holes are simultaneously formed when the wiring pattern is formed. The insulating film and the copper foil are again bonded to the copper foil on which the wiring pattern is formed, the resist of the wiring pattern is printed, and then etched a plurality of times, and the ground layer for grounding a plurality of wiring layers or components, and a power supply for power supply. A layer or the like is formed to complete a multilayer printed wiring board (PWB).

이러한 배선기판은, 도 1에 도시된 바와 같이, 배선층(6)이나 접지층(7) 및 전원층 등 각 층에 형성된 배선패턴의 형상이 각각 상이하며, 배선층(6)의 부품이 실장되는 영역에는 배선패턴이 많이 형성되어 있고, 특히, BGA패키지(5)나 CSP 같은 부품이 실장되는 영역의 배선층(6)에는 복잡한 배선패턴이 형성되어 있다.As shown in FIG. 1, the wiring boards have different shapes of wiring patterns formed on the respective layers such as the wiring layer 6, the ground layer 7, and the power supply layer, and the components of the wiring layer 6 are mounted. Many wiring patterns are formed in the structure, and in particular, complicated wiring patterns are formed in the wiring layer 6 in a region where components such as the BGA package 5 and the CSP are mounted.

그리고, 이러한 BGA패키지(5)나 CSP 같은 부품이 실장되는 배선층(6)의 영역에 대응하는 접지층(7)이나 전원층의 영역에는, 배선층(6)의 배선패턴 양에 대응하여 동박판에 소정의 더미패턴(10)이 형성되어 있다. 이 더미패턴(10)은, 도 2에 도시된 바와 같이, 바둑판 형상으로 형성할 수도 있고, 비아홀이나 다른 동박층과의 신호연결을 고려하여 적절한 패턴으로 형성할 수도 있다.Then, in the area of the ground layer 7 or the power supply layer corresponding to the area of the wiring layer 6 on which the components such as the BGA package 5 and the CSP are mounted, the copper foil sheet is applied to the amount of the wiring pattern of the wiring layer 6. A predetermined dummy pattern 10 is formed. As shown in FIG. 2, the dummy pattern 10 may be formed in a checkerboard shape or may be formed in an appropriate pattern in consideration of signal connection with a via hole or another copper foil layer.

이러한 배선기판(1)에 부품이 실장되어 인쇄회로기판(1)이 완성되며, 부품 실장공정은 배선기판(1)에 솔더크림을 인쇄하는 과정, 각 실장위치에 부품을 안착시키는 과정, 예열존과 가열존 및 냉각존을 통과시키는 과정으로 이루어진다. 한편, 부품이 실장된 영역의 배선층(6)과, 접지층(7)이나 전원층에 형성된 더미패턴(10)에 의해 동박의 양이 거의 동일해지므로, 부품의 실장과정 중 인쇄회로기판(1)에 열이 가해지더라도 각 동박층의 열 팽창량이 균일해지게 되어 종래와 같은 바이메탈 현상을 방지할 수 있게 된다.The components are mounted on the wiring board 1 to complete the printed circuit board 1, and the component mounting process is a process of printing a solder cream on the wiring board 1, a process of seating components at each mounting position, and a preheating zone. And a process of passing the heating zone and the cooling zone. On the other hand, since the amount of copper foil becomes substantially the same by the wiring layer 6 in the region where the component is mounted and the dummy pattern 10 formed in the ground layer 7 or the power supply layer, the printed circuit board 1 Even if heat is applied), the amount of thermal expansion of each copper foil layer becomes uniform, thereby preventing the conventional bimetal phenomenon.

이와 같이, 본 발명에서는, 배선층(6)의 부품이 실장되는 영역과, 부품실장 영역에 대응하는 접지층(7) 및 전원층의 동박에 더미패턴(10)을 형성함으로써, 각 동박층 간의 배선패턴의 양을 거의 동일하게 형성하여 열에 의한 팽창량을 거의 균일하게 한다. 이에 따라, 각 동박층의 열 팽창량의 불균일에 의한 인쇄회로기판(1)의 휨을 방지할 수 있게 된다.Thus, in this invention, the dummy pattern 10 is formed in the copper foil of the ground layer 7 and the power supply layer which correspond to the component mounting area | region, the component mounting area | region, and the wiring between each copper foil layer is formed. The amount of the pattern is formed to be almost equal to make the amount of expansion due to heat almost uniform. Thereby, the curvature of the printed circuit board 1 by the nonuniformity of the thermal expansion amount of each copper foil layer can be prevented.

이상에서 설명한 바와 같이, 본 발명에 따르면, 부품이 실장되는 영역에서 각 동박층간의 열 팽창량이 균일해짐으로써, 인쇄회로기판의 휨을 방지할 수 있게 된다.As described above, according to the present invention, the amount of thermal expansion between the copper foil layers becomes uniform in the region where the component is mounted, thereby preventing warpage of the printed circuit board.

Claims (3)

상호 전기적 신호의 전달이 가능한 배선패턴이 형성된 복수의 동박층을 가지며, 조밀하게 배치된 다수의 접점을 갖는 부품이 실장되는 인쇄회로기판에 있어서,In a printed circuit board having a plurality of copper foil layer formed with a wiring pattern capable of transmitting electrical signals to each other, and a component having a plurality of densely arranged contacts are mounted, 상기 동박층은,The copper foil layer, 상기 부품이 실장되는 배선층과,A wiring layer on which the component is mounted; 상기 배선층의 부품 실장영역에 대응되는 영역에 소정의 더미패턴이 형성된 동박패턴층을 포함하는 것을 특징으로 하는 인쇄회로기판.And a copper foil pattern layer having a predetermined dummy pattern formed in a region corresponding to the component mounting region of the wiring layer. 제 1 항에 있어서,The method of claim 1, 상기 동박패턴층은 상기 부품의 접지를 위한 접지층인 것을 특징으로 하는 인쇄회로기판.The copper foil pattern layer is a printed circuit board, characterized in that the ground layer for the ground of the component. 제 1 항에 있어서,The method of claim 1, 상기 동박패턴층은 전원 공급을 위한 전원층인 것을 특징으로 하는 인쇄회로기판.The copper foil pattern layer is a printed circuit board, characterized in that the power supply layer for power supply.
KR1019990036347A 1999-08-30 1999-08-30 Printed circuit board KR20010019763A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100744140B1 (en) 2006-07-13 2007-08-01 삼성전자주식회사 Printed circuit board having dummy pattern
US10002822B2 (en) 2015-06-24 2018-06-19 Samsung Electronics Co., Ltd. Circuit boards and semiconductor packages including the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50104961U (en) * 1974-02-01 1975-08-29
JPS51100853U (en) * 1975-02-10 1976-08-13
JPS53146956U (en) * 1977-04-26 1978-11-18
JPS547369U (en) * 1977-06-20 1979-01-18
JPS5989577U (en) * 1982-12-06 1984-06-18 三菱電機株式会社 Circuit board warpage prevention device
KR19980068062U (en) * 1997-05-30 1998-12-05 엄길용 Twist-resistant printed circuit board

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50104961U (en) * 1974-02-01 1975-08-29
JPS51100853U (en) * 1975-02-10 1976-08-13
JPS53146956U (en) * 1977-04-26 1978-11-18
JPS547369U (en) * 1977-06-20 1979-01-18
JPS5989577U (en) * 1982-12-06 1984-06-18 三菱電機株式会社 Circuit board warpage prevention device
KR19980068062U (en) * 1997-05-30 1998-12-05 엄길용 Twist-resistant printed circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100744140B1 (en) 2006-07-13 2007-08-01 삼성전자주식회사 Printed circuit board having dummy pattern
US10002822B2 (en) 2015-06-24 2018-06-19 Samsung Electronics Co., Ltd. Circuit boards and semiconductor packages including the same
US10141255B2 (en) 2015-06-24 2018-11-27 Samsung Electronics Co., Ltd. Circuit boards and semiconductor packages including the same

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