KR20010008582A - Method For Trement High Temperature Of Wafer - Google Patents
Method For Trement High Temperature Of Wafer Download PDFInfo
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- KR20010008582A KR20010008582A KR1019990026499A KR19990026499A KR20010008582A KR 20010008582 A KR20010008582 A KR 20010008582A KR 1019990026499 A KR1019990026499 A KR 1019990026499A KR 19990026499 A KR19990026499 A KR 19990026499A KR 20010008582 A KR20010008582 A KR 20010008582A
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- Prior art keywords
- wafer
- heat treatment
- high temperature
- temperature
- seconds
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000007789 gas Substances 0.000 claims abstract description 13
- 230000007547 defect Effects 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims description 25
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 238000002156 mixing Methods 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 8
- 238000005247 gettering Methods 0.000 abstract description 7
- 238000000137 annealing Methods 0.000 abstract description 5
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 19
- 238000011109 contamination Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
본 발명은 웨이퍼를 고온으로 열처리하는 방법에 관한 것으로서, 특히, 웨이퍼의 표면에 급속열처리 어닐링공정으로 열처리 부위를 형성한 후, 반도체소자 제조공정에서 발생하는 물순물 혹은 오염을 제어하도록 하는 웨이퍼의 고온 열처리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of heat-treating a wafer at a high temperature. In particular, after forming a heat treatment portion on a surface of a wafer by a rapid heat-treatment annealing process, the high temperature of the wafer to control water impurities or contamination generated in a semiconductor device manufacturing process. It relates to a heat treatment method.
일반적으로, 웨이퍼는 규소를 얇은 박판으로 형성한 것으로서, 규소(Si)를 고순도로 정제하여 결정시킨 후에 얇게 잘라내어서 반도체소자를 만드는 기본재료로 사용하게 된다. 웨이퍼는 통상적으로 여러 가지의 반도체 공정을 통하여 상부면에 무수한 패턴을 형성하고, 이 패턴이 형성된 칩들을 어떤 문자등을 저장할 수 있는 메모리소자나 연산을 수행하는 연산용소자, 컨트롤소자등으로 형성한다.In general, a wafer is formed of a thin thin plate of silicon, and is used as a base material for making a semiconductor device by thinly cutting silicon (Si) after crystallization with high purity. Wafers typically form a myriad of patterns on the upper surface through various semiconductor processes, and the chips on which the patterns are formed are formed into memory elements capable of storing certain characters, computing elements performing calculations, and control elements. .
한편, 현재 사용중인 웨이퍼의 경우, 침입산소 농도(Interstitial Oxygen Content)가 12 ∼ 15ppma 정도 이며, 소자 생성시 받는 열처리 공정으로 웨이퍼 내부에 있던 산소가 치환형자리로 바꿈하거나, 치환형 자리(Substition Site)로 변형되거나, 내부에서 뭉쳐 BMD(Bulk Micro Defect)로 전이될 수 있으며, 웨이퍼의 표면에서는 확산(Out-Diffusion)되어 표면 부위의 결함을 유발하는 문제를 지닌다.On the other hand, the wafer currently in use has an interstitial oxygen content of about 12 to 15 ppma, and the oxygen inside the wafer is replaced with a substitution site or a substitution site by a heat treatment process during device generation. ), Or agglomerated inwardly and transferred to BMD (Bulk Micro Defect), and the surface of the wafer is out-diffused to cause defects on the surface area.
그리고, 결함의 발생중에서 내부에 BMD형태로 전이되는 경우, 아이지 사이트(IG Site; Intrinsic Gettering Site)를 형성하여 불순물 게더링(Impurity Gettering) 효과를 가질 수 있다.In addition, when a defect is transferred to a BMD form therein, an IG site (IG Site; Intrinsic Gettering Site) may be formed to have an impurity gettering effect.
그러나, 너무나 많은 산소 함유량의 변화가 발생하는 경우, 웨이퍼의 표면에 까지 BMD가 전이하여 표면피트(Surface Pit)성 결함으로 발전될 수 있으며, 이 결함은 게이트 씨닝(Gate Thinning) 및 국부적인 스트레스(Stress)를 강화시켜 전압강하 현상(Yield Drop)을 유발하여 소자의 전기적인 특성을 저하시키는 문제점을 지닌다.However, if too much change in oxygen content occurs, BMD can be transferred to the surface of the wafer and developed into surface pit defects, which are gate thinning and local stress ( Stress is enhanced to cause a voltage drop phenomenon (Yield Drop) has a problem of lowering the electrical characteristics of the device.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 웨이퍼의 표면에 급속열처리 어닐링공정으로 열처리 부위를 형성한 후 반도체소자 제조공정에서 발생하는 불순물 혹은 오염을 제어하도록 하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and an object thereof is to control impurities or contamination generated in a semiconductor device manufacturing process after forming a heat treatment site on a surface of a wafer by a rapid thermal annealing process.
도 1은 본 발명에 따른 열처리방법으로 웨이퍼를고온 열처리하는 상태를 도시하고 있다.1 shows a state in which the wafer is subjected to a high temperature heat treatment by the heat treatment method according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 웨이퍼 20 : 아이지 부위10 wafer 20 eye area
이러한 목적은 반도체소자의 칩을 형성하는 웨이퍼에서, 상기 웨이퍼를 급속열처리 어닐링(Rapid Thermal Process Annealing)공정으로 표면 결함(Surface Defect)을 줄이도록 아이지 부위(IG Site : Intrinsic Gettering Site)를 형성하는 웨이퍼의 고온 열처리 방법을 제공함으로써 달성된다.The purpose is to form an IG site (Intrinsic Gettering Site) in a wafer forming a chip of a semiconductor device to reduce surface defects by a rapid thermal process annealing process. It is achieved by providing a high temperature heat treatment method.
그리고, 상기 급속열처리 온도는 1000 ∼ 1300℃ 범위에서, 20초 ∼ 1800초 동안 진행하는 것이 바람직하다.And, the rapid heat treatment temperature is preferably in the range of 1000 ~ 1300 ℃, 20 seconds to 1800 seconds.
상기 급속열처리 공정의 승온비(Ramp-Up Rate)는 100 ∼ 2000℃/sec이고, 사용가스는 N2및 O2가스인 것이 바람직 하다.It is preferable that the ramp-up rate of the rapid heat treatment process is 100 to 2000 ° C / sec, and the gas used is N 2 and O 2 gas.
상기 사용 가스의 N2: O2의 혼합비율은 1 : 0.03 ∼ 0.15 인 것이 바람직하다.N 2 of the gas used: the mixing ratio of O 2 is 1: preferably from 0.03 ~ 0.15.
이하, 첨부한 도면에 의거하여 본 발명에 바람직한 일실시예에 대하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 열처리방법으로 웨이퍼를 고온 열처리하는 상태를 도시하고 있다.1 shows a state in which the wafer is subjected to a high temperature heat treatment by the heat treatment method according to the present invention.
본 발명에 따른 열처리 방법을 살펴 보면, 도 1 에 도시된 바와 같이, 반도체소자의 칩을 형성하는 웨이퍼에서, 상기 웨이퍼(10)를 급속열처리 어닐링공정으로 표면 결함을 줄이도록 아이지 부위(20)를 형성하는상태를 도시하고 있다.Looking at the heat treatment method according to the present invention, as shown in Figure 1, in the wafer forming the chip of the semiconductor device, the ionic region 20 to reduce the surface defects by the rapid thermal annealing process the wafer 10 The forming state is shown.
상기 급속열처리 온도는 1000 ∼ 1300℃ 범위에서, 20초 ∼ 1800초 동안 진행하는 것이 바람직 하다.The rapid heat treatment temperature is preferably in the range of 1000 to 1300 ℃, 20 seconds to 1800 seconds.
이 때, 1800초 이상으로 열처리 하는 경우, BMD가 니얼 써얼피스(Near Surface)까지 침투하여 소자 특성의 열화가 나타날 수 있다.At this time, when the heat treatment for 1800 seconds or more, BMD penetrates to the near surface (Near Surface) may deteriorate device characteristics.
한편, 고온 열처리 온도 및 시간도 중요한 변수 이지만 램업시, 받을 수 있는 써멀 버젯(Thermal Budget) 역시 산소의 침전(Oxygen Precipitation)을 유발할 수 있는 요인이다.On the other hand, high temperature heat treatment temperature and time is also an important variable, but the thermal budget that can be received during the RAM (Thermal Budget) is also a factor that can cause oxygen precipitation (Oxygen Precipitation).
그리고, 상기 급속열처리 공정의 승온비는 100 ∼ 2000℃/sec이고, 사용가스는 N2및 O2가스인 것이 바람직 하다.The temperature increase ratio of the rapid heat treatment step is preferably 100 to 2000 ° C / sec, and the use gas is N 2 and O 2 gas.
상기 사용 가스의 N2: O2의 혼합비율은 1 : 0.03 ∼ 0.15 인 것이 바람직하다.N 2 of the gas used: the mixing ratio of O 2 is 1: preferably from 0.03 ~ 0.15.
이 때, 상기 N2및 O2의 혼합가스 사용시, 로우 산소(Low O2)를 첨가하는 것이 바람직 하다.At this time, when using the mixed gas of N 2 and O 2 , it is preferable to add low oxygen (Low O 2 ).
상기 아이지 부위(20)는 웨이퍼(10)의 표면 근방 아래쪽 10 ∼ 150㎛의 깊이(Depth)에 디누디드 존(DZ; Denuded Zone)을 형성하여 만들게 된다. 그리고, 아이지 부위(20)는 불순물을 게더링함과 동시에 써얼피스 및 니얼 써얼피스 부근의 BMD결함의 발생을 억제하고, COP(Crystal Originated Partical)를 감소시키게 된다.The eye area 20 is formed by forming a denuded zone (DZ) at a depth of 10 to 150 μm below the surface of the wafer 10. In addition, the eye area 20 gathers impurities and suppresses the occurrence of BMD defects in the vicinity of the earpiece and the nial earpiece, and reduces the COP (Crystal Originated Partical).
따라서, 본 발명에 따른 웨이퍼의 고온 열처리 방법을 이용하게 되면, 웨이퍼의 표면에 급속열처리 어닐링공정으로 열처리 부위를 형성한 후 반도체소자 제조공저에서 발생하는 물순물 혹은 오염을 제어하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, when the high temperature heat treatment method of the wafer according to the present invention is used, it is very useful and effective to control the water impurities or contamination generated in the semiconductor device manufacturing process after forming the heat treatment site on the surface of the wafer by the rapid heat treatment annealing process. Invention.
즉, 반도소자의 전압 강하에 영향을 미치는 결함의 감소(Reduction) 및 불순 물의 게더링(Impurity Gettering)을 강화하여 반도체소자의 수율을 증가시키도록 하는 장점을 지닌다.That is, it has the advantage of increasing the yield of the semiconductor device by reducing the defect (Induction) and impurity gettering (impurity gettering) affecting the voltage drop of the semiconductor device.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990026499A KR20010008582A (en) | 1999-07-02 | 1999-07-02 | Method For Trement High Temperature Of Wafer |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990026499A KR20010008582A (en) | 1999-07-02 | 1999-07-02 | Method For Trement High Temperature Of Wafer |
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| KR20010008582A true KR20010008582A (en) | 2001-02-05 |
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| KR1019990026499A KR20010008582A (en) | 1999-07-02 | 1999-07-02 | Method For Trement High Temperature Of Wafer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100777570B1 (en) * | 2006-11-21 | 2007-11-16 | 동부일렉트로닉스 주식회사 | Contamination detecting apparatus in rapid thermal process chamber |
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1999
- 1999-07-02 KR KR1019990026499A patent/KR20010008582A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100777570B1 (en) * | 2006-11-21 | 2007-11-16 | 동부일렉트로닉스 주식회사 | Contamination detecting apparatus in rapid thermal process chamber |
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