KR20010003468A - method of forming overlay measurement pattern for semiconductor device - Google Patents
method of forming overlay measurement pattern for semiconductor device Download PDFInfo
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- KR20010003468A KR20010003468A KR1019990023765A KR19990023765A KR20010003468A KR 20010003468 A KR20010003468 A KR 20010003468A KR 1019990023765 A KR1019990023765 A KR 1019990023765A KR 19990023765 A KR19990023765 A KR 19990023765A KR 20010003468 A KR20010003468 A KR 20010003468A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
본 발명은 반도체 소자의 오버레이 측정패턴 형성방법에 관한 것으로, 특히 오버레이 정확도(overlay accuracy)를 향상시킬 수 있는 반도체 소자의 오버레이 측정패턴 형성방법에 관한 것이다.The present invention relates to a method for forming an overlay measurement pattern of a semiconductor device, and more particularly, to a method for forming an overlay measurement pattern of a semiconductor device capable of improving overlay accuracy.
오버레이 정확도란 디바이스의 프로세스 스텝의 진행시 전(前)스텝 및 현(現)스텝간의 정렬상태를 나타내는 지수로서 마스크 제작시 발생하는 에러와 디바이스의 프로세스 및 시스템 에러에 의해 영향을 받는다. 이러한 오버레이 정확도를 측정하기 위하여, 다이(die) 사이를 분할하는 스크라이브 라인(scribe line) 내에 버니어(vernier)와 같은 오버레이 측정패턴을 형성한다. 일반적으로 오버레이 측정패턴은 전스텝에서 형성된 외부박스와 현스텝에서 형성된 내부박스로 이루어진다.The overlay accuracy is an index indicating the alignment state between the previous step and the current step in the progress of the process step of the device. The overlay accuracy is influenced by the error occurring during the manufacture of the mask and the process and system errors of the device. To measure this overlay accuracy, an overlay measurement pattern, such as a vernier, is formed in a scribe line that divides between dies. In general, the overlay measurement pattern includes an outer box formed in the previous step and an inner box formed in the current step.
도 1a 내지 도 1e는 종래의 반도체 소자의 오버레이 측정패턴 형성방법을 설명하기 위한 단면도이다.1A to 1E are cross-sectional views illustrating a method for forming an overlay measurement pattern of a conventional semiconductor device.
도 1a를 참조하면, 반도체 기판(10)의 스크라이브 라인 상에 산화막을 증착하고 패터닝하여 산화막 패턴(11)을 형성하고, 도 1b에 도시된 바와 같이, 기판 전면에 폴리실리콘막(12)을 형성한다. 그런 다음, 폴리실리콘막(12)의 전면 식각하여 도 1c에 도시된 바와 같이 산화막 패턴(11)의 측벽에 외부박스(12A)를 형성한다.Referring to FIG. 1A, an oxide layer 11 is formed by depositing and patterning an oxide layer on a scribe line of the semiconductor substrate 10, and as shown in FIG. 1B, a polysilicon layer 12 is formed on the entire surface of the substrate. do. Then, the entire surface of the polysilicon layer 12 is etched to form the outer box 12A on the sidewall of the oxide layer pattern 11 as shown in FIG. 1C.
도 1d에 도시된 바와 같이, 기판 전면에 산화막(13)을 증착하고, 외부박스(12A) 중앙의 산화막(13) 상부에 포토레지스트막을 도포하고 노광 및 현상하여 내부박스(14)로서 포토레지스트 패턴을 형성한다.As shown in FIG. 1D, an oxide film 13 is deposited on the entire surface of the substrate, and a photoresist film is coated on the oxide film 13 in the center of the outer box 12A, and exposed and developed to expose the photoresist pattern as the inner box 14. To form.
한편, 도 2는 상기한 오버레이 측정패턴을 나타낸 평면도로서, 도 2에 도시된 바와 같이, 외부박스(12A)와 내부박스(14) 사이의 수평거리(X1, X2) 및 수직거리 (Y1, Y1)를 이용하여 오버레이 정확도를 측정한다.2 is a plan view illustrating the overlay measurement pattern described above. As shown in FIG. 2, the horizontal distances X1 and X2 and the vertical distances Y1 and Y1 between the outer box 12A and the inner box 14 are illustrated. ) To measure overlay accuracy.
그러나, 전면식각에 의해 외부박스(11)의 손상이 야기되어 프로파일이 균일하지 못하기 때문에 오버레이 측정 장비의 측정오차가 증폭되어 오버레이 불량을 유발하여 재작업 회수 및 검사시간이 증가됨으로써, 생산성이 저하될 뿐만 아니라 수율 및 신뢰성이 저하된다.However, due to the entire surface etching, damage to the outer box 11 is caused, and thus the profile is not uniform. Thus, the measurement error of the overlay measuring equipment is amplified to cause the overlay failure, thereby increasing the number of rework and inspection time, thereby reducing productivity. As well as lower yield and reliability.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 전면식각 후 오버레이 정확도를 향상시킬 수 있는 반도체 소자의 오버레이 측정패턴 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming an overlay measurement pattern of a semiconductor device capable of improving overlay accuracy after front etching.
도 1a 내지 도 1e는 종래의 반도체 소자의 오버레이 측정패턴 형성방법을 설명하기 위한 단면도.1A to 1E are cross-sectional views illustrating a method for forming an overlay measurement pattern of a conventional semiconductor device.
도 2는 종래의 반도체 소자의 오버레이 측정패턴을 나타낸 평면도.2 is a plan view showing an overlay measurement pattern of a conventional semiconductor device.
도 3a 내지 도 3f는 본 발명의 실시예에 따른 반도체 소자의 오버레이 측정패턴 형성방법을 설명하기 위한 단면도.3A to 3F are cross-sectional views illustrating a method for forming an overlay measurement pattern of a semiconductor device in accordance with an embodiment of the present invention.
도 4는 본 발명의 실시예에 따른 반도체 소자의 오버레이 측정패턴을 나타낸 평면도.4 is a plan view showing an overlay measurement pattern of a semiconductor device according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
30 : 반도체 기판 31 : 산화막 패턴30 semiconductor substrate 31 oxide film pattern
32 : 폴리실리콘막 32A : 외부박스32: polysilicon film 32A: outer box
33 : 산화막 34 : 내부박스33: oxide film 34: inner box
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라, 다이와 다이사이를 분할하는 스크라이브 라인을 구비한 반도체 기판을 제공하고, 반도체 기판 전면에 제 1 막을 형성한다. 그런 다음, 제 1 막 상에 스크라이브 라인 상의 제 1 막을 마스킹하는 포토레지스트 패턴을 형성하고, 다이의 제 1 막을 전면식각한다. 그런 다음, 포토레지스트 패턴을 제거하여 스크라이브 라인 상의 제 1 막을 노출시켜 외부박스를 형성하고, 기판 전면에 제 2 막을 형성한 후, 외부박스 내의 제 2 막 상에 포토레지스트 패턴으로 이루어진 내부박스를 형성한다.In order to achieve the above object of the present invention, according to the present invention, a semiconductor substrate having a scribe line for dividing between a die and a die is provided, and a first film is formed on the entire surface of the semiconductor substrate. A photoresist pattern is then formed on the first film to mask the first film on the scribe line, and the first film of the die is etched. Then, the photoresist pattern is removed to expose the first film on the scribe line to form an outer box, the second film is formed on the entire surface of the substrate, and then the inner box of the photoresist pattern is formed on the second film in the outer box. do.
본 실시예에서, 제 1 막은 포토레지스트막이고, 제 2 막은 산화막이다.In this embodiment, the first film is a photoresist film and the second film is an oxide film.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 3a 및 도 3f는 본 발명의 실시예에 따른 반도체 소자의 오버레이 측정패턴 형성방법을 설명하기 위한 단면도이다.3A and 3F are cross-sectional views illustrating a method for forming an overlay measurement pattern of a semiconductor device according to an embodiment of the present invention.
도 3a를 참조하면, 반도체 기판(30)의 스크라이브 라인 상에 산화막을 증착하고 패터닝하여 산화막 패턴(31)을 형성하고, 도 3b에 도시된 바와 같이, 기판 전면에 폴리실리콘막(32)을 형성한다. 그리고 나서, 도 3c에 도시된 바와 같이, 기판(30) 전면에 포토레지스트막을 도포하고 노광 및 현상하여 스크라이브 라인을 마스킹하는 제 1 포토레지스트 패턴(33)을 형성한다.Referring to FIG. 3A, an oxide layer 31 is formed by depositing and patterning an oxide layer on a scribe line of the semiconductor substrate 30, and as shown in FIG. 3B, a polysilicon layer 32 is formed on the entire surface of the substrate. do. Then, as shown in FIG. 3C, a photoresist film is coated on the entire surface of the substrate 30, and exposed and developed to form a first photoresist pattern 33 for masking a scribe line.
그런 다음, 기판(30)의 셀 영역(미도시)에서 노출된 폴리실리콘막(32)을 전면 식각한 후, 도 3d에 도시된 바와 같이, 제 1 포토레지스트 패턴(33)을 제거하여 스크라이브 라인 상의 폴리실리콘막(32)을 노출시킨다. 즉, 노출된 폴리실리콘막 (32)이 외부박스(32A)가 되는데, 전면식각시 외부박스(32A)가 제 1 포토레지스트 패턴(33)에 의해 보호되기 때문에, 외부박스(32A)의 프로파일이 균일하다.Then, the entire surface of the polysilicon film 32 exposed in the cell region (not shown) of the substrate 30 is etched, and as shown in FIG. 3D, the first photoresist pattern 33 is removed to scribe lines. The polysilicon film 32 on the top is exposed. That is, the exposed polysilicon film 32 becomes the outer box 32A. Since the outer box 32A is protected by the first photoresist pattern 33 during front etching, the profile of the outer box 32A is Uniform
도 3e를 참조하면, 기판 전면에 산화막(33)을 증착하고, 산화막(33) 상부에 포토레지스트막을 도포하고 노광 및 현상하여, 도 3f에 도시된 바와 같이, 외부박스(32A)의 중앙에 내부박스(34)로서 제 2 포토레지스트 패턴을 형성한다.Referring to FIG. 3E, an oxide film 33 is deposited on the entire surface of the substrate, a photoresist film is coated on the oxide film 33, and exposed and developed, and as shown in FIG. 3F, the inside of the outer box 32A is located in the center of the outer box 32A. A second photoresist pattern is formed as the box 34.
한편, 도 4는 상기한 오버레이 측정패턴을 나타낸 평면도로서, 도 4에 도시된 바와 같이, 외부박스(32A)와 내부박스(34) 사이의 수평거리(X1, X2) 및 수직거리 (Y1, Y1)를 이용하여 오버레이 정확도를 측정한다.4 is a plan view illustrating the above-described overlay measurement pattern. As shown in FIG. 4, horizontal distances X1 and X2 and vertical distances Y1 and Y1 between the outer box 32A and the inner box 34 are illustrated. ) To measure overlay accuracy.
상기한 본 발명에 의하면, 전면식각시 외부박스가 포토레지스트 패턴에 의해 보호되기 때문에, 전면식각에 의한 외부박스의 손상이 방지되어 프로파일이 균일하다. 이에 따라, 전면식각 후 오버레이 측정 장비의 측정오차가 제거되어 오버레이 정확도가 향상됨으로써 생산성이 증가될 뿐만 아니라 소자의 수율 및 신뢰성이 향상된다.According to the present invention described above, since the outer box is protected by the photoresist pattern during the front etching, damage to the outer box by the front etching is prevented and the profile is uniform. Accordingly, the measurement error of the overlay measuring equipment after the front etching is eliminated to improve the overlay accuracy, thereby increasing productivity and improving the yield and reliability of the device.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
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|---|---|---|---|
| KR1019990023765A KR20010003468A (en) | 1999-06-23 | 1999-06-23 | method of forming overlay measurement pattern for semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990023765A KR20010003468A (en) | 1999-06-23 | 1999-06-23 | method of forming overlay measurement pattern for semiconductor device |
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| KR1019990023765A KR20010003468A (en) | 1999-06-23 | 1999-06-23 | method of forming overlay measurement pattern for semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100915064B1 (en) * | 2007-09-28 | 2009-09-02 | 주식회사 하이닉스반도체 | Overlay vernier and method for forming the same |
| CN109817516A (en) * | 2017-11-21 | 2019-05-28 | 三星电子株式会社 | Semiconductor device with overlapping pattern |
-
1999
- 1999-06-23 KR KR1019990023765A patent/KR20010003468A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100915064B1 (en) * | 2007-09-28 | 2009-09-02 | 주식회사 하이닉스반도체 | Overlay vernier and method for forming the same |
| CN109817516A (en) * | 2017-11-21 | 2019-05-28 | 三星电子株式会社 | Semiconductor device with overlapping pattern |
| CN109817516B (en) * | 2017-11-21 | 2024-02-02 | 三星电子株式会社 | Semiconductor device with overlapped pattern |
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