KR20000073749A - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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Publication number
KR20000073749A
KR20000073749A KR1019990017220A KR19990017220A KR20000073749A KR 20000073749 A KR20000073749 A KR 20000073749A KR 1019990017220 A KR1019990017220 A KR 1019990017220A KR 19990017220 A KR19990017220 A KR 19990017220A KR 20000073749 A KR20000073749 A KR 20000073749A
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South Korea
Prior art keywords
gas
etching
insulating layer
polysilicon
photoresist
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KR1019990017220A
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Korean (ko)
Inventor
이재봉
이현철
이혁준
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윤종용
삼성전자 주식회사
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Priority to KR1019990017220A priority Critical patent/KR20000073749A/en
Publication of KR20000073749A publication Critical patent/KR20000073749A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve productivity of the semiconductor device, by minimizing a step difference between a cell region and a periphery without a planarization process. CONSTITUTION: An insulating layer is formed on a substrate(50), and the insulating layer is patterned to form a contact hole(58) on the substrate. Polysilicon is stacked on the insulating layer and contact hole to form a polysilicon layer. After photoresist is applied on the polysilicon layer, the photoresist is patterned by a photolithography method to form a photoresist pattern on the polysilicon layer. A storage electrode(70) is formed by etching an inside of a cell of the polysilicon layer vertically and by etching a side of a periphery slantingly with a mixture gas composed of HBr, Cl2, He, and O2 gas, using the photoresist pattern as an etching mask. A dielectric layer and a plate electrode are sequentially formed on the storage electrode.

Description

반도체 장치의 제조방법{METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 장치의 제조방법에 관한 것으로서, 보다 상세하게는 반도체 장치의 셀 영역과 주변부와의 단차를 최소화하여 평탄화 공정을 단순화시킬 수 있는 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device, which can simplify a planarization process by minimizing a step difference between a cell region and a peripheral portion of a semiconductor device.

반도체 장치의 제조공정이 서브마이크론(sub-micron) 레벨로 진행됨에 따라 가공치수가 미세화하여 0.4㎛ 이하 레벨의 패턴 가공이 필요하게 되었다. 따라서, 높은 식각선택비와 미세 선폭 제어 등의 요구가 강조되고 있다. 이에 따라, 수직 프로파일(profile)을 형성하는 이방성 건식식각 방식이 식각공정의 대다수를 차지하게 되었으며, 수직 프로파일에 대한 요구는 회로선폭길이(design rule)의 감소와 더불어 그 정도가 더욱 강해지고 있는 추세이다.As the manufacturing process of the semiconductor device proceeds to the sub-micron level, the processing dimension becomes finer, and pattern processing of 0.4 mu m or less level is required. Therefore, demand for high etching selectivity, fine line width control, and the like is emphasized. Accordingly, the anisotropic dry etching method that forms the vertical profile occupies the majority of the etching process, and the demand for the vertical profile is increasing with the decrease of the design rule. to be.

이와 같이 수직 프로파일이 요구되는 이유는 고집적화에 따른 해상성능의 향상을 도모하기 위한 것이다. 존재해야하는 패턴의 결손, 불필요한 패턴의 출현은 디바이스의 특성을 손상하는 큰 요인이다. 따라서, 본질적으로 결함을 일으킬 가능성이 있는 사진식각공정은 개선되어야만 한다.The reason why the vertical profile is required is to improve the resolution performance due to high integration. The lack of patterns that need to be present, the appearance of unnecessary patterns is a major factor impairing the characteristics of the device. Therefore, the photolithography process, which is inherently likely to cause defects, must be improved.

한편, 상기와 같이 수직한 프로파일을 갖는 건식식각 방식을 연구함과 동시에 반도체 장치의 평탄도를 향상시키기 위한 연구도 활발히 진행되어지고 있다.On the other hand, while researching a dry etching method having a vertical profile as described above, studies to improve the flatness of semiconductor devices have been actively conducted.

도 1a 내지 도 1d는 종래의 반도체장치의 미세패턴 제조공정을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views for explaining a micropattern manufacturing process of a conventional semiconductor device.

도 1a를 참조하면, 필드산화막(2)에 의해 활성영역과 필드영역으로 구분된 반도체 기판(1)상에 게이트 전극(4)과 소오스/드레인 영역(6)으로 이루어진 트랜지스터를 형성한 후, 상기 결과물 전면에 제1 절연층(10)을 형성한다. 이어서, 상기 절연층(10)의 상부에 식각저지층(12)으로서 질화막을 형성한 후, 그 상부에 다시 제2 절연층(14)을 형성한다. 상기 제2 절연층(14) 상에 포토레지스트를 도포한 후, 리소그래피에 의해 상기 드레인/소오스 영역(6)의 일부를 노출시키는 콘택홀(8)을 형성하기 위한 포토레지스트 패턴(도시안됨)을 형성한 다음 상기 포토레지스트 패턴을 식각마스크로 하여 상기 제2 절연층(14), 식각저지층(12) 및 제1 절연층(10)을 이방성식각하여 콘택홀(8)을 형성한다.Referring to FIG. 1A, a transistor including a gate electrode 4 and a source / drain region 6 is formed on a semiconductor substrate 1 divided into an active region and a field region by a field oxide film 2. The first insulating layer 10 is formed on the entire surface of the resultant product. Subsequently, after the nitride film is formed as the etch stop layer 12 on the insulating layer 10, the second insulating layer 14 is formed again on the nitride film. After applying photoresist on the second insulating layer 14, a photoresist pattern (not shown) for forming a contact hole 8 exposing a part of the drain / source region 6 by lithography is shown. After the formation, the contact hole 8 is formed by anisotropically etching the second insulating layer 14, the etch stop layer 12, and the first insulating layer 10 using the photoresist pattern as an etching mask.

상기 콘택홀(8)이 형성되어 있는 상기 기판(1)의 전면에 상기 콘택홀(8)을 채우고 상기 제2 절연층(14)을 기준으로 일정 두께를 가지도록 도전층(16)을 형성한다. 이어서, 상기 도전층(16)의 상부에 고온 산화물로 이루어진 제1 식각마스크층(18)과 다결정 실리콘으로 이루어진 제2 식각마스크층(20)을 형성한다.The conductive layer 16 is formed to fill the contact hole 8 in the entire surface of the substrate 1 on which the contact hole 8 is formed and to have a predetermined thickness based on the second insulating layer 14. . Subsequently, a first etching mask layer 18 made of a high temperature oxide and a second etching mask layer 20 made of polycrystalline silicon are formed on the conductive layer 16.

도 1b를 참조하면, 상기 제2 식각마스크층(20)의 상부에 포토레지스트를 도포한 후, 통상의 사진공정에 의해 커패시터 스토리지 전극 형성을 위한 포토레지스트 패턴(22)을 형성한다.Referring to FIG. 1B, after the photoresist is applied on the second etching mask layer 20, the photoresist pattern 22 for forming the capacitor storage electrode is formed by a general photolithography process.

계속하여, 상기 포토레지스트 패턴(22)을 식각마스크로 하여 플루오로카본(CF4)과 트리플루오로메탄(CHF3)을 이용한 플라즈마 건식식각방법으로 상기 제2 식각마스크층(20)인 다결정 실리콘층을 이방성 식각하면, 다결정 실리콘으로 구성된 제2 식각마스크(20a)가 형성된다. 이와 동시에 상기 포토레지스트 패턴(22) 및 상기 제2 식각마스크(20a)의 측벽에는 포토레지스트내의 탄소, 수소 및 산소 성분이 플라즈마와 반응하여 폴리머스페이서(24)가 형성된다.Subsequently, the second etching mask layer 20 is polycrystalline silicon by a plasma dry etching method using fluorocarbon (CF 4 ) and trifluoromethane (CHF 3 ) using the photoresist pattern 22 as an etching mask. When the layer is anisotropically etched, a second etching mask 20a made of polycrystalline silicon is formed. At the same time, a polymer spacer 24 is formed on sidewalls of the photoresist pattern 22 and the second etching mask 20a by reacting carbon, hydrogen and oxygen components in the photoresist with plasma.

도 1c를 참조하면, 상기 포토레지스트 패턴(22), 폴리머스페이서(24) 및 제2 식각마스크(20a)를 식각마스크로 하여 상기 제1 식각마스크층(18)을 이방성식각하여 제1 식각마스크(18a)를 형성한다.Referring to FIG. 1C, the first etching mask layer 18 is anisotropically etched using the photoresist pattern 22, the polymer spacer 24, and the second etching mask 20a as an etching mask to form a first etching mask ( 18a).

도 1d를 참조하면, 상기 제1 및 제2 식각마스크(18a, 20a)를 이용하여 상기 도전층(16)을 이방성식각하여 스토리지 전극 패턴(16a)을 형성한다. 상기 제2 식각마스크(20a)는 상기 도전층(16)의 식각과 동시에 제거된다.Referring to FIG. 1D, the conductive layer 16 is anisotropically etched using the first and second etching masks 18a and 20a to form the storage electrode pattern 16a. The second etching mask 20a is removed at the same time as the etching of the conductive layer 16.

이어서, 암모니아(NH4)와 불산(HF)으로 이루어진 화학약품을 이용한 습식식각으로 상기 스토리지 전극 패턴(16a) 하부의 제2 절연층(14) 및 상기 제1 식각마스크(18)를 제거함으로써 커패시터 스토리지 전극을 완성한다.Subsequently, the capacitor is removed by removing the second insulating layer 14 and the first etching mask 18 under the storage electrode pattern 16a by wet etching using a chemical agent consisting of ammonia (NH 4 ) and hydrofluoric acid (HF). Complete the storage electrode.

그러나, 상기한 미세패턴 제조방법으로 제조한 캐패시터는 캐패시터의 프로파일(profile)이 수직하게 형성됨으로서, 셀영역과 주변부와의 단차가 증가하는 단점이 있다. 이와같이 셀영역과 주변부와 단차가 증가하게 되면, 이 후 상기 단차를 줄이기 위하여 수행되는 화학적기계적연마(CMP) 방법과 같은 평탄화 공정시 반도체장치가 손상되는 문제점이 있다.However, the capacitor manufactured by the method of manufacturing the fine pattern has a disadvantage in that the profile of the capacitor is vertically formed, thereby increasing the step difference between the cell region and the peripheral portion. In this way, if the step area and the cell area and the periphery increase, there is a problem that the semiconductor device is damaged during the planarization process, such as a chemical mechanical polishing (CMP) method performed to reduce the step.

이러한 문제점을 해결하고자, 캐패시터를 형성한 후 캐패시터의 상부에 다수의 산화물을 적층하는 방법이 국내공개특허 공보 제97-54079호(발명의 명칭 : 반도체장치의 제조방법)에 기재되어 있다.In order to solve this problem, a method of stacking a plurality of oxides on the capacitor after forming the capacitor is described in Korean Patent Publication No. 97-54079 (name of the invention: a method of manufacturing a semiconductor device).

도 2는 상기 국내 공개 특허 공보 제97-54079호에 기재된 반도체장치의 제조방법을 설명하기 위한 단면도이다.2 is a cross-sectional view for explaining a method for manufacturing a semiconductor device described in Korean Laid-Open Patent Publication No. 97-54079.

도 2를 참조하면, 일반적인 메모리 커패시터의 제조 공정에 따라 비트라인(도시안됨)을 형성하고, 그 위에 층간 절연막(44)을 형성한 후, 상기 절연막(44)을 선택적으로 식각하여 반도체 기판(30)상에 콘택홀(46)을 형성한다.Referring to FIG. 2, a bit line (not shown) is formed in accordance with a general process of manufacturing a memory capacitor, an interlayer insulating film 44 is formed thereon, and the insulating film 44 is selectively etched to form a semiconductor substrate 30. The contact hole 46 is formed on ().

계속하여, 상기 콘택홀(46)을 포함하는 상기 절연막(30) 상에 폴리실리콘을 증착시킨 후, 상기 폴리실리콘을 선택적으로 식각하여 스토리지 전극(32)을 형성한다.Subsequently, after depositing polysilicon on the insulating layer 30 including the contact hole 46, the polysilicon is selectively etched to form a storage electrode 32.

이어서, 상기 스토리지 전극(32)을 에워싸는 유전막(34)을 형성하고, 상기 유전막(34)상에 플레이트 전극(36)을 형성한 후, 상기 플레이트 전극(36)을 포함하는 절연막 상에 TEOS막(38)), BPSG막(40), SOG막(42)을 차례로 형성한다.Subsequently, a dielectric film 34 surrounding the storage electrode 32 is formed, and a plate electrode 36 is formed on the dielectric film 34, and then a TEOS film (on the insulating film including the plate electrode 36) is formed. 38), the BPSG film 40, and the SOG film 42 are formed in this order.

그리고 에치백 공정을 실시하여 셀 영역과 주변영역간에 발생한 고단차를 평탄화시킨다.An etch back process is performed to planarize the high step generated between the cell region and the peripheral region.

그러나, 상술한 종래의 반도체장치의 제조방법에 따르면, 포토레지스트의 측면에 폴리머 스페이서를 형성한 후, 건식식각방법으로 패터닝하여 수직한 프로파일을 갖는 스토리지 전극을 형성함으로써, 패턴이 형성되는 셀영역과 패턴이 형성되지 않는 주변부와의 단차가 급격하게 증가하게 되어, 이 후 수행되는 에치백 공정시 셀영역과 주변부와의 연결부위에 발생하는 식각 잔류물 등이 제거되지 않는 문제점이 있으며, 또한 단차를 줄이기 위한 방법으로써 커패시터의 상부에 여러층의 산화물을 형성해야하는 공정이 장시간 필요하게 되어 반도체 장치의 생산효율이 저하되는 문제점이 있다.However, according to the above-described method of manufacturing a semiconductor device, by forming a polymer spacer on the side surface of the photoresist and patterning it by dry etching to form a storage electrode having a vertical profile, the cell region in which the pattern is formed and There is a problem that the step with the peripheral portion where the pattern is not formed increases rapidly, and the etching residue generated in the connection area between the cell region and the peripheral portion during the etch back process, which is subsequently performed, is not removed. As a method for reducing, there is a problem in that a process of forming multiple layers of oxides on the capacitor is required for a long time, thereby lowering the production efficiency of the semiconductor device.

따라서, 본 발명의 목적은 셀영역과 주변부와의 단차를 최소화함으로써, 반도체 장치의 생산효율을 향상시킬 수 있는 반도체 장치의 제조방법을 제공하는 것이다.Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device which can improve the production efficiency of the semiconductor device by minimizing the step between the cell region and the peripheral portion.

도 1a 내지 도 1d는 종래의 반도체 장치의 미세패턴 제조공정을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a micropattern manufacturing process of a conventional semiconductor device.

도 2는 종래의 반도체 장치의 평탄화 방법을 설명하기 위한 단면도이다.2 is a cross-sectional view illustrating a planarization method of a conventional semiconductor device.

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 반도체 장치의 제조방법을 설명하기 위한 단면도들이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of the drawings>

50 : 기판 52 : 필드산화막50 substrate 52 field oxide film

54 : 게이트 56 : 소오스/드레인 영역54 gate 56 source / drain regions

58 : 콘택홀 60 : 제1 절연층58: contact hole 60: first insulating layer

62 : 식각저지층 64 : 제2 절연층62: etch stop layer 64: second insulating layer

66 : 폴리실리콘층 68 : 제2 포토레지스트 패턴66 polysilicon layer 68 second photoresist pattern

70 : 스토리지 전극 72 : 에지(edge)70 storage electrode 72 edge

74 : 유전체막 76 : 플레이트 전극74 dielectric film 76 plate electrode

78 : TEOS막 80 : SOG막78: TEOS film 80: SOG film

82 : 제2 포토레지스트 패턴의 측면82: side of second photoresist pattern

90 : 셀영역 92 : 주변부90: cell area 92: periphery

상술한 본 발명의 목적을 달성하기 위하여 본 발명은 기판 상에 절연층을 형성하고, 상기 절연층을 패터닝하여 상기 기판 상에 컨택홀을 형성하는 단계, 상기 절연층 및 컨택홀의 상부에 폴리실리콘을 적층하여 폴리실리콘층을 형성하는 단계, 상기 폴리실리콘의 상부에 포토레지스트를 도포한 후, 상기 포토레지스트를 사진식각방법으로 패터닝하여 상기 폴리실리콘의 상부에 포토레지스트패턴을 형성하는 단계, 상기 포토레지스트 패턴을 식각마스크로 하여 브롬화수소(HBr)가스, 염소(Cl2)가스, 헬륨(He)가스 및 산소(O2)가스로 이루어진 혼합가스로 상기 폴리실리콘층 중 셀 내부는 수직하게 식각하고, 주변부쪽의 측면부는 경사지게 식각하여 스토리지 전극을 형성하는 단계, 그리고 상기 스토리지 전극의 상부에 유전막 및 플레이트 전극을 순차적으로 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조방법을 제공한다.In order to achieve the above object of the present invention, the present invention is to form an insulating layer on a substrate, and to form a contact hole on the substrate by patterning the insulating layer, the polysilicon on the insulating layer and the contact hole Forming a polysilicon layer by laminating, applying a photoresist on the polysilicon, and then patterning the photoresist by a photolithography method to form a photoresist pattern on the polysilicon, the photoresist Using the pattern as an etch mask, a mixed gas consisting of hydrogen bromide (HBr) gas, chlorine (Cl 2 ) gas, helium (He) gas, and oxygen (O 2 ) gas is used to etch the inside of the cell vertically in the polysilicon layer. Side surfaces of the peripheral portion are inclined to form a storage electrode, and a dielectric film and a plate electrode are sequentially formed on the storage electrode. In that it comprises a step of forming a provides a semiconductor device manufacturing method according to claim.

상기 플레이트 전극을 형성한 후에는 상기 플레이트 전극의 상부에 SOG막을 도포하고 습식 에치백 공정으로 상기 기판의 상부를 평탄화하는 공정이 수행된다.After the plate electrode is formed, a process of applying an SOG film on the plate electrode and flattening the top of the substrate by a wet etch back process is performed.

상기 폴리실리콘층을 건식 식각하는 단계는 약 80∼230mTorr의 압력, 약 300∼400W의 RF전력에서 수행되며, 상기 브롬화수소 가스의 유량은 약 120sccm 정도이며, 상기 염소가스의 유량은 약 30sccm 정도이고, 상기 헬륨가스 및 상기 산소가스의 유량은 약 8sccm 정도이다.Dry etching the polysilicon layer is carried out at a pressure of about 80 to 230mTorr, RF power of about 300 to 400W, the flow rate of the hydrogen bromide gas is about 120sccm, the flow rate of the chlorine gas is about 30sccm The flow rate of the helium gas and the oxygen gas is about 8 sccm.

본 발명에 따르면, 폴리실리콘층을 형성한 후, 스토리지 전극을 형성하기 위한 건식식각공정시, 브롬화수소 가스, 염소 가스, 헬륨 가스, 산소 가스를 이용하여 건식식각함으로써, 로딩효과에 의해 셀영역과 주변부와의 단차가 완화되어 이 후 평탄화하기위하여 수행되는 평탄화공정시간을 단축시킬 수 있으므로, 반도체 장치의 생산성을 향상시킬 수 있다.According to the present invention, after forming the polysilicon layer, during the dry etching process for forming the storage electrode, by dry etching using hydrogen bromide gas, chlorine gas, helium gas, oxygen gas, the cell region and the Since the step with the peripheral portion is alleviated, the planarization process time performed to planarize later can be shortened, so that the productivity of the semiconductor device can be improved.

이하 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 따른 반도체 장치의 제조방법을 상세하게 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 반도체 장치의 제조방법을 설명하기 위한 단면도들이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

도 3a를 참조하면, 필드산화막(52)에 의해 액티브영역과 필드영역으로 분리된 반도체 기판(50) 상에 게이트 전극(54)과 소오스/드레인 영역(56)으로 이루어진 트랜지스터를 형성한 후, 상기 결과물의 전면에 산화 실리콘을 증착하여 제1 절연층(60)을 형성한다.Referring to FIG. 3A, a transistor including a gate electrode 54 and a source / drain region 56 is formed on a semiconductor substrate 50 separated by a field oxide film 52 into an active region and a field region. Silicon oxide is deposited on the entire surface of the resultant to form the first insulating layer 60.

이어서, 상기 제1 절연층(60)의 상부에 질화물을 적층하여 식각저지층(62)을 형성한 후, 그 상부에 다시 산화 실리콘을 증착하여 제2 절연층(64)을 형성한다. 계속하여 상기 제2 절연층(64)의 상부에 포토레지스트를 도포하여 제1 포토레지스트막을 형성한 후, 통상의 사진방법을 이용하여 상기 소오스/드레인 영역(56)의 일부를 노출시키는 콘택홀을 형성하기 위한 제1 포토레지스트 패턴(도시안됨)을 형성한다. 다음에, 상기 제1 포토레지스트 패턴을 식각마스크로 하여 상기 제2 절연층(64), 식각저지층(62), 및 제1 절연층(60)을 이방성 식각하여 콘택홀(58)을 형성한다.Subsequently, nitride is deposited on the first insulating layer 60 to form the etch stop layer 62, and then silicon oxide is deposited on the second insulating layer 64 to form the second insulating layer 64. Subsequently, after forming a first photoresist film by applying photoresist on the second insulating layer 64, a contact hole for exposing a part of the source / drain region 56 is exposed using a conventional photographing method. A first photoresist pattern (not shown) is formed to form. Next, the contact hole 58 is formed by anisotropically etching the second insulating layer 64, the etch stop layer 62, and the first insulating layer 60 by using the first photoresist pattern as an etching mask. .

도 3b를 참조하면, 상기 콘택홀(58)이 형성된 상기 기판(50)의 전면 및 상기 콘택홀(58)의 내부에 폴리실리콘을 적층하여 소정의 두께를 갖는 폴리실리콘층(66)을 형성한다. 계속하여, 상기 폴리실리콘층(66)의 상부에 포토레지스트를 도포하여 제2 포토레지스트막(도시 안됨)을 형성한 후, 통상의 사진공정을 이용하여 상기 폴리실리콘층(66)의 상부에 제2 포토레지스트 패턴(68)을 형성한다.Referring to FIG. 3B, a polysilicon layer 66 having a predetermined thickness is formed by stacking polysilicon on the front surface of the substrate 50 on which the contact hole 58 is formed and inside the contact hole 58. . Subsequently, a photoresist is applied on the polysilicon layer 66 to form a second photoresist film (not shown), and then the upper portion of the polysilicon layer 66 is formed by using a normal photographing process. 2 Photoresist pattern 68 is formed.

도 3c를 참조하면, 상기 제2 포토레지스트 패턴(68)을 식각마스크로 하여 상기 제2 포토레지스트 패턴(68)의 하부에 노출된 폴리실리콘층(66)을 브롬화수소(HBr) 가스, 염소(Cl2) 가스, 헬륨(He) 가스 및 산소(O2) 가스를 사용하여 건식식각방법으로 식각함으로써 스토리지 전극(70)을 형성한다.Referring to FIG. 3C, the polysilicon layer 66 exposed under the second photoresist pattern 68 using the second photoresist pattern 68 as an etching mask is formed of hydrogen bromide (HBr) gas and chlorine ( The storage electrode 70 is formed by etching by dry etching using Cl 2 ) gas, helium (He) gas, and oxygen (O 2 ) gas.

일반적으로 미세한 패턴을 형성하고, 패턴밀도의 차이로 인하여 식각된 패턴의 크기가 일정치 않게 되는 로딩효과(loading effect)를 줄이기 위해 이방성 건식식각방법에 사용되는 가스로는 플루오로카본(CF4) 가스, 트리플루오로메탄(CHF3) 가스, 헥사플루오르화 황(SF6) 가스, 염소 가스 등의 혼합가스가 사용되고 있다. 그러나, 상기 가스들을 사용한 이방성 건식식각 방법으로 스토리지 전극을 형성할 경우 로딩효과를 억제하여 수직한 프로파일을 얻을 수 있다는 장점은 있으나, 셀과 주변부와의 단차도 함께 증가하게 됨으로써, 이후 복수 회의 평탄화공정이 요구됨으로써 공정시간이 늘어나게 되는 단점이 있다.In general, a fluorocarbon (CF 4 ) gas is used for the anisotropic dry etching method to form a fine pattern and to reduce a loading effect in which the size of the etched pattern becomes inconsistent due to a difference in pattern density. And mixed gases such as trifluoromethane (CHF 3 ) gas, sulfur hexafluoride (SF 6 ) gas, and chlorine gas. However, when the storage electrode is formed by the anisotropic dry etching method using the gases, there is an advantage in that the vertical profile is obtained by suppressing the loading effect, but the step difference between the cell and the peripheral part is also increased, and then, the multiple planarization process is performed. This demand is disadvantageous in that the process time is increased.

따라서, 본 발명에서는 상기 노출된 폴리실리콘층(66)을 브롬화수소(HBr) 가스, 염소(Cl2) 가스, 헬륨(He) 가스 및 산소(O2) 가스로 이루어진 혼합가스를 사용하여 이방성 건식식각방법으로 식각함으로써, 셀 영역(90)의 패턴에 대해서는 종래와 같이 수직하게 이방성 식각이 이루어짐으로써 수직한 프로파일(profile)을 갖도록 식각이 되지만, 상기 제2 포토레지스트 패턴(68)이 형성되어 있지 않고, 또한 상기 셀영역(90)보다 상대적으로 폴리실리콘층이 많이 노출되어 있는 주변부(92)에서는 폴리실리콘과 반응가스와의 반응으로 인하여 형성된 폴리머들이 상기 셀영역(90)과 상기 주변부(92)와의 연결부위의 상부에 형성된 상기 제2 포토레지스트 패턴(68)의 측면(82)에 부착되어 에칭시 마스크 역할을 부분적으로 수행하게 된다. 따라서, 도시한 바와 같이, 상기 주변부(92)와의 연결 부위의 상부에 형성된 스토리지 전극(70)의 에지부분(72, 즉 주변부쪽의 측면부)이 경사지게 식각된다.Therefore, in the present invention, the exposed polysilicon layer 66 is anisotropic dry using a mixed gas composed of hydrogen bromide (HBr) gas, chlorine (Cl 2 ) gas, helium (He) gas, and oxygen (O 2 ) gas. By etching by the etching method, the pattern of the cell region 90 is etched to have a vertical profile by vertically anisotropic etching as in the prior art, but the second photoresist pattern 68 is not formed. In addition, in the peripheral portion 92 where the polysilicon layer is exposed relatively more than the cell region 90, polymers formed by the reaction between the polysilicon and the reaction gas are formed in the cell region 90 and the peripheral portion 92. It is attached to the side surface 82 of the second photoresist pattern 68 formed on the upper portion of the connection portion to partially serve as a mask during etching. Therefore, as shown in the drawing, the edge portion 72 (that is, the side portion of the peripheral portion) of the storage electrode 70 formed on the connection portion with the peripheral portion 92 is inclinedly etched.

상기 폴리실리콘층(66)을 건식식각방법으로 패터닝하는 공정은 예를 들면, AMT(Applied Material Technology)사에서 제조한 P 5000(Precision 5000)플라즈마 식각장치에서 수행되며, 약 80∼230mTorr정도의 압력과, 300∼400W의 RF전력에서 실시한다.The process of patterning the polysilicon layer 66 by a dry etching method is performed in, for example, a P 5000 (Precision 5000) plasma etching apparatus manufactured by AMT (Applied Material Technology), and has a pressure of about 80 to 230 mTorr. And RF power of 300 to 400 W.

상기 브롬화수소 가스의 유량은 약 120sccm정도이고, 상기 염소가스의 유량은 약 30sccm정도이며, 상기 헬륨가스 및 상기 산소가스의 유량은 약 8sccm정도로 한다. 또한, 바람직하게는 상기 브롬화수소 가스, 염소 가스의 혼합 비율은 약 4:1정도가 되도록하며, 상기 헬륨가스 및 상기 산소 가스는 소량 첨가한다.The flow rate of the hydrogen bromide gas is about 120 sccm, the flow rate of the chlorine gas is about 30 sccm, and the flow rate of the helium gas and the oxygen gas is about 8 sccm. Preferably, the mixing ratio of the hydrogen bromide gas and the chlorine gas is about 4: 1, and the helium gas and the oxygen gas are added in small amounts.

상술한 본 발명의 이방성 건식식각 방법의 메카니즘을 상세히 살펴보면 다음과 같다.Looking at the mechanism of the anisotropic dry etching method of the present invention described above in detail.

먼저, 헬륨 가스는 불활성 가스로서 플라즈마 장치 내에서 발생한 플라즈마가 다른 가스와 반응하는 것을 억제하는 역할을 하고, 산소 가스는 산화성 가스이기 때문에 반응 활성도가 높아 반응성이 강하므로, 원하는 방향으로 쉽게 식각이 이루어진다. 또한, 염소 가스는 폴리실리콘에 대한 선택비가 매우 높기 때문에 이방성 식각이 용이하게 수행되며, 브롬화수소 가스는 폴리실리콘과 반응하여 브롬화실리콘(SiBr4)과 같은 반응생성물들을 생성시킨다.First, helium gas is an inert gas, and serves to suppress the plasma generated in the plasma apparatus from reacting with other gases, and since oxygen gas is an oxidizing gas, the reaction activity is high and the reaction is strong, so that etching is easily performed in a desired direction. . In addition, since chlorine gas has a very high selectivity to polysilicon, anisotropic etching is easily performed, and hydrogen bromide gas reacts with polysilicon to generate reaction products such as silicon bromide (SiBr 4 ).

따라서, 상기 제2 포토레지스트 패턴(68)을 형성한 후, 상기 반응가스들을 이용하여 이방성 식각을 수행하게 되면, 패턴이 작게 형성된 상기 셀영역(90)에서는 폴리실리콘의 양이 적으므로 브롬화수소 가스와의 반응으로 인하여 상기 제2 포토레지스트 패턴(68)의 측면에 소량의 반응생성물들이 얇은 막으로 형성되지만, 상기 제2 포토레지스트 패턴(68)이 형성되지 않고 또한 폴리실리콘층이 다량 노출되어 있는 상기 주변부(92)에서는 폴리실리콘과 브롬화수소 가스와의 반응으로 인하여 다량의 반응생성물들이 상기 주변부(92)와 인접한 상기 제2 포토레지스트 패턴(68)의 측면(82)에 형성된다. 따라서, 상기 폴리실리콘층을 식각하는 상기 이방성 식각 공정이 진행될수록, 주변부와 인접한 상기 제2 포토레지스트 패턴(68)의 측면(82)에는 많은 상기 반응생성물들이 쌓이게 되고, 이에 따라 그 하부에 형성된 상기 폴리실리콘층이 덜 식각되어지게 되면서, 도 3c와 같이 상기 주변부(92)에 인접한 상기 스토리지 전극(70)의 에지부분(72)이 경사지게 된다.Therefore, when the anisotropic etching is performed using the reaction gases after the formation of the second photoresist pattern 68, since the amount of polysilicon is small in the cell region 90 in which the pattern is small, hydrogen bromide gas is used. Although a small amount of reaction products are formed in a thin film on the side of the second photoresist pattern 68 due to the reaction with the second photoresist pattern 68, the second photoresist pattern 68 is not formed and a large amount of the polysilicon layer is exposed. In the peripheral portion 92, a large amount of reaction products are formed on the side surface 82 of the second photoresist pattern 68 adjacent to the peripheral portion 92 due to the reaction between the polysilicon and the hydrogen bromide gas. Accordingly, as the anisotropic etching process for etching the polysilicon layer proceeds, many reaction products are accumulated on the side surface 82 of the second photoresist pattern 68 adjacent to a peripheral portion, and thus the lower portion of the polysilicon layer is formed. As the polysilicon layer is less etched, the edge portion 72 of the storage electrode 70 adjacent to the peripheral portion 92 is inclined as shown in FIG. 3C.

계속하여, 상기 제2 포토레지스트 패턴(68)을 제거하여 스토리지 전극(70)을 형성한다.Subsequently, the second photoresist pattern 68 is removed to form the storage electrode 70.

도 3d를 참조하면, 상기 스토리지 전극(70)을 형성한 후, 상기 스토리지 전극(70)의 상부에 유전물질, 바람직하게는 오산화탄탈륨(Ta2O5)을 도포하여 유전체막(74)을 형성하고, 상기 유전체막(74)의 상부에 폴리실리콘을 상기 유전체막(74)의 전면에 증착시켜 플레이트 전극(76)을 형성한다. 따라서, 스토리지 전극(70), 유전체막(74) 및 플레이트 전극(76)으로 구성된 커패시터가 완성된다.Referring to FIG. 3D, after forming the storage electrode 70, a dielectric material, preferably tantalum pentoxide (Ta 2 O 5 ), is coated on the storage electrode 70 to form the dielectric film 74. Then, polysilicon is deposited on the dielectric film 74 on the entire surface of the dielectric film 74 to form a plate electrode 76. Thus, a capacitor composed of the storage electrode 70, the dielectric film 74 and the plate electrode 76 is completed.

이어서, 상기 플레이트 전극(76)의 상부에 TEOS막(78)을 적층하고, 그 상부에 스핀 온 글래스(SOG) 공정을 이용하여 SOG막(80)을 도포한 다음, 습식 에치백공정을 실시하여 상기 기판(50)의 상부를 평탄화시킴으로써 상기 셀영역(90)과 상기 주변부(92)와의 단차를 최소화시킨다.Subsequently, the TEOS film 78 is stacked on the plate electrode 76, the SOG film 80 is coated on the plate using a spin on glass (SOG) process, and then a wet etch back process is performed. By flattening the upper portion of the substrate 50, the step difference between the cell region 90 and the peripheral portion 92 is minimized.

종래에는 스토리지 전극 중 주변부와 인접한 에지(edge)부분이 수직하게 형성됨으로써 셀영역과 주변부와의 단차가 급격하게 형성되어, 이후 수행되는 평탄화공정, 즉 스핀 온 글래스 공정을 수차례 실시하여야 하는 단점이 있었으나, 본 발명에 의하면, 상기 스토리지 전극의 에지부분(72)이 약 10∼45°정도 경사를 갖도록 형성됨으로써, 이 후 수행되는 평탄화 공정을 단축시킬 수 있다.Conventionally, the edge portion adjacent to the periphery of the storage electrode is vertically formed so that a step between the cell region and the periphery is rapidly formed, and thus, a planarization process, that is, a spin on glass process, is performed several times. However, according to the present invention, since the edge portion 72 of the storage electrode is formed to be inclined by about 10 to 45 °, the planarization process performed thereafter can be shortened.

본 발명에 따른 반도체 장치의 제조방법에 의하면, 폴리실리콘층을 형성한 후, 스토리지 전극을 형성하기 위한 건식식각 공정시, 브롬화수소 가스, 염소 가스, 헬륨 가스, 산소 가스를 이용하여 건식식각함으로써, 브롬화수소 가스와 폴리실리콘과의 반응으로 생성된 반응생성물들이 셀과 주변부와의 연결부위에 형성된 포토레지스트 패턴의 측부에 형성됨으로써 그 하부에 형성된 폴리실리콘층이 소정의 경사를 갖게 된다. 따라서, 셀영역과 주변부와의 단차가 완화되어 이 후 평탄화하기위하여 수행되는 평탄화공정시간을 단축시킬 수 있으므로, 반도체 장치의 생산성을 향상시킬 수 있다.According to the method of manufacturing a semiconductor device according to the present invention, after forming a polysilicon layer, by dry etching using hydrogen bromide gas, chlorine gas, helium gas, oxygen gas during the dry etching process for forming a storage electrode, The reaction products generated by the reaction between the hydrogen bromide gas and the polysilicon are formed on the side of the photoresist pattern formed at the connection portion between the cell and the peripheral portion, so that the polysilicon layer formed thereunder has a predetermined slope. Therefore, the step between the cell region and the peripheral portion is alleviated, so that the planarization process time performed to planarize later can be shortened, so that the productivity of the semiconductor device can be improved.

상술한 바와 같이, 본 발명의 바람직한 실시예를 참조하여 설명하였지만 해당 기술 분야의 숙련된 당업자라면 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (3)

기판 상에 절연층을 형성하고, 상기 절연층을 패터닝하여 상기 기판 상에 컨택홀을 형성하는 단계;Forming an insulating layer on the substrate and patterning the insulating layer to form contact holes on the substrate; 상기 절연층 및 컨택홀의 상부에 폴리실리콘을 적층하여 폴리실리콘층을 형성하는 단계;Stacking polysilicon on the insulating layer and the contact hole to form a polysilicon layer; 상기 폴리실리콘층의 상부에 포토레지스트를 도포한 후, 상기 포토레지스트를 사진식각방법으로 패터닝하여 상기 폴리실리콘층의 상부에 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern on the polysilicon layer by coating the photoresist on the polysilicon layer, and then patterning the photoresist by photolithography; 상기 포토레지스트 패턴을 식각마스크로 하여 브롬화수소(HBr)가스, 염소(Cl2)가스, 헬륨(He)가스 및 산소(O2)가스로 이루어진 혼합가스로 상기 폴리실리콘층 중 셀 내부는 수직하게 식각하고, 주변부쪽의 측면부는 경사지게 식각하여 스토리지 전극을 형성하는 단계; 그리고The photoresist pattern as an etching mask is a mixed gas composed of hydrogen bromide (HBr) gas, chlorine (Cl 2 ) gas, helium (He) gas, and oxygen (O 2 ) gas. Etching and etching sidewalls of the peripheral portion inclinedly to form storage electrodes; And 상기 스토리지 전극의 상부에 유전막 및 플레이트 전극을 순차적으로 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조방법.And sequentially forming a dielectric film and a plate electrode on the storage electrode. 제1항에 있어서, 상기 플레이트 전극을 형성한 후, 상기 플레이트 전극의 상부에 SOG막을 도포하고 습식 에치백 공정을 수행하여 상기 기판의 상부를 평탄화하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.The semiconductor device of claim 1, further comprising, after forming the plate electrode, applying an SOG film on the plate electrode and performing a wet etch back process to planarize the top of the substrate. Manufacturing method. 제1항에 있어서, 상기 이방성 식각하는 단계는 80∼230mTorr의 압력, 300∼400W의 RF전력에서 수행되며, 상기 브롬화수소 가스의 유량은 120sccm이고, 상기 염소가스의 유량은 30sccm이며, 상기 헬륨가스 및 상기 산소가스의 유량은 8sccm인 것을 특징으로 하는 반도체 장치 제조방법.The method of claim 1, wherein the anisotropic etching is performed at a pressure of 80 to 230 mTorr and an RF power of 300 to 400 W, the flow rate of the hydrogen bromide gas is 120 sccm, the flow rate of the chlorine gas is 30 sccm, and the helium gas. And the flow rate of the oxygen gas is 8 sccm.
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