KR20000048093A - Tungsten silicide nitride as an electrode for tantalum pentoxide devices - Google Patents
Tungsten silicide nitride as an electrode for tantalum pentoxide devices Download PDFInfo
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- KR20000048093A KR20000048093A KR1019990056953A KR19990056953A KR20000048093A KR 20000048093 A KR20000048093 A KR 20000048093A KR 1019990056953 A KR1019990056953 A KR 1019990056953A KR 19990056953 A KR19990056953 A KR 19990056953A KR 20000048093 A KR20000048093 A KR 20000048093A
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- layer
- gate electrode
- tungsten silicide
- insulating layer
- silicon
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- 229910021342 tungsten silicide Inorganic materials 0.000 title claims abstract description 29
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 title claims abstract description 12
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 title claims abstract description 12
- -1 Tungsten silicide nitride Chemical class 0.000 title claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 17
- 230000005669 field effect Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 15
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims description 10
- 238000004544 sputter deposition Methods 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 3
- 238000005477 sputtering target Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims 5
- 230000006837 decompression Effects 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 claims 1
- 239000011261 inert gas Substances 0.000 claims 1
- 239000001301 oxygen Substances 0.000 abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 3
- 238000005240 physical vapour deposition Methods 0.000 description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- AZCUJQOIQYJWQJ-UHFFFAOYSA-N oxygen(2-) titanium(4+) trihydrate Chemical compound [O-2].[O-2].[Ti+4].O.O.O AZCUJQOIQYJWQJ-UHFFFAOYSA-N 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000003786 synthesis reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910008807 WSiN Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229920002994 synthetic fiber Polymers 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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Abstract
Description
본 발명은 전계 효과 장치들을 제조하기 위한 방법과 보다 구체적으로 실리콘 MOS 트랜지스터들에 대한 게이트 전극들을 형성하기 위한 방법에 관한 것이다.The present invention relates to a method for manufacturing field effect devices and, more particularly, to forming gate electrodes for silicon MOS transistors.
1970년대 초기에 전계 효과 트랜지스터들의 상업적 시도 이후로, 게이트 유전체는 실리콘 이산화물과 보다 최근에 실리콘 산화질화물(oxynitride)을 가진다. 이러한 장치들에 대한 전극은 정상적으로 듀얼-도핑되었고 티타늄 질화물의 불순물(dopant) 확산 배리어에 탑트(topped)된다. 최근에, 티타늄 질화물은 유전체로서 실리콘 이산화물로 대체되는 것이 제안되었다. 전체를 설명하는 것처럼 여기에 포함된 C. Hu, Elec. Dev. Letters, Sept. 1998, p.341-42를 참조한다. 그러나, 티타늄 펜타옥사이드 누설 전류는 산소가 없어짐에 따라 증가된 온도 처리에 따라 증가된다. O2또는 N2O와 같은 산화 가스에서 어널링은 정상적으로 이 하락을 반전한다. 티타늄 질화물은 특히, 약 600℃에서, 이 온도에서 분해하기 시작하는 티타늄 질화물로서 이 산소 손실에 대한 효과가 없는 배리어이다. 따라서, 티타늄 펜타옥사이드는 게이트 유전체로서 사용될 때 고-밀도 실리콘 MOS 트랜지스터로 개선된 게이트 전극 물질을 요구한다.Since commercial attempts by field effect transistors in the early 1970s, gate dielectrics have silicon dioxide and more recently silicon oxynitride. The electrode for these devices was normally dual-doped and topped with a dopant diffusion barrier of titanium nitride. Recently, titanium nitride has been proposed to be replaced by silicon dioxide as a dielectric. As described in its entirety, C. Hu, Elec. Dev. Letters, Sept. See 1998, p. 341-42. However, the titanium pentaoxide leakage current increases with increasing temperature treatment as oxygen is lost. In oxidizing gases such as O 2 or N 2 O, annealing normally reverses this drop. Titanium nitride is a titanium nitride that begins to decompose at this temperature, especially at about 600 ° C., and is a barrier with no effect on this oxygen loss. Thus, titanium pentaoxides require improved gate electrode materials with high-density silicon MOS transistors when used as gate dielectrics.
우리는 축적된(stacked) 티티늄 펜타옥사이드 유전체 또는 티타늄 펜타옥사이드로 실리콘 MOS 트랜지스터 IC 장치들에 대한 개선된 MOS 게이트 구조를 개발하였다. 구조는 WSi 및 WSIN의 두 레벨 합성과, WSI/WSIN/WSi의 세 레벨 합성을 포함한다. 텅스텐 실리사이드층은 게이트 구조에 대한 전기적 전도성을 제공하고, 텅스텐 실리콘 질화물층은, 약 800℃로 중가된 온도에서 특히, 산소 확산에 대한 효과적인 배리어이다. 이 게이트 구조는 티타늄 질화물의 증가된 온도 문제들이 전혀 없도록 견딘다. 개선된 구조의 유용한 특징은 합성의 모든 층들의 편리한 in-situ 처리로 단일 증착 도구로 제조될 수 있다.We have developed an improved MOS gate structure for silicon MOS transistor IC devices with a stacked titanium pentaoxide dielectric or titanium pentaoxide. The structure includes two-level synthesis of WSi and WSIN, and three-level synthesis of WSI / WSIN / WSi. The tungsten silicide layer provides electrical conductivity to the gate structure, and the tungsten silicon nitride layer is an effective barrier to oxygen diffusion, especially at temperatures elevated to about 800 ° C. This gate structure withstands no increased temperature problems of titanium nitride. A useful feature of the improved structure can be made in a single deposition tool with convenient in-situ treatment of all layers of the synthesis.
도1은 본 발명에 따른 합성 게이트 전극 모드를 도시하는 전형적인 전계 효과 트랜지스터의 게이트 영역의 개략도.1 is a schematic diagram of a gate region of a typical field effect transistor showing a composite gate electrode mode in accordance with the present invention.
도2는 본 발명을 구현하는데 유용한 물리적 증기 증착(physical vapor deposition)(PVD) 장치의 개략도.2 is a schematic diagram of a physical vapor deposition (PVD) device useful for implementing the present invention.
도3 내지 도 5는 도1의 합성 게이트 전극을 형성하기 위한 처리 순서를 나타내는 개략도.3 to 5 are schematic diagrams showing a processing procedure for forming the composite gate electrode of FIG.
*도면의 주요 부분에 대한 부호의 간단한 설명** Brief description of symbols for the main parts of the drawings *
11: 실리곤 기판 12: 전계 유전체11: silicon substrate 12: electric field dielectric
13: 게이트 유전체 16: 합성 게이트 전극13: gate dielectric 16: composite gate electrode
17: 텡스텐 실리사이드 질화물층17: tungsten silicide nitride layer
본 발명은 첨부하는 도면을 참조하여 숙독할 때, 다음의 구체적인 설명으로부터 이해될 수 있다. 반도체 산업에서 공통 실행에 따라, 도면의 다양한 특징들이 스케일(scale)되지 않았다는 것이 강조된다.The invention can be understood from the following detailed description when read with reference to the accompanying drawings. It is emphasized that various features of the figures have not been scaled, in accordance with common practice in the semiconductor industry.
도1을 참조하여, 실리콘 기판(11)이 전계 유전체(12)와 도시되고, 금속-유기적 화학적 증기 증착(metal-organic chemical vapor deposition)(MOCVD)에 의해 형성되는 티타늄 펜타옥사이드 게이트 유전체(13)가 도시된다. 본 발명의 양호한 적용에서, 게이트 유전체층은 10㎚보자 작고, 양호하게는 6㎚보다 작다. 이것은 산소 고갈 문제[p들이 티타늄 펜타옥사이드 유전체들과 가장 맹렬한(severe) 차원의 영역이다. 임의의 이론들과 유지되기를 바라지 않는다면, 산소 손실은 화학량론의 티타늄 옥사이드를 만들 수 있고, 손실 산소는 정공 캐리어들을 남기고, 이것은 티타늄 펜타옥사이드의 절연 영역을 감소시키고, 누설 전류를 증가시킨다. 특히 바람직한 것은 실리콘 이산화물이 실리콘상에 먼저 형성되는 축적된 티타늄 펜타옥사이드 유전체 시스템의 사용이고, 티타늄 펜타옥사이드에 의해 뒤따르고, 실리콘 이산화물의 다른 층에 의해 뒤따르고, 각각의 두께는 약 0.8㎚ 내지 2㎚, 약 3 내지 약 30㎚, 약 0.5 내지 약 2㎚이다. 축적된 티타늄 펜타옥사이드 시스템은 P.K. Roy 등에 의해 Appl. Phys. Letts., Vol. 72, No. 22, June1, 1998, pp. 2835-37에서 충분히 설명되었다면 참조에 의해 여기서 포함된다.Referring to Fig. 1, a silicon substrate 11 is shown with an electric field dielectric 12, and a titanium pentaoxide gate dielectric 13 formed by metal-organic chemical vapor deposition (MOCVD). Is shown. In a preferred application of the present invention, the gate dielectric layer is smaller than 10 nm and preferably smaller than 6 nm. This is an oxygen depletion problem [p is the most severe dimension of titanium pentaoxide dielectrics. Without wishing to be maintained with certain theories, oxygen loss can make stoichiometric titanium oxide, and the lost oxygen leaves hole carriers, which reduces the insulating area of titanium pentaoxide and increases the leakage current. Particularly preferred is the use of an accumulated titanium pentaoxide dielectric system in which silicon dioxide is first formed on silicon, followed by titanium pentaoxide, followed by another layer of silicon dioxide, each thickness of about 0.8 nm to 2 Nm, about 3 to about 30 nm, about 0.5 to about 2 nm. Accumulated titanium pentaoxide system is P.K. By Appl. Phys. Letts., Vol. 72, No. 22, June 1, 1998, pp. If fully described in 2835-37, incorporated herein by reference.
처리 순서에서 다음은 합성 게이트 전극(16)의 형성이다. 게이트 전극은 본 발명의 양호한 층의 구조에서, 구별되는 휴식(break)없이 하나로부터 다른 하나로 물질 전이와 전체 합성 게이트 전극이 단일 처리 동작을 필연적으로 만들도록 하는 사실을 알리도록 단일 고체 아웃라인으로 예시된다. 합성 게이트 전극은 게이트 유전체(13)상에 증착된 산소 확산 배리어으로 텅스텐 실리사이드 질화물층, WsixNy와, 텅스텐 실리사이드 질화물층(17)에 증착된 텅스텐 실리사이드층(18), WSix를 구비한다. 알루미늄 및 구리와 같은 다른 전기적 전도성 물질들은, 그러나 선호되는 WSix대신에, 또는 부가하여 증착될 수 있다. 합성 게이트 전극층을 형성하는데 있어서, 모든 층들은 나중에 설명되는 것처럼 하나의 순서 동작에서 증착된다.Next in the processing sequence is the formation of the composite gate electrode 16. The gate electrode is illustrated as a single solid outline in the preferred layered structure of the present invention to inform the fact that the material transition from one to the other and the entire composite gate electrode inevitably result in a single processing operation without distinct breaks. do. The composite gate electrode comprises a tungsten silicide nitride layer, Wsi x N y, and a tungsten silicide layer 18, WSi x deposited on the tungsten silicide nitride layer 17 as an oxygen diffusion barrier deposited on the gate dielectric 13. . Other electrically conductive materials, such as aluminum and copper, however, may be deposited instead of, or in addition to, the preferred WSi x . In forming the composite gate electrode layer, all the layers are deposited in one sequential operation as described later.
또 다른 실시예에서, WSI의 부착 계층(adhesion layer)은 전형적으로 각각 약 1에서 2nm, 약 5에서 30nm, 약 10에서 120nm의 두께를 가진 WSi, WSiN, WsI로 구성된 3 계층을 형성하기 위해 먼저 스택된 탄탈 5산화물(stacked tantalum pentoxide)위에 위치한다.In another embodiment, the adhesion layer of the WSI is typically first formed to form three layers of WSi, WSiN, WsI, each having a thickness of about 1 to 2 nm, about 5 to 30 nm, and about 10 to 120 nm, respectively. It is placed on stacked tantalum pentoxide.
합성 스택은 기능적 증감 물질(gradient meterial)로서 증작되고, 질소 및 실리콘은 텅스텐을 고려하여 매우 부드럽게 컨테트(content)하고, 계층들 사이를 예리하게 정의한 경계를 다소 가진다.Synthetic stacks are deposited as functional gradient materials, nitrogen and silicon content very smoothly in view of tungsten, with somewhat sharply defined boundaries between layers.
그러면, 합성 게이트 전극은 예를 들어, 종래의 RIE(reactive ion etching)에 의해 정의된다. 유전체(13)는 소스 드레인 영역(합성 게이트 전극(16)을 마스크로 사용하는)위의 영역으로부터 에치(etch)된 것으로서 도 1에 도시된다. 그러면, 소스 및 드레인(21 및 22)들은 종래의 이온 주입에 의해 형성된다. 대안으로, 유전체 계층은 장소에 남을 수 있고, 소스 및 드레인 주입물은 이식 마스크로서 복합 게이트 전극을 사용하여 유전체 계층을 통한다. p-채널 장치를 위해 불순물은 붕소이고, n-채널 장치를 위해 불순물은 전형적으로 비소이다. 몇몇 선행 기술 처리에서, 게이트 전극은 이식 단계 동안 노출되고, 불순물은 게이트 전도성을 높이기 위해 노출된 게이트 전극에 이식된다. 그러나, 본 발명의 합성 물질을 사용하여 게이트의 불순물은 필요하지 않고, 회피한다.The composite gate electrode is then defined, for example, by conventional reactive ion etching (RIE). The dielectric 13 is shown in FIG. 1 as etched from an area above the source drain region (using the synthetic gate electrode 16 as a mask). The sources and drains 21 and 22 are then formed by conventional ion implantation. Alternatively, the dielectric layer may remain in place and the source and drain implants pass through the dielectric layer using the composite gate electrode as a implantation mask. The impurity is boron for p-channel devices and the impurity is typically arsenic for n-channel devices. In some prior art processes, the gate electrode is exposed during the implantation step and impurities are implanted in the exposed gate electrode to increase the gate conductivity. However, impurities of the gate are not necessary and avoided using the synthetic material of the present invention.
소스/드레인의 형성 후, 인터레벨(interlevel) 유전체가 위치되고, 소스/드레인 컨텍트 윈도우는 석판술(lithography)을 통해 인터레벨 유전체에서 열리고, 게이트 전극 및 소스/드레인 영역에의 컨텍트는 텅스텐이나 알루미늄 플러그 혹은 스터드(stud)를 사용하여 제작된다. 그러면, 내부 컨텍트 물질 레벨은 증착되고, 패턴되고(도시하지 않음), 다른 인터레벨 유전체는 증착된다(도시하지 않음). 선택적으로 제 3 내부 컨텍트 레벨(도시하지 않음)은 형성된다. 소스 및 드레인 컨텍트는 도 1의 24 및 25에 개략적으로 도시된다. 본 단계의 마지막 시리즈는 IC 기술에서 표준화되고 여기서는 설명하지 않는다.After formation of the source / drain, an interlevel dielectric is placed, the source / drain contact window is opened in the interlevel dielectric via lithography, and the contacts to the gate electrode and source / drain regions are tungsten or aluminum. Manufactured using plugs or studs. Internal contact material levels are then deposited, patterned (not shown), and other interlevel dielectrics are deposited (not shown). Optionally, a third internal contact level (not shown) is formed. Source and drain contacts are schematically illustrated in 24 and 25 of FIG. 1. The final series of steps is standardized in IC technology and will not be described here.
본 발명의 문맥에서의 과정의 중요한 특징은 다중 계층 게이트 전극의 형성이다. 이것은 도 2-5와 연결하여 더욱 자세히 설명된다.An important feature of the process in the context of the present invention is the formation of a multi-layer gate electrode. This is explained in more detail in connection with Figures 2-5.
다중 게이트 전극을 형성하는 계층을 위한 양호한 증착 절차는 물리적 증기 증착(PVD) 즉, 스퍼터링(sputtering)이다. 텅스텐 실리사이드 계층은 감압된 내부 가스 환경에서 텅스텐 실리사이드 표적으로부터 스푸터된다. 질소 및 아르곤 게스에서의 반작용 스푸트링은 질화물 계층을 형성한다. 질소 하나만이 사용된다. 다중 계층 증착 단계들은 같은 증착 장치에서 PVD 장치에서 진공 상태를 파괴하지 않고 순서적으로 양호하게 수행된다. 본 설명의 목적을 위해, 이러한 방법으로 형성된 계층들은 "insitu"로 형성된다고 정의한다.A preferred deposition procedure for the layer forming the multiple gate electrode is physical vapor deposition (PVD), i.e. sputtering. The tungsten silicide layer is sputtered from the tungsten silicide target in a reduced pressure internal gaseous environment. Reaction sputtering in nitrogen and argon gas forms a nitride layer. Only one nitrogen is used. Multi-layer deposition steps are performed satisfactorily in order without breaking the vacuum in the PVD device in the same deposition device. For the purposes of this description, the layers formed in this way are defined to be formed "insitu".
PVD 프로세서 자신은 전통적인 것이고 어떤 적당한 PVD 장치에서 수행된다. PVD 장치의 개략도는 도 2에 도시된다. 진공실(27)은 웨이퍼(wafer)(35)를 지원하는 스푸트링 표적(29), 임의의 시준기(collimator)(31)(게스는 탑이나 바닥으로 부터 방에 주입된다.) 및 배양기 히터(substrate heater)(33)를 포함한다. 게스 흐름은 도면에서 지시되고 물질 계층을 스푸트링하기 위한 아르곤을 포함하고, 질화물 계층을 각각 스푸트링하기 위한 아르곤 더하기 질소를 포함한다.The PVD processor itself is traditional and runs on any suitable PVD device. A schematic diagram of a PVD device is shown in FIG. 2. The vacuum chamber 27 is a sputtering target 29 that supports a wafer 35, an optional collimator 31 (the guest is injected into the room from the top or the bottom) and the incubator heater ( substrate heater 33). The gas flow is indicated in the figure and includes argon for sputtering the material layer, and includes argon plus nitrogen for sputtering the nitride layer, respectively.
도 3을 참고하여, 실리콘 기판이 여기서 형성된 탄탈 팬트-옥시드 게이트 유전체 계층(42)과 함께 41에 도시된다. 저항적으로 가열된 서스셉터(susceptor) 혹은 히터나 아르곤과 가열된 후측(backside)의 사용(도시되지 않음)은 웨이퍼의 온도를 증가하기 위해 사용된다. 이러한 관점은 MOS 장치의 게이트/채널 영역이고, 필드 유전체는 나타나지 않는다. 게이트 전극 계층은 다음에 증착된다.Referring to FIG. 3, a silicon substrate is shown at 41 with the tantalum pant-oxide gate dielectric layer 42 formed here. A resistively heated susceptor or the use of a heater or argon and a heated backside (not shown) is used to increase the temperature of the wafer. This view is the gate / channel region of the MOS device, and no field dielectric appears. The gate electrode layer is then deposited.
도 4를 참고하여, 배리어층(43)은 계층(43)에 증착된 스퍼터이다. 질소를 PVD 리엑터에 부가하여 PVD 리엑터 에서의 양호한 "in situ"이다. 배리어 계층은 WSixNy이고, 다중 계층 게이트 전극 스택에서 방산(diffusion)으로 산소 손실을 미리 설명된 탄탈 팬트 옥시드로부터 막기위한 키 요소이다. 양호한 질소 흐름은 약 5에서 55sccm 사이, 아르곤 케리어 가스 흐름은 약 40에서 60sccm사이이다. 계층(43)의 실리사이드/질화물 물질은 전형적으로 높은 저항 물질이다. 질소 흐름 비율 및 계층의 결과 합성을 제어하는 것은 이 물질의 쉬트(sheet)저항을 제어할 수 있다. WSixNy배리어 계층을 위한 양호한 합성 범위는 약 5에서 30%N, 약 40에서 60% SI, 발란스 W 이다. 계층(44)의 양호한 두께는 약 50에서 300A의 범위이다. 질화물은 질소 흐름에 의존하는 질화물이나 비-질화물 모드에 증착된다. 이 증착 모드는 당업자에게 알려져있다.Referring to FIG. 4, the barrier layer 43 is a sputter deposited on the layer 43. Nitrogen is added to the PVD reactor to be a good "in situ" in the PVD reactor. The barrier layer is WSi x N y and is a key element to prevent oxygen loss from the previously described tantalum pant oxide with diffusion in the multi-layer gate electrode stack. Good nitrogen flow is between about 5 and 55 sccm and argon carrier gas flow is between about 40 and 60 sccm. The silicide / nitride material of layer 43 is typically a high resistance material. Controlling the nitrogen flow rate and the resulting synthesis of the strata can control the sheet resistance of the material. A good synthesis range for the WSi x N y barrier layer is about 5 to 30% N, about 40 to 60% SI, balance W. Preferred thicknesses of layer 44 range from about 50 to 300 A. FIG. Nitride is deposited in a nitride or non-nitride mode that is dependent on nitrogen flow. This deposition mode is known to those skilled in the art.
도 5의 44에 도시된 텅스텐 실리사이드층은 약 2보다 큰 Si 대 W 비로 WSIx 표적을 사용하여 PVD 반응기에서 증착된다. 양호하게 Si/W비는 약 2.5보다 크고, 가장 효과적인 범위는 2.5 내지 2.9이다. 층(44)은 약 25 내지 약 400℃의 범위에서 온도와 약 2 내지 약 6 mTorr의 범위의 압력에서 아르곤 대기에서 증착된다. 100 내지 1200Å의 범위에서 층(44)의 두께는 양호하게 약 600 내지 약 800Å이다.The tungsten silicide layer shown at 44 in FIG. 5 is deposited in a PVD reactor using a WSIx target with a Si to W ratio greater than about 2. Preferably the Si / W ratio is greater than about 2.5 and the most effective range is 2.5 to 2.9. Layer 44 is deposited in an argon atmosphere at a temperature in the range of about 25 to about 400 ° C. and a pressure in the range of about 2 to about 6 mTorr. The thickness of layer 44 in the range of 100 to 1200 mm 3 is preferably about 600 to about 800 mm 3.
예를 들어, 실리사이드는 디클로실레인(dichlorosilane)을 사용하여 형성될 수 있거나 또는 유사한 전조(precursor)이고, 질수의 소스를 제공하는 가스들에 부가하여 형성되는 실리콘 질화물층을 사용하여 형성될 수 있다.For example, the silicide may be formed using dichlorosilane or may be formed using a silicon nitride layer that is a similar precursor and formed in addition to gases providing a source of lean. have.
본 기술 분야에 숙련된 사람들은 본 발명의 다층 게이트 전극을 이용하는 장점을 알고 있다. 실리사이드에 대란 실리사이드-질화물의 다층 구조는 스트레스를 수용할 수 있는 합성적으로 그레이드-스택형으로 구성되어 있다. 그와 같은 구조에 대한 제조의 용이함은 종래의 기술에서 처럼 개별적인 도구로 폴리-실리콘을 증착시키는 비용 없이 하나의 단일 챔버에서 전체 게이트 전극 스택이 증착될 수 있다는 사실에 근거를 둔다. 또한, WSixNy는 장치가 열처리되면서 제조될 때 탄탈 펜트옥사이드의 산소 확산에 대한 훌륭한 배리어로서 역할을 한다. 이와 같은 배리어는 종래의 기술에 이용된 폴리-SI 또는 탄탈 질화물에 이용될 수 없다.Those skilled in the art know the advantages of using the multilayer gate electrode of the present invention. The multilayer structure of silicide-nitrides facing silicides is synthetically graded-stacked to accommodate stress. The ease of fabrication for such a structure is based on the fact that the entire gate electrode stack can be deposited in one single chamber without the cost of depositing poly-silicon with separate tools as in the prior art. WSixNy also serves as an excellent barrier to oxygen diffusion of tantalum pentoxide when the device is manufactured as it is heat treated. Such a barrier cannot be used for poly-SI or tantalum nitride used in the prior art.
본 발명의 여러 부가적인 변경안은 본 기술 분야에 숙련된 사람들에 의해 있을 수 있다, 본 명세서에 기재된 특정 기술에 대한 모든 변경은 본 기술이 본원의 명세서 및 특허 청구 범위 내에서 적당히 고려 및 향상될 수 있는 원리에 기본적으로 의존한다.Many additional modifications of the present invention can be made by those skilled in the art, and all changes to the specific technology described herein may be properly considered and improved by the technology within the specification and claims herein. It basically depends on the principle.
본 발명은 텅스텐 실리사이드 질화물층을 포함하고, 텅스텐 실리사이드 질화물/텅스텐 실리사이드는 탄탈 펜트옥사이드에서 산소 결핍 효과를 감소시킬 수 있다.The present invention includes a tungsten silicide nitride layer, and tungsten silicide nitride / tungsten silicide can reduce the oxygen deficiency effect in tantalum pentoxide.
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US9/209,787 | 1998-12-11 | ||
US09/209,787 US6339246B1 (en) | 1998-12-11 | 1998-12-11 | Tungsten silicide nitride as an electrode for tantalum pentoxide devices |
US09/209,787 | 1998-12-11 |
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JP2003282873A (en) * | 2002-03-22 | 2003-10-03 | Sony Corp | Semiconductor device and its fabricating method |
US20040135218A1 (en) * | 2003-01-13 | 2004-07-15 | Zhizhang Chen | MOS transistor with high k gate dielectric |
US20060091483A1 (en) * | 2004-11-02 | 2006-05-04 | Doczy Mark L | Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode |
US20060267113A1 (en) * | 2005-05-27 | 2006-11-30 | Tobin Philip J | Semiconductor device structure and method therefor |
US10164044B2 (en) * | 2015-04-16 | 2018-12-25 | Micron Technology, Inc. | Gate stacks |
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JP3294041B2 (en) * | 1994-02-21 | 2002-06-17 | 株式会社東芝 | Semiconductor device |
US5576579A (en) * | 1995-01-12 | 1996-11-19 | International Business Machines Corporation | Tasin oxygen diffusion barrier in multilayer structures |
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