KR20000045863A - Method for forming multilayer copper interconnect of semiconductor device - Google Patents
Method for forming multilayer copper interconnect of semiconductor device Download PDFInfo
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- KR20000045863A KR20000045863A KR1019980062459A KR19980062459A KR20000045863A KR 20000045863 A KR20000045863 A KR 20000045863A KR 1019980062459 A KR1019980062459 A KR 1019980062459A KR 19980062459 A KR19980062459 A KR 19980062459A KR 20000045863 A KR20000045863 A KR 20000045863A
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- 238000000034 method Methods 0.000 title claims abstract description 61
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 44
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 43
- 239000010949 copper Substances 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 229910008482 TiSiN Inorganic materials 0.000 claims abstract description 29
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims abstract description 29
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract description 5
- 238000005121 nitriding Methods 0.000 claims description 18
- 239000003963 antioxidant agent Substances 0.000 claims description 7
- 230000003078 antioxidant effect Effects 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 239000012298 atmosphere Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000003064 anti-oxidating effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 42
- 230000003405 preventing effect Effects 0.000 abstract description 8
- 239000000463 material Substances 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 abstract description 2
- 230000001546 nitrifying effect Effects 0.000 abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 description 9
- 150000001875 compounds Chemical class 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 229910004200 TaSiN Inorganic materials 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910008807 WSiN Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 125000001301 ethoxy group Chemical group [H]C([H])([H])C([H])([H])O* 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
Description
본 발명은 반도체장치의 금속 배선 형성방법에 관한 것으로서, 특히 비저항이 작으며 신뢰성이 우수한 구리를 금속 배선용으로 이용할 때 구리 배선의 확산을 방지함으로써 구리 배선 공정의 신뢰성을 높일 수 있는 반도체소자의 다층 구리 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device. In particular, multilayer copper of a semiconductor device capable of increasing the reliability of a copper wiring process by preventing the diffusion of copper wiring when a copper having a low specific resistance and high reliability is used for metal wiring. It relates to a wiring forming method.
통상적으로 금속 배선으로 널리 사용되는 금속으로는 텅스텐, 알루미늄 및 알루미늄 합금 등이 있었다. 이 금속들은 비교적 용이하게 식각되므로 금속 배선을 형성하기 위하여 전면(blanket) 증착, 노광 및 식각 공정 등의 일련의 공정들을 거치게 된다.Typically, tungsten, aluminum, aluminum alloy, and the like are widely used as metal wirings. Since these metals are relatively easily etched, they go through a series of processes, such as blanket deposition, exposure and etching processes, to form metal interconnects.
최근에는, 반도체 소자가 점점 고집적화됨에 따라 금속 배선공정시 통상적으로 사용된 텅스텐, 알루미늄에 대비하여 비저항이 작으며 반도체 소자의 성능 향상, 예를 들어 RC 지연시간 감소와 신뢰성 향상에 유리한 장점을 가지고 있는 구리를 금속 배선 재료로 대체하고자 많은 연구가 이루어지고 있다.In recent years, as semiconductor devices have been increasingly integrated, their resistivity is lower than that of tungsten and aluminum, which are commonly used in metal wiring processes, and have advantages in improving the performance of semiconductor devices, for example, reducing RC delay time and improving reliability. Much research is being done to replace copper with metallization materials.
한편, 반도체 소자의 고집적화는 스텝 커버리지 및 비아(또는 콘택홀) 매립 특성이 좋지 않을 경우 금속 배선이 단락되거나 신뢰성이 저하되기 때문에 구리 이중 상감 공정에서의 콘택홀 매립 특성을 향상시킬 수 있는 구리(Cu) 증착 공정이 요구되고 있으나, 종래 금속 배선 형성시 예를 들어 알루미늄(Al) 배선의 경우 알루미늄의 확산을 방지하기 위해 사용되는 TiN을 구리 배선 공정시에도 이용할 경우 TiN막내의 구리 확산 계수가 높아진다.On the other hand, the high integration of the semiconductor device may improve the contact hole filling characteristics in the copper double damascene process because the metal wiring is shorted or the reliability is deteriorated when the step coverage and the via (or contact hole) filling characteristics are poor. Although a deposition process is required, the diffusion coefficient of copper in the TiN film is increased when TiN, which is used to prevent the diffusion of aluminum, is also used in the copper wiring process.
그러므로, 구리 배선 공정시 구리 확산을 방지하기 위한 새로운 재료적인 연구가 진행되고 있는데, 그 중에서도 TaN, WNx 등의 이원계 확산 방지물질과 TiSiN, WSiN, TaSiN 등의 삼원계 확산 방지물질이 연구중에 있다.Therefore, new material researches for preventing copper diffusion in the copper wiring process are being conducted. Among them, binary diffusion preventing materials such as TaN and WNx and ternary diffusion preventing materials such as TiSiN, WSiN and TaSiN are being studied.
그러나, 확산 방지 특성이 우수한 삼원계 확산 방지막의 경우 질화막 제조 기술은 화합물 타겟을 반응성 스퍼터링 방법으로 제조하고 있는데, 삼원계 화합물의 경우 제 2의 원소인 실리콘(Si)양이 5∼10% 이상일 경우 비저항이 1mΩ-㎝ 이상으로 증가되어 이를 적용하는데 어려움이 있다.However, in the case of the tertiary diffusion barrier layer having excellent diffusion preventing properties, the nitride film fabrication technique manufactures the compound target by the reactive sputtering method. In the case of the tertiary compound, when the amount of silicon (Si) which is the second element is 5-10% or more, The specific resistance is increased to 1 mΩ-cm or more, which makes it difficult to apply.
본 발명의 목적은 구리 배선의 확산 방지용으로 TaSiN의 삼원계 물질을 형성하기 위하여 TaSix 박막을 증착하고 질화처리를 실시함으로써 저저항을 갖는 구리배선의 전기적 특성을 향상시킬 수 있는 반도체소자의 다층 구리 배선 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to deposit a TaSix thin film and perform nitriding to form a TaSiN ternary material for preventing diffusion of copper wiring, thereby increasing the electrical properties of a copper wiring having low resistance. It is to provide a formation method.
도 1 내지 도 4는 본 발명에 따른 반도체소자의 다층 구리 배선 형성방법을 순서적으로 설명하기 위한 공정순서도이다.1 to 4 are process flowcharts for sequentially explaining a method for forming a multilayer copper wiring of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 반도체기판 12: 활성 영역10: semiconductor substrate 12: active region
20: 하부 층간절연막 22: 상부 층간절연막20: lower interlayer insulating film 22: upper interlayer insulating film
30: 제 1 TiSiN막 32, 38: 구리30: first TiSiN film 32, 38: copper
34, 40: 산화방지막 36: 제 2 TiSiN막34, 40: antioxidant film 36: second TiSiN film
상기 목적을 달성하기 위하여 본 발명의 제조 방법은 반도체소자의 다층 구리 배선 형성 방법에 있어서, 반도체 소자의 활성 영역이 노출되도록 평탄화된 하부 층간절연막에 콘택홀을 형성하는 단계와, 콘택홀이 형성된 층간절연막 상부에 TaSi을 증착하고 고온의 질화 공정을 실시하여 제 1 TiSiN막을 형성하는 단계와, 제 1 TiSiN막 상부에 콘택홀을 채우도록 구리를 증착하여 하부 배선을 형성하고 그 위에 산화방지막을 형성하는 단계와, 상기 결과물에 상부 층간절연막을 형성하고 상부 층간절연막내에 하부 배선의 일부가 개방되도록 비아를 형성하는 단계와, 비아 위에 TaSi를 증착하고 저온 질소분위기에서 질화처리를 실시하여 제 2 TiSiN막을 형성하는 단계와, 제 2 TiSiN막 상부에 콘택홀을 채우도록 구리를 증착하여 상부 배선을 형성하고 그 위에 산화방지막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a multilayer copper interconnection of a semiconductor device, the method comprising: forming a contact hole in a lower interlayer insulating film planarized to expose an active region of a semiconductor device, and forming an interlayer with a contact hole Depositing TaSi on the insulating film and performing a high temperature nitriding process to form a first TiSiN film; and depositing copper so as to fill a contact hole on the first TiSiN film to form a lower wiring and an antioxidant film thereon; Forming a second TiSiN film by forming an upper interlayer insulating film on the resultant, forming a via so that a portion of the lower wiring is opened in the upper interlayer insulating film, depositing TaSi on the via and performing nitriding in a low temperature nitrogen atmosphere. And depositing copper to fill the contact hole on the second TiSiN film to form an upper wiring and oxidizing thereon. It characterized in that made in a step of forming a final.
본 발명의 제조 방법에 있어서, 제 1 TiSiN막을 형성하기 전에 Ti을 10∼100Å으로 증착하는 단계를 더 포함하도록 한다.In the manufacturing method of the present invention, the method further comprises depositing Ti at 10 to 100 GPa before forming the first TiSiN film.
바람직하게는 본 발명의 TaSi의 증착은 스퍼터링 내지 화학기상증착 공정을 이용하며 TaSi의 두께를 50∼1000Å으로 한다.Preferably, the deposition of TaSi of the present invention uses a sputtering to chemical vapor deposition process, and the thickness of TaSi is 50 to 1000 Pa.
더 바람직하게는 본 발명의 제 1 TiSiN막 형성을 위한 콘택홀 위의 TaSi에 실시되는 질화처리 공정은 퍼니스 어닐링 내지 급속 열공정을 이용하며 N2내지 NH3가스를 사용하며 650∼900℃의 온도 조건으로 진행한다.More preferably, the nitriding process performed on TaSi on the contact hole for forming the first TiSiN film of the present invention uses a furnace annealing to rapid thermal process, uses N 2 to NH 3 gas, and has a temperature of 650 to 900 ° C. Proceed to condition.
더욱 바람직하게는 본 발명의 제 2 TiSiN막 형성을 위한 비아 위의 TaSi에 실시되는 질화처리 공정은 0∼500℃의 온도 조건에서 진행하며 N2내지 NH3가스분위기에서 플라즈마공정을 실시한다.More preferably, the nitriding process performed on TaSi on the via for forming the second TiSiN film of the present invention is carried out at a temperature condition of 0 to 500 ° C. and the plasma process is performed in an N 2 to NH 3 gas atmosphere.
또한, 본 발명의 산화 방지막은 TiN, TaN 및 WN 중의 어느 하나를 이용하여 형성한다.In addition, the antioxidant film of this invention is formed using any one of TiN, TaN, and WN.
그러므로, 본 발명에 따른 기술적 원리를 살펴보면, 임의의 조성비를 갖는 TaSix 화합물을 증착한 다음 질소 분위기에서 750∼800℃의 열처리 또는 저온의 플라즈마 처리하여 TaySixNz의 삼원계 화합물을 형성한다. 이때, x,y의 조성 영역은 초기 타겟 화합물의 조성에 의존하며 z는 질화처리시의 공정변수(온도, 유량, 플라즈마 조건)에 달려 있는데, 예를 들어 TaSix 타겟의 x가 2일 때 TaSi2가 되며 이때의 벌크 비저항은 18∼25Ω-㎝으로 매우 낮다.Therefore, looking at the technical principle according to the present invention, TaSix compound having an arbitrary composition ratio is deposited and then thermally treated at a temperature of 750-800 ° C. or plasma at low temperature to form a tertiary compound of Ta y Si x N z . . At this time, the composition region of x, y depends on the composition of the initial target compound and z depends on the process variables (temperature, flow rate, plasma conditions) during the nitriding treatment, for example, TaSi 2 when x of the TaSix target is 2 The bulk resistivity at this time is very low, 18-25 Ω-㎝.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따른 반도체소자의 다층 구리 배선 형성방법을 순서적으로 설명하기 위한 공정순서도이다.1 to 4 are process flowcharts for sequentially explaining a method for forming a multilayer copper wiring of a semiconductor device according to the present invention.
우선, 도 1에 도시된 바와 같이 반도체기판(10)에 통상의 소자 제조 공정을 진행한 후에 반도체 소자간을 연결하기 위한 금속 배선 공정을 실시한다. 이에, 반도체기판(10) 상부에 있는 하부 층간절연막(20)을 선택적으로 식각해서 기판의 소정 활성 영역이 노출되는 콘택홀을 형성한다. 그 다음, 스퍼터링 내지 화학기상증착 공정을 이용하여 하부 층간절연막(20) 상부에 TaSix를 50∼1000Å의 두께로 증착하고 고온의 질화 공정을 실시함으로써 TaSi이 TaSiN 삼원계 물질로 변형된 제 1 TiSiN막(30)을 형성한다. 화학기상증착 공정으로 TaSix를 증착할 경우에는 Ta의 소스로서 TaCl4또는 PET(Penta Ethoxy TantalAte): Ta(C2H5)5를 사용하며 Si의 소스로서 SiH4또는 Si2H6을 사용하며 동시에 H2와 Ar을 사용하기도 한다. 이때 기판의 온도는 100∼800℃로 한다. 또한 질화 공정은 퍼니스 어닐링(furnace annealing) 내지 급속 열공정(rapid thermal annealing)을 이용하며 N2내지 NH3가스를 사용하며 650∼900℃의 온도 조건으로 진행한다.First, as shown in FIG. 1, after the normal device manufacturing process is performed on the semiconductor substrate 10, a metal wiring process for connecting the semiconductor devices is performed. Accordingly, the lower interlayer insulating layer 20 on the semiconductor substrate 10 is selectively etched to form a contact hole through which a predetermined active region of the substrate is exposed. Then, the first TiSiN film in which TaSi is transformed into a TaSiN ternary material by depositing TaSix to a thickness of 50 to 1000 GPa on the lower interlayer insulating film 20 by using a sputtering or chemical vapor deposition process and performing a high temperature nitriding process. 30 is formed. When depositing TaSix by chemical vapor deposition, TaCl 4 or PET (Penta Ethoxy TantalAte): Ta (C 2 H 5 ) 5 is used as the source of Ta, and SiH 4 or Si 2 H 6 is used as the source of Si. At the same time, H 2 and Ar may be used. At this time, the temperature of the board | substrate shall be 100-800 degreeC. In addition, the nitriding process uses furnace annealing to rapid thermal annealing and uses N 2 to NH 3 gas and proceeds at a temperature of 650 to 900 ° C.
이어서, 도 2에 도시된 바와 같이 제 1 TiSiN막(30) 상부에 콘택홀을 채우도록 구리를 증착하여 하부 배선(32)을 형성한다. 이때, 구리 증착공정은 화학기상증착법, 전기도금(electro-plating) 또는 이온화된 구리 스퍼터링(ionized Cu-sputtering)방법을 이용한다. 그리고, 하부 배선(32)의 구리의 표면산화를 방지하고자 인트(in situ)로 TiN, TaN 및 WN 중에서 어느 한 물질을 선택하여 하부 배선(32) 위에 증착해서 산화방지막(32)을 형성한다.Subsequently, as shown in FIG. 2, copper is deposited to fill the contact hole on the first TiSiN film 30 to form the lower wiring 32. At this time, the copper deposition process uses a chemical vapor deposition method, electroplating (electro-plating) or ionized copper sputtering (ionized Cu-sputtering) method. In order to prevent surface oxidation of copper of the lower interconnection 32, any one of TiN, TaN, and WN is selected as an in situ and deposited on the lower interconnection 32 to form an antioxidant layer 32.
그 다음 도 3에 도시된 바와 같이, 상기 결과물에 절연물질을 증착하고 이를 평탄화하여 상부 층간절연막(22)을 형성한 후에 사진 및 식각 공정으로 상기 하부배선(32)의 일부가 개방되도록 비아를 형성한다. 그 위에 TaSix를 증착하고 저온 질소분위기에서 질화처리를 실시하여 제 2 TiSiN막(36)을 형성한다. 이때, 질화처리 공정은 0∼500℃의 온도 조건에서 진행하며 N2내지 NH3가스분위기에서 플라즈마공정을 이용한다.Next, as shown in FIG. 3, an insulating material is deposited on the resultant and planarized to form an upper interlayer insulating layer 22, and then a via is formed to open a portion of the lower wiring 32 by a photo and etching process. do. TaSix is deposited thereon and nitrided in a low temperature nitrogen atmosphere to form a second TiSiN film 36. At this time, the nitriding process is carried out at a temperature condition of 0 ~ 500 ℃ and using a plasma process in the N 2 to NH 3 gas atmosphere.
계속해서 도 4에 도시된 바와 같이 제 2 TiSiN막(36) 상부에 콘택홀을 채우도록 구리를 증착하여 상부 배선(38)을 형성하고 그 위에 구리의 표면 산화를 방지하기 위하여 산화방지막(40)을 형성한다.Subsequently, as shown in FIG. 4, copper is deposited to fill the contact hole on the second TiSiN film 36 to form the upper wiring 38, and the antioxidant film 40 is formed thereon to prevent surface oxidation of the copper thereon. To form.
본 발명의 다층 구리 배선 형성방법에서, 제 1 TiSiN막(30)을 형성하기 전에 Ti을 10∼100Å으로 증착하여 활성 영역(12)의 자연 산화막을 제거할 수 있다. 그리고, 하부 배선 및 상부배선의 영역 확보를 위한 콘택홀 내지 비아 형성시 통상의 듀얼 데마신(dual damascene) 공정을 이용할 수도 있다.In the method of forming the multilayer copper wiring of the present invention, before forming the first TiSiN film 30, Ti may be deposited at 10 to 100 kV to remove the native oxide film of the active region 12. In addition, a conventional dual damascene process may be used when forming contact holes or vias for securing the area of the lower wiring and the upper wiring.
또한, 본 발명에서 막을 형성하고자 실시되는 질화공정시 고온의 열공정을 통한 TaSiN의 형성은 구리배선이 기판의 활성영역과 연결될 때 적용이 가능하며, 저온 플라즈마를 통한 질화처리는 종말처리 공정의 TaSiN의 형성에 적합하다.In addition, the formation of TaSiN through a high temperature thermal process during the nitriding process performed to form a film in the present invention can be applied when copper wiring is connected to the active region of the substrate, and nitriding through low temperature plasma is TaSiN in the terminal treatment process. Suitable for the formation of
그러므로, 본 발명은 임의의 조성비를 갖는 TaSix 화합물을 증착한 다음 질소 분위기에서 750∼800℃의 열처리 또는 저온의 플라즈마 처리하여 TaySixNz의 삼원계 화합물로 이루어진 TiSiN막(30,36)을 형성한다. 이때, x,y의 조성 영역은 초기 타겟 화합물의 조성에 의존하며 z는 질화처리시의 공정변수(온도, 유량, 플라즈마 조건)에 달려 있으며, 예를 들어 TaSix 타겟의 x가 2일때 TaSi2가 되며 이때의 벌크 비저항은 18∼25Ω-㎝으로 매우 낮다.Therefore, the present invention provides a TiSiN film (30, 36) made of a ternary compound of Ta y Si x N z by depositing a TaSix compound having an arbitrary composition ratio and then performing a heat treatment at 750 to 800 ° C. or a low temperature plasma treatment in a nitrogen atmosphere. To form. At this time, the composition region of x, y depends on the composition of the initial target compound and z depends on the process variables (temperature, flow rate, plasma conditions) during the nitriding treatment. For example, when Ta of the TaSix target is 2, TaSi 2 is The bulk resistivity at this time is very low, 18-25 Ω-cm.
상기한 바와 같이 본 발명은, 반도체소자의 고밀도화와 신호전달 속도의 향상에 따라 RC지연 시간의 최소화를 위한 구리 배선 형성시 구리 원자가 하부의 절연막 내지 기판으로 확산되는 것을 방지하고자 구비 배선 형성 전에 비저항이 낮은 TaSiN막을 추가 증착함으로써 고온에서도 안정된 구리 배선을 확보할 수 있으며 다층 구리 배선의 전기적 특성 저하를 방지할 수 있는 장점을 가지고 있다.As described above, according to the present invention, in order to prevent copper atoms from diffusing into an insulating layer or a substrate under the formation of a copper wiring for minimizing the RC delay time according to the increase in the density of the semiconductor device and the improvement of the signal transmission speed, the resistivity before forming the wiring is provided. By further depositing a low TaSiN film, it is possible to secure stable copper wiring even at high temperatures and to prevent deterioration of electrical characteristics of the multilayer copper wiring.
Claims (6)
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