KR20000045436A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20000045436A
KR20000045436A KR1019980061994A KR19980061994A KR20000045436A KR 20000045436 A KR20000045436 A KR 20000045436A KR 1019980061994 A KR1019980061994 A KR 1019980061994A KR 19980061994 A KR19980061994 A KR 19980061994A KR 20000045436 A KR20000045436 A KR 20000045436A
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South Korea
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gmos
lvtgmos
field transistor
npn
stack structure
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KR1019980061994A
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Korean (ko)
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황윤택
배세열
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김영환
현대전자산업 주식회사
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Priority to KR1019980061994A priority Critical patent/KR20000045436A/en
Publication of KR20000045436A publication Critical patent/KR20000045436A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A semiconductor device is provided to improve an electrostatic discharge character by providing an electrostatic discharge preventing circuit for protecting inner elements of the semiconductor device. CONSTITUTION: A semiconductor device has a p-well formed on a semiconductor substrate. First isolation layers(31,41,51) are defined by GMOS(500) and LVTGMOS(600). A p-well pickups(33,43,53) are disposed at an outside of the first isolation layer(31,41,51). Second isolation layers(35,45,55) are disposed at an outside of the p-well pickup(33,43,53) and n-well guard rings(37,47,57) are provided at an outside of the other isolation layers. A series stack structure of GMOS(500) and LVTGMOS(600) is provided. The semiconductor device has a PNP field transistor in which a Vcc is connected between the series stack structure and a pad(400) and a NPN field transistor in which a Vcc is connected between the series stack structure and the pad(400).

Description

반도체소자Semiconductor device

본 발명은 정전기 방전 ( electro static discharge, 이하 ESD 라 함 ) 보호 회로가 구비되는 반도체소자에 관한 것으로, 특히 ESD 재핑 ( zapping ) 시 갑자기 많은 전류가 인가되어서 집적회로의 내부회로에 손상을 주는 현상을 막기 위하여, ESD 보호회로에서 들어온 전하들을 효과적으로 클램핑 ( clammping ) 하여 ESD 특성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with an electrostatic discharge (ESD) protection circuit, and in particular, a phenomenon in which an internal circuit of an integrated circuit is damaged by suddenly applying a large amount of current during ESD zapping. In order to prevent the present invention, the present invention relates to a technique capable of effectively clamping charges coming from an ESD protection circuit to improve ESD characteristics.

일반적인 MOS 회로는 내부적으로 2.5 ∼ 5 볼트 내외의 전압으로 동작하게 설계되어 있다. 그러나, 그들은 여러 원인등으로 인해 그 이상의 높은 전압에 노출된 경우가 발생하게 되는데, 이러한 상황에서는 MOS 소자의 게이트산화막 파괴 현상, 접합 스파이크 ( junction spiking ) 현상등이 발생되어 소자가 완전히 파괴되거나 혹은 미세하게 손상을 받아 누설전류의 발생으로 신뢰성에 심각한 영향을 주게 된다.Typical MOS circuits are designed to operate internally at voltages of around 2.5 to 5 volts. However, they may be exposed to higher voltages due to various causes, such as gate oxide breakdown of the MOS device, junction spiking, or the like, and the device is completely destroyed or fine. This damage is seriously affected by the leakage current.

상기한 바와같이 높은 전압에 대한 반도체소자의 노출은 여러가지 원인이 있을 수가 있는데 그 중 대표적인 것이 우리가 소자를 손으로 다룰때 사람몸에서 발생되는 정전기가 소자로 흘러 들어가는 경우다. 일반적으로 사람몸에서는 2000 ∼ 수만 볼트의 정전기 전압이 발생한다.As described above, the exposure of a semiconductor device to high voltages can have various causes. One of them is a case in which static electricity generated in the human body flows into the device when we handle the device by hand. In general, the human body generates an electrostatic voltage of 2000 to tens of thousands of volts.

한편, 또 한가지는 반도체소자를 어떠한 장비나 소켓 ( socket ) 등에 꽂을때 그 장비의 접지상태가 불안정하면 순간적으로 전하가 핀을 타고 소자로 흘러 들어가게 될 것이다.On the other hand, when the semiconductor device is plugged into any equipment or socket, if the grounding state of the equipment is unstable, electric charge will flow to the device through the pin.

위에서 서술한 바와같이 사용자가 주의하지 않으면 반도체소자는 언제든지 정전기 등과 같은 유익하지 않은 고전압에 항상 노출될 위험성이 있다.As described above, if the user is not careful, the semiconductor device is always exposed to unfavorable high voltage such as static electricity.

이러한 정전기 피해를 막기 위하여 핸들링 ( handling ) 할때 안티-스테틱 튜브 ( anti-static tube ) 를 사용하거나 접지 밴드를 착용한채 핸들링하는 등 최소한의 예방을 할 수 있으나, 궁극적으로는 정전기 방지용 회로를 회로의 입력단 ( 게이트단) 에 앞서 구성하여야 한다.In order to prevent such static damage, it is possible to minimize the handling such as using anti-static tube or handling with grounding band when handling. It must be configured before the input terminal (gate stage) of.

최근들어, 반도체소자는 소자의 고집적화에 따라 두께가 점점 더 얇아져 보다 높은 ESD 내성을 필요로 하고 정전기 방전에 의한 영향을 더욱 더 심하게 받는다.In recent years, semiconductor devices have become thinner and thinner with higher integration, which requires higher ESD resistance and is more severely affected by electrostatic discharge.

그리고, 상기 ESD 는 메모리소자의 셀부에 비하여 훨씬 큰 디자인룰에 의하여 디자인되어 그에 따른 반도체소자의 고집적화를 더욱 어렵게 한다.In addition, the ESD is designed by a much larger design rule than the cell portion of the memory device, thereby making it more difficult to integrate the semiconductor device.

도 1 및 도 2 는 종래기술에 따른 반도체소자를 도시한 것으로, 도 1 은 GMOS 와 VLTGMOS 가 직렬로 연결된 시리즈 스택 ( series stack ) 구조의 ESD 방전 보호 회로도이고, 도 2 는 상기 도 1 의 레이아웃도이다.1 and 2 illustrate a semiconductor device according to the prior art, FIG. 1 is an ESD discharge protection circuit diagram of a series stack structure in which GMOS and VLTGMOS are connected in series, and FIG. 2 is a layout diagram of FIG. to be.

상기 도 2 는 GMOS (200)드레인과 LVTGMOS (300)로 연결된 시리즈 스택 구조의 ESD 보호회로의 레이아웃을 도시한 것으로서, 폐곡선 형태로 일정범위를 갖는 엔웰 가아드링(25)이 구비되고, 상기 엔웰 가아드링(25)의 내측으로 제2소자분리막(23), 피웰 픽업(21), 제1소자분리막(13)의 순서로 각각 구비되고, 상기 제1소자분리막(13) 영역 내에 GMOS(200)와 LVTGMOS(300)이 각각 구비되고, 상기 엔웰 가아드링(25) 내측에 포함된 부분과 상관없이 패드(100)가 구비된다. (도 2)FIG. 2 illustrates a layout of an ESD protection circuit having a series stack structure connected by a drain of the GMOS 200 and the LVTGMOS 300, and includes an enwell guard ring 25 having a predetermined range in a closed curve shape. The second device isolation layer 23, the pewell pick-up 21, and the first device isolation layer 13 are provided in the order of the inside of the dring 25, respectively, and the GMOS 200 and the GMOS 200 may be disposed in the region of the first device isolation layer 13. LVTGMOS (300) is provided respectively, the pad 100 is provided irrespective of the portion contained inside the enwell guard ring (25). (Figure 2)

이상에서 설명한 바와같이 종래기술에 따라 ESD 보호회로가 구비되는 반도체소자는, ESD 재핑시 GMOS 의 드레인영역에 과전류가 흐르게 되어 반도체소자의 ESD 레벨를 낮추고 그에 따른 반도체소자의 특성 및 신뢰성을 저하시킬 수 있는 문제점이 있다.As described above, in the semiconductor device having the ESD protection circuit according to the related art, an overcurrent flows in the drain region of the GMOS during the ESD zapping, thereby lowering the ESD level of the semiconductor device and thus degrading the characteristics and reliability of the semiconductor device. There is a problem.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, GMOS 와 LVTGMOS 가 직렬로 연결된 스택구조과 패드 사이에 Vss 가 연결된 NPN 필드 트랜지스터와 Vcc 가 연결된 PNP 필드 트랜지스터가 연결되어 하나의 전류통로를 형성함으로써 과도전류에 의한 ESD 특성 저하를 방지하는 반도체소자를 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, an NPN field transistor connected with Vss and a PNP field transistor connected with Vcc are connected between a stack structure and a pad in which GMOS and LVTGMOS are connected in series to form a single current path. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that prevents degradation of ESD characteristics caused by current.

도 1 은 종래기술에 따른 정전기 방전 보호 회로를 도시한 회로도.1 is a circuit diagram showing a static discharge protection circuit according to the prior art.

도 2 는 도 1 에 따른 정전기 방전 보호회로를 도시한 레이아웃도.2 is a layout showing the electrostatic discharge protection circuit according to FIG.

도 3 은 본 발명에 따른 정전기 방전 보호 회로를 도시한 회로도.3 is a circuit diagram showing an electrostatic discharge protection circuit according to the present invention.

도 4 는 도 3 에 따른 정전기 방전 보호 회로를 도시한 레이아웃도.4 is a layout showing the electrostatic discharge protection circuit according to FIG.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

21,31,41,51 : 제1소자분리막21,31,41,51: first device separation membrane

23,33,43,53 : 피웰 픽업 ( p-well pick-up )23,33,43,53: p-well pick-up

25,35,45,55 : 제2소자분리막25,35,45,55: second device separation membrane

27,37,47,57 : 엔웰 가아드링 ( n-type guardring )27,37,47,57: n-type guardring

60 : NPN 필드 트랜지스터의 드레인60: drain of NPN field transistor

70 : NPN 필드 트랜지스터의 소오스70: source of NPN field transistor

80 : PNP 필드 트랜지스터의 드레인80: drain of PNP field transistor

90 : PNP 필드 트랜지스터의 소오스90: source of PNP field transistor

100,400 : 패드 200,500 : GMOS100,400: Pad 200,500: GMOS

300,600 : LVTGMOS300,600: LVTGMOS

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자는,In order to achieve the above object, a semiconductor device according to the present invention,

GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와 패드 사이에 별도의 전류통로가 구비되는 반도체소자에 있어서,A semiconductor device having a separate current path between a pad and a series stack structure connected by GMOS and LVTGMOS,

반도체기판 상에 형성된 피웰과,A pewell formed on the semiconductor substrate,

상기 GMOS 와 LVTGMOS 가 이격되어 형성된 섬형태의 제1소자분리막과,An island-shaped first device isolation layer formed by separating the GMOS and LVTGMOS;

상기 섬형태의 소자분리막의 외측에 구비되는 피웰 픽업과,A pewell pick-up provided outside the island-type device isolation film;

상기 피웰 픽업의 외측에 구비되는 제2소자분리막과,A second device isolation film provided outside the pewell pickup;

상기 다른 소자분리막의 외측에 구비되는 엔웰 가아드링과,An enwell guard ring provided at an outer side of the other device isolation film;

상기 GMOS 드레인 영역에 접속되는 패드로 구비되는 GMOS 와 LVTGMOS 의 시리즈 스택 구조와,A series stack structure of GMOS and LVTGMOS provided with pads connected to the GMOS drain region,

상기 GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와 상기 패드 사이에 Vcc 가 연결된 PNP 필드 트랜지스터와,A PNP field transistor having Vcc connected between the pad and the series stack structure connected by the GMOS and the LVTGMOS,

상기 GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와 상기 패드 사이에 Vss 가 연결된 NPN 필드 트랜지스터로 구비되어 별도의 전류통로가 포함되는 것과,A series stack structure connected by the GMOS and the LVTGMOS and an NPN field transistor having Vss connected between the pads to include a separate current path;

상기 GMOS 와 LVTGMOS 는 10 ∼ 30 ㎛ 의 거리가 유지되는 것과,The GMOS and LVTGMOS is maintained at a distance of 10 to 30 ㎛,

상기 GMOS 드레인과 웰 픽업은 10 ∼ 30 ㎛ 의 거리가 유지되는 것과,The GMOS drain and the well pickup is maintained at a distance of 10 to 30 ㎛,

상기 GMOS 와 LVTGMOS 사이에 활성영역 안쪽으로 NSD 임플란트된 것과,NSD implant into the active region between the GMOS and LVTGMOS,

상기 NPN 필드 트랜지스터와 PNP 필드 트랜지스터는 각각 두개의 소오스 노드가 Vss, Vcc 로 연결되는 것과,The NPN field transistor and the PNP field transistor are each connected with two source nodes Vss and Vcc,

상기 NPN 필드 트랜지스터의 드레인영역에 피웰 대신 엔웰이 구비되는 것과,An enwell is provided in the drain region of the NPN field transistor instead of a pewell;

상기 NPN 필드 트랜지스터의 드레인영역에서 금속콘택과 엔웰 가아드링 사이의 스페이스가 10 ∼ 20 ㎛ 인 것과,A space between the metal contact and the enwell guard ring in the drain region of the NPN field transistor is 10 to 20 µm,

상기 NPN 과 PNP 필드 트랜지스터의 드레인영역에서 금속콘택이 2로우이상으로 되고, 금속콘택과 활성영역이 2 ∼ 4 ㎛ 중첩되어 전류를 분산시키는 것과,The metal contact becomes 2 rows or more in the drain region of the NPN and the PNP field transistor, and the metal contact and the active region overlap with each other by 2 to 4 µm to disperse current;

상기 NPN 필드 트랜지스터의 드레인 부분에 폴리실리콘이나 실리사이드로 버퍼층이 구비되는 것을 특징으로 한다.A drain layer of the NPN field transistor may be provided with a buffer layer made of polysilicon or silicide.

한편, 이상의 목적을 달성하기 위한 본 발명의 원리는,On the other hand, the principle of the present invention for achieving the above object,

GMOS 와 LVTGMOS 사이와, GMOS 드레인영역과 웰 픽업 사이에서의 기생 바이폴라 트랜지스터에 의한 GMOS 드레인에서의 과도전류를 막아주기 위하여, 상기 GMOS 와 LVTGMOS 사이와, GMOS 드레인영역과 웰 픽업 사이의 거리를 10 ∼ 30 ㎛ 정도로 유지하고,In order to prevent transient currents in the GMOS drain between the GMOS and the LVTGMOS and between the GMOS drain region and the well pickup by the parasitic bipolar transistor, the distance between the GMOS and the LVTGMOS and between the GMOS drain region and the well pick-up is 10 to 10%. Kept at about 30 μm,

상기 GMOS 와 LVTGMOS 의 시리즈 스택 구조와 패드 사이에 Vcc 가 연결된 PNP 필드 트랜지스터와 Vss 가 연결된 NPN 필드 트랜지스터가 연결되어 별도의 전류통로를 형성함으로써 과도전류에 의한 ESD 특성 열화를 방지할 수 있도록 하는 것이다.The PNP field transistor connected with Vcc and the NPN field transistor connected with Vss are connected between the series stack structure and the pad of the GMOS and LVTGMOS to form a separate current path to prevent deterioration of ESD characteristics due to transient current.

도 3 및 도 4 는 본 발명에 실시예에 따라 정전기 방전 보호회로가 구비되는 반도체소자의 회로도 및 레이아웃도이다.3 and 4 are a circuit diagram and a layout diagram of a semiconductor device provided with an electrostatic discharge protection circuit according to an embodiment of the present invention.

상기 도 3 은, GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와 Vss 가 연결된 NPN 필드 트랜지스터와 Vcc 가 연결된 PNP 필드 트랜지스터가 연결되어 하나의 전류통로를 형성하는 ESD 보호 회로도로서, 상기 PNP 필드 트랜지스터와 NPN 필드 트랜지스터의 드레인 노드가 패드에 연결된 것이다.3 is an ESD protection circuit diagram in which a series stack structure connected by GMOS and LVTGMOS, an NPN field transistor connected by Vss, and a PNP field transistor connected by Vcc are connected to form a current path, wherein the PNP field transistor and the NPN field transistor are connected to each other. The drain node of is connected to the pad.

상기 도 4 는, 상기 도 3 의 회로도에 따라 도시된 반도체소자의 레이아웃도로서, 폐곡선 형태로 일정범위를 갖는 엔웰 가아드링(37)이 구비되고, 상기 엔웰 가아드링(37)의 내측으로 제2소자분리막(35), 피웰 픽업(33), 제1소자분리막(31)의 순서로 각각 구비되고, 상기 제1소자분리막(31) 영역 내에 GMOS(500)와 LVTGMOS(600)이 각각 구비되되, 이들 모두가 반도체기판 상의 피웰에 구비되는 상기 GMOS 와 LVTGMOS 의 시리즈 스택 구조가 구비되고,4 is a layout diagram of the semiconductor device illustrated in accordance with the circuit diagram of FIG. 3, and includes an enwell guard ring 37 having a predetermined range in the form of a closed curve, and includes a second inside of the enwell guard ring 37. In the order of the device isolation film 35, the Pwell pickup 33, and the first device isolation film 31, respectively, GMOS 500 and LVTGMOS 600 are provided in the region of the first device isolation film 31, respectively. All of them are provided with a series stack structure of the above-described GMOS and LVTGMOS provided in the pewell on the semiconductor substrate,

상기 엔웰 가아드링(37) 내측에 포함된 부분과 상관없이 패드(400)가 구비되며,The pad 400 is provided irrespective of a portion included inside the enwell guard ring 37,

상기 엔웰 가아드링(37)과 이격되어 페곡선 형태로 일정범위를 갖는 엔웰 가아드링(47)이 구비되고, 상기 엔웰 가아드링(47)의 내측으로 제2소자분리막(45), 피웰 픽업(43), 제1소자분리막(41)의 순서로 각각 구비되고, 상기 제1소자분리막(41) 영역 내에 소오스(70), 드레인(60) 및 소오스(70)의 순서로 구비되되, 상기 드레인(60)의 양측으로 Vss 에 연결되는 상기 소오스(70)가 일정간격 이격되어 구비되는 NPN 필드 트랜지스터가 구비되고,An enwell guard ring 47 spaced apart from the enwell guard ring 37 and having a predetermined range in the shape of a curved line is provided, and the second device isolation layer 45 and the pewell pickup 43 are provided inside the enwell guard ring 47. And the first device isolation layer 41, respectively, in the order of the source 70, the drain 60, and the source 70 in the region of the first device isolation layer 41. NPN field transistors having the source 70 connected to both sides of Vss at regular intervals are provided on both sides of

상기 엔웰 가아드링(37,47)과 이격되어 페곡선 형태로 일정범위를 갖는 엔웰 가아드링(57)이 구비되고, 상기 엔웰 가아드링(57)의 내측으로 제2소자분리막(55), 피웰 픽업(53), 제1소자분리막(51)의 순서로 각각 구비되고, 상기 제1소자분리막(51) 영역 내에 소오스(90), 드레인(80) 및 소오스(90)의 순서로 구비되되, 상기 드레인(80)의 양측으로 Vcc 에 연결되는 상기 소오스(90)가 일정간격 이격되어 구비되는 PNP 필드 트랜지스터가 구비된 것이다.An enwell guard ring 57 spaced apart from the enwell guard rings 37 and 47 and having a predetermined range in the shape of a curved line is provided, and a second device isolation layer 55 and a pewell pickup are formed inside the enwell guard ring 57. (53) and the first device isolation layer 51, respectively, in the order of source (90), drain (80), and source 90 in the region of the first device isolation layer (51). PNP field transistors having the source 90 connected to Vcc at both sides of the 80 are spaced by a predetermined interval.

그리고, 상기 도 4 의 레이아웃은, GMOS (500)와 LVTGMOS (600) 사이 그리고 GMOS (500)와 웰 픽업 (33) 사이의 기생 트랜지스터에 의한 GMOS 드레인에서의 과도전류를 해결하기 위하여, 그 간격을 10 ∼ 30 ㎛ 정도로 유지함으로써 주전류흐름을 NPN 필드 트랜지스터로 만들어 ESD 레벨을 향상시킨다.In addition, the layout of FIG. 4 is used to solve the gap between the GMOS 500 and the LVTGMOS 600 and between the GMOS 500 and the well pickup 33 to solve the transient current in the GMOS drain by the parasitic transistor. Maintaining about 10 to 30 µm improves the ESD level by making the main current flow into the NPN field transistor.

그리고, ESD 재핑시 기생 바이폴라 트랜지스터에 의한 전류통로를 막기 위하여, 패드(400)와 GMOS(500) 사이의 피웰 픽업(33)과 엔웰 가아드링(37)에 금속콘택을 형성함으로써 상기 NPN 필드 트랜지스터가 ESD 보호 동작을 하도록 함으로써 ESD 특성을 향상시킨다.In addition, the NPN field transistor is formed by forming a metal contact in the Pwell pickup 33 and the enwell guard ring 37 between the pad 400 and the GMOS 500 to prevent current flow by the parasitic bipolar transistor during ESD zapping. ESD protection improves the ESD characteristics.

그리고, ESD 재핑시 GMOS 드레인의 끝부분에서의 과도전류와 기생 트랜지스터에 의한 GMOS 드레인에서의 과도전류를 막기 위하여, GMOS(500)와 LVTGMOS(600) 사이에 NSD 임플란트를 하되, 활성영역 안쪽으로 하여 NPN 필드 트랜지스터가 ESD 보호 활동을 할 수 있도록 한다.In order to prevent the transient current at the end of the GMOS drain and the transient current at the GMOS drain by the parasitic transistor during ESD zapping, an NSD implant is provided between the GMOS 500 and the LVTGMOS 600, but the inside of the active region Allow NPN field transistors to perform ESD protection.

그리고, 상기 NPN 필드 트랜지스터의 드레인 영역에 피웰 대신 엔웰을 형서하여 ESD 재핑시 드레인 부분에 약간의 손상을 보상함으로써 ESD 레벨을 향상시킨다. 이때, N+ 접합은 엔웰이 감싸고 있어 누설전류 테스트시 약간의 전류를 보상받는다.In addition, by filling an enwell instead of a pwell in the drain region of the NPN field transistor, an ESD level is improved by compensating for a slight damage to the drain portion during ESD zapping. At this time, the N + junction is enclosed by the enwell, so that a slight current is compensated during the leakage current test.

그리고, NPN 필드 트랜지스터의 드레인 영역의 끝부분에서 금속콘택과 엔웰 가아드링 사이의 스페이스를 10 ∼ 20 ㎛ 로 하여 ESD 레벨 저하를 방지한다.At the end of the drain region of the NPN field transistor, the space between the metal contact and the enwell guard ring is set to 10 to 20 µm to prevent the ESD level from dropping.

그리고, 상기 NPN 과 PNP 필드 트랜지스터의 드레인 영역에서의 금속콘택을 2 로우(rows) 이상으로 하고 금속콘택과 활성영역을 2 ∼ 4 ㎛ 로 중첩시켜 ESD 재핑시 전류가 잘 분사되도록 하여 ESD 레벨을 향상시킨다.In addition, the metal contact in the drain region of the NPN and the PNP field transistor is 2 rows or more, and the metal contact and the active region are overlapped by 2 to 4 μm so that the current is well injected during the ESD zapping, thereby improving the ESD level. Let's do it.

한편, 상기 NPN 필드 트랜지스터의 드레인 부분에 폴리실리콘이나 실리사이드로 버퍼층을 구비하여 과도전류에 의한 열을 분사시킴으로써 후속 콘택공정시 스파이킹 현상을 방지함으로써 ESD 레벨을 향상시킨다.On the other hand, by providing a buffer layer of polysilicon or silicide in the drain portion of the NPN field transistor by spraying the heat caused by the transient current to prevent the spike phenomenon during the subsequent contact process to improve the ESD level.

이상에서 상세히 기술한 바와 같이 본 발명에 따른 반도체소자는, GMOS 와 LVTGMOS 가 직렬로 연결된 시리즈 스택 구조와 패드 사이에 Vcc 에 연결된 PNP 필드 트랜지스터와 Vss 에 연결된 NPN 필드 트랜지스터가 연결되어 전류통로를 형성함으로써 GMOS 드레인으로부터의 과도전류에 의한 ESD 특성 열화를 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described in detail above, in the semiconductor device according to the present invention, a PNP field transistor connected to Vcc and an NPN field transistor connected to Vss are connected between a series stack structure and a pad in which GMOS and LVTGMOS are connected in series to form a current path. There is an effect of preventing the deterioration of ESD characteristics due to the transient current from the GMOS drain and thereby improving the characteristics and reliability of the semiconductor device.

Claims (9)

GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와 패드 사이에 별도의 전류통로가 구비되는 반도체소자에 있어서,A semiconductor device having a separate current path between a pad and a series stack structure connected by GMOS and LVTGMOS, 반도체기판 상에 형성된 피웰과,A pewell formed on the semiconductor substrate, 상기 GMOS 와 LVTGMOS 가 이격되어 형성된 섬형태의 제1소자분리막과,An island-shaped first device isolation layer formed by separating the GMOS and LVTGMOS; 상기 섬형태의 소자분리막의 외측에 구비되는 피웰 픽업과,A pewell pick-up provided outside the island-type device isolation film; 상기 피웰 픽업의 외측에 구비되는 제2소자분리막과,A second device isolation film provided outside the pewell pickup; 상기 다른 소자분리막의 외측에 구비되는 엔웰 가아드링과,An enwell guard ring provided at an outer side of the other device isolation film; 상기 GMOS 드레인 영역에 접속되는 패드로 구비되는 GMOS 와 LVTGMOS 의 시리즈 스택 구조와,A series stack structure of GMOS and LVTGMOS provided with pads connected to the GMOS drain region, 상기 GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와 상기 패드 사이에 Vcc 가 연결된 PNP 필드 트랜지스터와,A PNP field transistor having Vcc connected between the pad and the series stack structure connected by the GMOS and the LVTGMOS, 상기 GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와 상기 패드 사이에 Vss 가 연결된 NPN 필드 트랜지스터로 구비되어 별도의 전류통로가 포함되는 반도체소자.And a series stack structure connected by the GMOS and the LVTGMOS and an NPN field transistor having Vss connected between the pads to include a separate current path. 제 1 항에 있어서,The method of claim 1, 상기 GMOS 와 LVTGMOS 는 10 ∼ 30 ㎛ 의 거리가 유지되는 것을 특징으로 하는 반도체소자.The GMOS and LVTGMOS is a semiconductor device, characterized in that the distance of 10 to 30 ㎛ is maintained. 제 1 항에 있어서,The method of claim 1, 상기 GMOS 드레인과 웰 픽업은 10 ∼ 30 ㎛ 의 거리가 유지되는 것을 특징으로 하는 반도체소자.And the GMOS drain and the well pick-up are kept at a distance of 10 to 30 µm. 제 1 항에 있어서,The method of claim 1, 상기 GMOS 와 LVTGMOS 사이에 활성영역 안쪽으로 NSD 임플란트된 것을 특징으로하는 반도체소자.And an NSD implant into the active region between the GMOS and the LVTGMOS. 제 1 항에 있어서,The method of claim 1, 상기 NPN 필드 트랜지스터와 PNP 필드 트랜지스터는 각각 두개의 소오스 노드가 Vss, Vcc 로 연결되는 것을 특징으로하는 반도체소자.The NPN field transistor and the PNP field transistor each have two source nodes connected to each other by Vss and Vcc. 제 1 항에 있어서,The method of claim 1, 상기 NPN 필드 트랜지스터의 드레인영역에 피웰 대신 엔웰이 구비되는 것을 특징으로 하는 반도체소자.And an enwell instead of a pewell in a drain region of the NPN field transistor. 제 1 항에 있어서,The method of claim 1, 상기 NPN 필드 트랜지스터의 드레인영역에서 금속콘택과 엔웰 가아드링 사이의 스페이스가 10 ∼ 20 ㎛ 인 것을 특징으로하는 반도체소자.And a space between the metal contact and the enwell guard ring in the drain region of the NPN field transistor is 10 to 20 µm. 제 1 항에 있어서,The method of claim 1, 상기 NPN 과 PNP 필드 트랜지스터의 드레인영역에서 금속콘택이 2로우이상으로 되고, 금속콘택과 활성영역이 2 ∼ 4 ㎛ 중첩되어 전류를 분산시키는 것을 특징으로하는 반도체소자.And at least two rows of metal contacts in the drain region of the NPN and the PNP field transistor, and dispersing a current by overlapping the metal contact and the active region by 2 to 4 µm. 제 1 항에 있어서,The method of claim 1, 상기 NPN 필드 트랜지스터의 드레인 부분에 폴리실리콘이나 실리사이드로 버퍼층이 구비되는 것을 특징으로 하는 반도체소자.And a buffer layer made of polysilicon or silicide in the drain portion of the NPN field transistor.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970030778A (en) * 1995-11-28 1997-06-26 문정환 Electro-static Discharge (EDS) and Latch-up Prevention Circuits
JPH09191242A (en) * 1996-01-10 1997-07-22 Toshiba Corp Semiconductor device
JPH1032260A (en) * 1996-07-12 1998-02-03 Yamaha Corp Input protecting circuit
KR19980058496A (en) * 1996-12-30 1998-10-07 김영환 Electrostatic Discharge Circuit of Semiconductor Devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970030778A (en) * 1995-11-28 1997-06-26 문정환 Electro-static Discharge (EDS) and Latch-up Prevention Circuits
JPH09191242A (en) * 1996-01-10 1997-07-22 Toshiba Corp Semiconductor device
JPH1032260A (en) * 1996-07-12 1998-02-03 Yamaha Corp Input protecting circuit
KR19980058496A (en) * 1996-12-30 1998-10-07 김영환 Electrostatic Discharge Circuit of Semiconductor Devices

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