KR20000044668A - Chemical mechanical polishing method of semiconductor device - Google Patents

Chemical mechanical polishing method of semiconductor device Download PDF

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Publication number
KR20000044668A
KR20000044668A KR1019980061167A KR19980061167A KR20000044668A KR 20000044668 A KR20000044668 A KR 20000044668A KR 1019980061167 A KR1019980061167 A KR 1019980061167A KR 19980061167 A KR19980061167 A KR 19980061167A KR 20000044668 A KR20000044668 A KR 20000044668A
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South Korea
Prior art keywords
polishing
chemical mechanical
polysilicon
film
oxide film
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KR1019980061167A
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Korean (ko)
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박성용
이상익
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김영환
현대전자산업 주식회사
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Priority to KR1019980061167A priority Critical patent/KR20000044668A/en
Publication of KR20000044668A publication Critical patent/KR20000044668A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG

Abstract

PURPOSE: A chemical mechanical polishing method of a semiconductor device is provided to prevent an erosion and dishing phenomenon from being induced by performing a chemical mechanical polishing process two times after depositing a polysilicon film for a contact plug. CONSTITUTION: In a chemical mechanical polishing method of a semiconductor device, an interlayer insulation film(2) having a thickness of 4000 to 20000 Angstroms is formed on a semiconductor substrate on which a word line(1) is formed. A sacrificial oxide film is formed on the interlayer insulation film(2) so as to have a thickness of 500 to 5000 Angstroms. A contact hole is formed by selectively etching the sacrificial oxide film and the interlayer insulation film(2), and a polysilicon is deposited on an entire surface so as to fill up the contact hole sufficiently. An excessively deposited polysilicon and the sacrificial oxide film are removed by a first chemical mechanical polishing process by use of a slurry for a polysilicon polishing. A polysilicon plug is formed by performing a second chemical mechanical polishing process up to a polishing target(11) by use of a slurry for an oxide film polishing.

Description

반도체소자의 화학적 기계적 평탄화방법Chemical Mechanical Planarization Method of Semiconductor Devices

본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 특히 폴리실리콘 콘택 형성을 위한 폴리실리콘막의 화학적 기계적 평탄화공정에 관한 것이다.The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to a chemical mechanical planarization process of a polysilicon film for forming a polysilicon contact.

종래의 일반적인 화학적 기계적 연마공정에 의한 콘택 형성방법은 도 1에 나타낸 바와 같이 워드라인(1)등이 형성된 반도체기판상에 층간절연막(2)을 형성한 후, 사진식각공정을 실시하여 콘택을 형성하고 콘택형성용 폴리실리콘(3)을 기판 전면에 증착한 다음 도 2에 나타낸 바와 같이 과도하게 증착된 폴리실리콘을 층간절연막상에 폴리실리콘이 남지 않을 때까지 폴리실리콘 연마용 슬러리를 사용하여 연마함으로써 평탄화를 행한다. 도 1에서 참조부호 10은 폴리실리콘 연마용 슬러리를 사용한 연마시의 연마타겟을 나타낸다. 도 1에 도시된 바와 같이 셀영역과 주변회로영역간에 단차가 존재하는 상황에서 폴리실리콘 슬러리를 사용하여 연마를 진행할 경우, 단차가 낮은 주변회로영역에 형성된 폴리실리콘층은 단차가 높은 셀영역에 형성된 폴리실리콘층보다 상대적으로 평탄화공정에 의해 제거되지 못하고 폴리실리콘 잔유물(8) 형태로 남게 되어 후속공정, 특히 금속플러그 형성공정에 심각한 영향을 주게 된다. 이러한 폴리실리콘 잔유물을 제거하기 위해서는 과도한 연마공정을 행하게 되는데, 이 경우 도 2에 나타낸 바와 같이 필연적으로 폴리실리콘 콘택측의 폴리실리콘이 과도하게 연마되는 디싱(6)이 발생하여 후속 폴리실리콘 플러그와의 콘택에 영향을 끼치며, 또한 콘택의 밀도가 높은 지역의 경우 층간절연막이 과도하게 연마되는 침식현상(7)이 일어나게 된다. 이러한 침식현상은 후속 사진공정에 있어서 초점심도 마진의 여유를 감소시킨다.In the conventional method of forming a contact by a chemical mechanical polishing process, as shown in FIG. 1, an interlayer insulating film 2 is formed on a semiconductor substrate on which a word line 1 or the like is formed, followed by a photolithography process to form a contact. By depositing the contact forming polysilicon 3 on the entire surface of the substrate and then using the polysilicon polishing slurry until the polysilicon deposited on the interlayer insulating film is not excessively deposited as shown in FIG. 2. Planarization is performed. In FIG. 1, reference numeral 10 denotes a polishing target during polishing using a polysilicon polishing slurry. As shown in FIG. 1, when polishing is performed using a polysilicon slurry in a situation where a step is present between a cell region and a peripheral circuit region, the polysilicon layer formed in the peripheral circuit region having a low level is formed in a cell region having a high level of difference. Rather than being removed by the planarization process rather than the polysilicon layer, it remains in the form of polysilicon residue 8, which seriously affects subsequent processes, particularly metal plug formation. In order to remove such polysilicon residues, an excessive polishing process is performed. In this case, as shown in FIG. 2, a dishing 6 is inevitably polished with polysilicon on the side of the polysilicon contact to generate a polysilicon plug. In an area that affects the contact and has a high density of contacts, an erosion phenomenon 7 occurs in which the interlayer insulating film is excessively polished. This erosion reduces the margin of depth of focus for subsequent photographic processes.

또한 화학적 기계적 연마시 발생하게 되는 연마 불균일도로 인하여 층간절연막 사이에 폴리실리콘이 남게 되어 이후 실시되는 열공정에 의해 실리콘입자들이 층간절연막 내부로 확산되면서 폴리실리콘 콘택의 누설전류를 증가시킬 수 있다.In addition, polysilicon remains between the interlayer insulating layers due to the polishing nonuniformity generated during chemical mechanical polishing, and silicon particles are diffused into the interlayer insulating layer by a thermal process to be performed, thereby increasing the leakage current of the polysilicon contact.

본 발명은 상술한 문제점을 해결하기 위한 것으로, 층간절연막 상부에 폴리실리콘과 연마속도가 비슷한 희생산화막을 증착하고 사진식각공정을 통하여 플러그 콘택을 형성하고 폴리실리콘박막을 증착한 후, 2회에 걸친 화학적 기계적 연마공정을 행함으로써 침식 및 디싱이 적게 일어나도록 하면서 콘택을 형성할 수 있는 반도체소자의 화학적 기계적 평탄화방법을 제공하는데 그 목적이 있다.The present invention is to solve the above-described problems, and after depositing a sacrificial oxide film having a similar polishing rate to polysilicon on the interlayer insulating film, and forming a plug contact through a photolithography process and depositing a polysilicon thin film, SUMMARY OF THE INVENTION An object of the present invention is to provide a chemical mechanical planarization method of a semiconductor device capable of forming a contact while reducing the erosion and dishing by performing a chemical mechanical polishing process.

상기 목적을 달성하기 위한 본 발명의 반도체소자의 화학적 기계적 평탄화방법은 반도체기판상에 층간절연막을 형성하는 단계, 상기 층간절연막상에 후속공정에서 형성될 연마대상막과의 연마선택비가 거의 없는 희생산화막을 형성하는 단계, 상기 희생산화막상에 연마대상막을 형성하는 단계, 상기 연마대상막 연마용 슬러리를 사용하여 1차 화학기계적 연마를 행하여 과도하게 증착된 연마대상막 부분을 연마하는 단계, 산화막 연마용 슬러리를 사용하여 2차 화학기계적 연마를 행하여 기판 표면을 평탄화시키는 단계를 포함하여 이루어진다.The chemical mechanical planarization method of the semiconductor device of the present invention for achieving the above object is a step of forming an interlayer insulating film on a semiconductor substrate, a sacrificial oxide film having almost no polishing selectivity with the polishing target film to be formed in a subsequent process on the interlayer insulating film Forming a polishing target film on the sacrificial oxide film; performing primary chemical mechanical polishing using the polishing slurry polishing slurry to polish an excessively deposited portion of the polishing target film; And performing a second chemical mechanical polishing using the slurry to planarize the substrate surface.

도 1 및 도 2는 종래기술에 의한 반도체소자의 화학기계적 평탄화방법을 도시한 단면도.1 and 2 are cross-sectional views showing a chemical mechanical planarization method of a semiconductor device according to the prior art.

도 3 내지 도 6은 본 발명에 의한 반도체소자의 화학기계적 평탄화방법을 도시한 공정순서도.3 to 6 are process flowcharts showing a chemical mechanical planarization method of a semiconductor device according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1.워드라인 2.층간절연막1.Wordline 2.Interlayer insulating film

3.폴리실리콘 6.디싱3.Polysilicon 6.Dishing

7.침식현상 8.폴리실리콘 잔유물7.Erosion Phenomenon 8.Polysilicon Residue

9.희생산화막9. Rare production curtain

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 3 내지 도 6에 본 발명에 의한 화학적 기계적 평탄화방법을 도시하였다. 먼저, 상기의 도 2에 나타낸 바와 같이 폴리실리콘 연마용 슬러리를 사용하여 연마할때 폴리실리콘과 층간절연산화막과의 연마선택비가 커서 발생되는 문제점을 해결하기 위하여 도 3에 나타낸 바와 같이 실리콘기판상에 워드라인(1)을 형성하고, 그 전면에 층간절연막(2)을 4000-20000Å 두께로 형성한 후, 그 위에 희생산화막(9)을 500-5000Å 두께로 형성한다. 이때 사용되는 희생산화막은 폴리실리콘 연마용 슬러리를 이용한 화학기계적 연마 측면에서 폴리실리콘과 비슷한 성질을 갖는 산화막이어야 한다. 예를 들면, 20% PSG의 경우 폴리실리콘 연마용 슬러리에 의한 연마속도가 폴리실리콘과 비슷하여 폴리실리콘과의 연마선택비가 없으므로 폴리실리콘 연마용 슬러리에도 쉽게 연마가 된다. 상기 희생산화막으로는 20% PSG이외에도 HDP-USG(high density plasma undoped silicate glass), O3-TEOS, USG등을 사용할 수 있다.3 to 6 illustrate a chemical mechanical planarization method according to the present invention. First, as shown in FIG. 2, in order to solve the problem that the polishing selectivity between the polysilicon and the interlayer insulating oxide film is large when polishing using the polysilicon polishing slurry, the silicon substrate as shown in FIG. After the word line 1 is formed, the interlayer insulating film 2 is formed to a thickness of 4000-20000 mW on the entire surface thereof, and then the sacrificial oxide film 9 is formed thereon to a thickness of 500-5000 mW. In this case, the sacrificial oxide film to be used should be an oxide film having properties similar to those of polysilicon in terms of chemical mechanical polishing using a polysilicon polishing slurry. For example, in the case of 20% PSG, the polishing rate by the polysilicon polishing slurry is similar to that of polysilicon, so that the polishing selectivity with the polysilicon does not exist, so that the polishing rate is easily polished to the polysilicon polishing slurry. As the sacrificial oxide film, high density plasma undoped silicate glass (HDP-USG), O3-TEOS, USG, etc. may be used in addition to 20% PSG.

다음에 사진식각공정을 통해 상기 희생산화막(9)과 층간절연막(2)을 선택적으로 식각하여 소정영역에 콘택을 형성한 후, 그 전면에 폴리실리콘(3)을 증착한다.Next, the sacrificial oxide layer 9 and the interlayer dielectric layer 2 are selectively etched through a photolithography process to form a contact in a predetermined region, and then polysilicon 3 is deposited on the entire surface.

이어서 도 4에 나타낸 바와 같이 폴리실리콘 연마용 슬러리를 이용하여 과도하게 증착된 폴리실리콘 부분을 1차 화학기계적 연마공정을 통해 희생산화막(9)까지 연마한다. 즉, 도 3의 참조부호 9로 나타낸 연마타겟까지 연마한다. 상기 폴리실리콘 연마용 슬러리로는 산화막과의 선택비가 30:1 이상인 슬러리를 사용하는 것이 바람직하며, 이때 사용되는 슬러리의 성분은 SiO2, CeO2, Al2O3으로 된 것이 바람직하다.Subsequently, as shown in FIG. 4, the polysilicon portion that is excessively deposited using the polysilicon polishing slurry is polished to the sacrificial oxide film 9 through the first chemical mechanical polishing process. That is, the polishing target shown by 9 in FIG. 3 is polished. As the polysilicon polishing slurry, it is preferable to use a slurry having a selectivity of 30: 1 or more with an oxide film, and the components of the slurry used are preferably SiO2, CeO2, Al2O3.

다음에 도 5에 나타낸 바와 같이 산화막 연마용 슬러리를 사용하여 연마타겟(11)까지 2차 화학기계적 연마공정을 행함으로써 도 6에 나타낸 바와 같이 폴리실리콘 플러그(3)를 형성한다. 상기 산화막 연마용 슬러리로는 그 성분이 SiO2, CeO2로 된 것을 사용하는 것이 바람직하다.Next, as shown in FIG. 5, the polysilicon plug 3 is formed as shown in FIG. 6 by performing a secondary chemical mechanical polishing process up to the polishing target 11 using an oxide film polishing slurry. It is preferable to use the thing whose whose components were SiO2 and CeO2 as said oxide film polishing slurry.

상기한 본 발명의 평탄화공정의 경우, 폴리실리콘 연마정지막으로 사용된 층간절연막이 상부의 희생산화막보다 연마속도가 낮기 때문에 폴리실리콘이나 희생산화막이 연마되는 동안에 거의 연마되지 않는다. 따라서 선택비가 높은 폴리실리콘 연마용 슬러리를 사용하여 완전히 연마할 필요가 없고, 폴리실리콘 슬러리를 사용하여 과도하게 화학기계적 연마를 하여 혹시 남아 있을지 모르는 잔류 폴리실리콘을 완전히 제거할 수 있으며, 2차로 산화막 슬러리를 사용하여 침식과 디싱을 최소화함으로써 평탄도가 얻어지므로 공정마진을 확보할 수 있어 생산성을 향상시킬 수 있다.In the planarization process of the present invention described above, since the interlayer insulating film used as the polysilicon polishing stop film has a lower polishing rate than the sacrificial oxide film on the upper side, it is hardly polished while the polysilicon or the sacrificial oxide film is polished. Therefore, it is not necessary to polish completely using a polysilicon polishing slurry having a high selectivity, and excessive polymechanical polishing using a polysilicon slurry can completely remove residual polysilicon that may be left, and a second oxide slurry Since flatness is obtained by minimizing erosion and dishing using, process margins can be secured and productivity can be improved.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

본 발명은 화학기계적 평탄화공정시 폴리실리콘과 연마속도가 비슷한 산화막을 층간절연막 상부에 미리 형성하여 적당히 식각한 후, 연마대상막인 폴리실리콘을 증착하고 화학기계적 연마공정을 행함으로써 기판의 평탄화도를 월등히 개선할 수 있고, 기존에 사용하던 폴리실리콘 연마용 슬러리만으로도 연마선택비를 폴리실리콘과 비슷하게 맞출 수 있으며, 전, 후속 공정의 마진확보로 반도체소자의 수율 및 생산성을 향상시킬 수 있다.According to the present invention, an oxide film having a polishing rate similar to that of polysilicon is formed in advance on an interlayer insulating film, and then etched appropriately, followed by depositing polysilicon, which is a film to be polished, and performing a chemical mechanical polishing process. It can be significantly improved, and the polishing selectivity can be adjusted similarly to polysilicon using only the polysilicon polishing slurry used previously, and the yield and productivity of the semiconductor device can be improved by securing the margin of the previous and subsequent processes.

Claims (5)

반도체기판상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate; 상기 층간절연막상에 후속공정에서 형성될 연마대상막과의 연마선택비가 거의 없는 희생산화막을 형성하는 단계;Forming a sacrificial oxide film having little polishing selectivity with the polishing target film to be formed in a subsequent step on the interlayer insulating film; 상기 희생산화막상에 연마대상막을 형성하는 단계;Forming a polishing target film on the sacrificial oxide film; 상기 연마대상막 연마용 슬러리를 사용하여 1차 화학기계적 연마를 행하여 과도하게 증착된 연마대상막 부분을 연마하는 단계; 및Polishing the excessively deposited portion of the polishing target film by performing primary chemical mechanical polishing using the polishing slurry polishing slurry; And 산화막 연마용 슬러리를 사용하여 2차 화학기계적 연마를 행하여 기판 표면을 평탄화시키는 단계Planarizing the surface of the substrate by performing secondary chemical mechanical polishing using an oxide polishing slurry 를 포함하는 반도체소자의 화학기계적 평탄화방법.Chemical mechanical planarization method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 희생산화막으로 20% PSG, HDP-USG, O3-TEOS, USG등을 사용하는 것을 특징으로 하는 반도체소자의 화학기계적 평탄화방법.The chemical mechanical planarization method of the semiconductor device, characterized in that 20% PSG, HDP-USG, O3-TEOS, USG and the like as the sacrificial oxide film. 제1항에 있어서, 상기 연마대상막은The method of claim 1, wherein the polishing target film 폴리실리콘층임을 특징으로 하는 반도체소자의 화학기계적 평탄화방법.A chemical mechanical planarization method of a semiconductor device, characterized in that the polysilicon layer. 제1항에 있어서,The method of claim 1, 상기 층간절연막을 4000-20000Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 화학기계적 평탄화방법.And forming the interlayer dielectric layer at a thickness of 4000-20000 GPa. 제1항에 있어서,The method of claim 1, 상기 희생산화막을 500-5000Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 화학기계적 평탄화방법.The chemical mechanical planarization method of a semiconductor device, characterized in that for forming the sacrificial oxide film to a thickness of 500-5000Å.
KR1019980061167A 1998-12-30 1998-12-30 Chemical mechanical polishing method of semiconductor device KR20000044668A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030020855A (en) * 2001-09-04 2003-03-10 엔이씨 일렉트로닉스 코포레이션 Method of forming metal wiring line
KR100492897B1 (en) * 2000-12-22 2005-06-02 주식회사 하이닉스반도체 Method for fabricating polysilicon plug using polysilicon slurry

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100492897B1 (en) * 2000-12-22 2005-06-02 주식회사 하이닉스반도체 Method for fabricating polysilicon plug using polysilicon slurry
KR20030020855A (en) * 2001-09-04 2003-03-10 엔이씨 일렉트로닉스 코포레이션 Method of forming metal wiring line

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