KR20000043072A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- KR20000043072A KR20000043072A KR1019980059379A KR19980059379A KR20000043072A KR 20000043072 A KR20000043072 A KR 20000043072A KR 1019980059379 A KR1019980059379 A KR 1019980059379A KR 19980059379 A KR19980059379 A KR 19980059379A KR 20000043072 A KR20000043072 A KR 20000043072A
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- dummy active
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- semiconductor device
- field oxide
- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 description 13
- 239000000126 substance Substances 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 장치에 관한 것으로, 특히 더미 액티브(dummy active)를 기판과 반대 도전형으로 형성하여 상층의 금속배선과의 커패시턴스를 줄여, 반도체 장치의 특성을 향상시키는데 적당하도록 한 반도체 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a dummy active is formed in an opposite conductivity type to a substrate so as to reduce capacitance with an upper metal wiring and to improve the characteristics of the semiconductor device. .
일반적으로, 반도체 장치에서 더미 액티브(dummy active)란 필드산화막을 낮은 깊이의 트랜치구조 내에 형성하기 위한 화학적 기계적 연마(chemical mechenical polishing)공정을 사용할 때, 그 트랜치구조의 조밀도에 따라 필드산화막의 구조가 변경되며, 이와 같이 트랜치구조내에 정상적인 필드산화막을 형성하기 위해 실제 액티브영역(active)이 아닌 필드산화막의 형성위치에 필드산화막을 형성하지 않는 더미 액티브(dummy active)를 형성하게 된다. 상기 화학적 기계적 연마공정은 안정한 공정이 아니며, 연마의 대상이 되는 층의 밀도, 막의 질에 따라 평탄화가 정확히 이루어지지 않은 경우가 빈번히 발생한다. 이와 같은 문제점을 방지하기 위해 종래에는 크기가 상대적으로 큰 필드산화막을 분할하여 그 필드산화막의 중앙부분에 필드산화막을 형성하지 않고, 기판을 그대로 방치하는 더미 액티브를 형성하며, 이와 같은 더미 액티브에는 소자가 형성되지 않는다. 종래의 더미 액티브는 순수한 기판 자체이며, 이와 같은 더미 액티브를 포함하는 종래 반도체 장치를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, in the semiconductor device, dummy active is a structure of the field oxide film depending on the density of the trench structure when using a chemical mechenical polishing process for forming the field oxide film into the trench structure having a low depth. In this way, in order to form a normal field oxide film in the trench structure, a dummy active that does not form a field oxide film is formed at a position where the field oxide film is formed, rather than an actual active region. The chemical mechanical polishing process is not a stable process, and the planarization is frequently performed according to the density of the layer to be polished and the quality of the film. In order to prevent such a problem, conventionally, a field oxide film having a relatively large size is divided to form a dummy active that leaves the substrate as it is without forming a field oxide film in the center portion of the field oxide film. Is not formed. Conventional dummy actives are pure substrates themselves, and will be described in detail with reference to the accompanying drawings of a conventional semiconductor device including such a dummy active.
도1은 종래 반도체 장치의 단면 모식도로서, 이에 도시한 바와 같이 사진식각공정을 통해 기판(1)에 트랜치구조를 형성하고, 그 트랜치구조가 형성된 기판(1)의 상부전면에 산화막을 증착하고, 화학적 기계적 연마를 통해 상기 트랜치구조 내에 위치하는 필드산화막(2)을 형성한다.FIG. 1 is a schematic cross-sectional view of a conventional semiconductor device. As shown in FIG. 1, a trench structure is formed on a substrate 1 through a photolithography process, and an oxide film is deposited on the upper surface of the substrate 1 on which the trench structure is formed. Through chemical mechanical polishing, a field oxide film 2 located in the trench structure is formed.
상기 도1에서 두 필드산화막(2)의 사이 기판(1) 영역은 실제 소자가 형성될 액티브영역이 아니며, 원래는 필드산화막(2)이 형성되어야 할 부분이지만, 정확한 필드산화막(2) 구조를 형성하기 위해 하나의 필드산화막(2)을 분할하여 기판(1)을 노출시킨 더미 액티브(5)가 된다.In FIG. 1, the region of the substrate 1 between the two field oxide films 2 is not an active region in which the actual element is to be formed, but is a part in which the field oxide film 2 should be formed. One field oxide film 2 is divided to form a dummy active 5 in which the substrate 1 is exposed.
이와 같은 구조에서 도면에는 도시되지 않았지만, 실제 소자가 형성될 영역인 액티브영역에 소자를 형성하고, 그 소자의 절연을 위한 층간절연막(3)을 형성한다.Although not shown in the drawing in this structure, the element is formed in the active region where the actual element is to be formed, and the interlayer insulating film 3 for insulation of the element is formed.
그리고, 상기 소자의 특정영역에 접하는 금속배선(4)을 상기 층간절연막(3)의 상부에 형성하며, 이때 금속배선(4)은 상기 더미 액티브(5)의 상부측을 지날 수 있다.In addition, a metal wiring 4 in contact with a specific region of the device is formed on the interlayer insulating film 3, wherein the metal wiring 4 may pass through the upper side of the dummy active 5.
이와 같이 금속배선(4)이 기판(1)인 더미 액티브(5)의 상부측 층간절연막(3)을 지날 경우, 그 금속배선(4)과 더미 액티브(5)가 전극으로 작용하고, 그 사이의 층간절연막(3)이 유전체로 작용하여 기생 커패시턴스(Ca)가 형성된다. 또한, 상기 필드산화막(2)이 형성된 기판(1) 영역에서도 상기 금속배선(4)과 기판(1)을 전극으로 하고, 그 사이의 필드산화막(2)과 층간절연막(3)을 유전체로 하는 기생 커패시턴스(Cc)가 형성된다.In this way, when the metal wiring 4 passes through the upper interlayer insulating film 3 of the dummy active 5, which is the substrate 1, the metal wiring 4 and the dummy active 5 serve as electrodes. The interlayer insulating film 3 acts as a dielectric to form parasitic capacitance Ca. In the region of the substrate 1 where the field oxide film 2 is formed, the metal wiring 4 and the substrate 1 are used as electrodes, and the field oxide film 2 and the interlayer insulating film 3 therebetween are used as dielectrics. Parasitic capacitance Cc is formed.
이때, 커패시턴스는 유전막의 두께에 반비례 하기 때문에 상기 더미 액티브(5)를 전극으로 하는 기생 커패시턴스(Ca)가 기판(1)을 전극으로 하는 기생 커패시턴스(Cc)보다 크게 된다. 이에 따라 금속배선(5)을 통해 인가되는 전류는 변형 또는 지연되는 결과를 갖게 된다.At this time, since the capacitance is inversely proportional to the thickness of the dielectric film, the parasitic capacitance Ca having the dummy active 5 as an electrode is larger than the parasitic capacitance Cc having the substrate 1 as an electrode. Accordingly, the current applied through the metal wiring 5 has a result of being deformed or delayed.
다시 말해서, 더미 액티브(5) 영역을 형성하지 않고, 전체에 필드산화막(2)을 형성할 때 기판(1)과 금속배선(4)의 커패시턴스(Cc)에 비해 더미 액티브(5)를 형성할 경우 더 큰 커패시턴스(Ca)가 금속배선(4)과 더미 액티브(5)의 사이에 발생하여 신호의 전달이 지연되거나, 심한 경우 신호의 왜곡이 발생하게 된다.In other words, when the field oxide film 2 is formed on the whole without forming the dummy active 5 region, the dummy active 5 may be formed compared to the capacitance Cc of the substrate 1 and the metal wiring 4. In this case, a larger capacitance Ca is generated between the metallization 4 and the dummy active 5 so that signal transmission is delayed or, in severe cases, signal distortion occurs.
상기한 바와 같이 종래 반도체 장치는 필드산화막의 균일한 형성을 위해 소자가 형성되지 않는 더미 액티브를 실제 필드산화막이 형성될 위치에 형성하여, 그 상부측을 지나는 금속배선과의 기생 커패시턴스를 상대적으로 크게 발생시켜, 금속배선을 통해 전송되는 신호를 지연시켜 반도체 장치의 특성이 저하되는 문제점이 있었다.As described above, the conventional semiconductor device forms a dummy active where no element is formed for the uniform formation of the field oxide film at the position where the actual field oxide film is to be formed, thereby relatively increasing the parasitic capacitance with the metal wiring passing through the upper side thereof. And delayed signals transmitted through the metallization, thereby deteriorating the characteristics of the semiconductor device.
이와 같은 문제점을 감안한 본 발명은 더미 액티브와 금속배선간의 커패시턴스를 줄일 수 있는 반도체 장치를 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a semiconductor device capable of reducing capacitance between dummy active and metal wiring.
도1은 종래 반도체 장치의 모식도.1 is a schematic diagram of a conventional semiconductor device.
도2는 본 발명 반도체 장치의 모식도.2 is a schematic diagram of a semiconductor device of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2:필드산화막1: Substrate 2: Field Oxide
3:층간절연막 4:금속배선3: interlayer insulating film 4: metal wiring
5:더미 액티브5: pile active
상기와 같은 목적은 더미 액티브를 기판과 다른 도전형으로 형성하여, 기판과 더미 액티브의 사이에 기생 커패시턴스를 발생시키고, 이를 이용하여 더미 액티브아 금속배선간의 커패시턴스를 상쇄시킴으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is achieved by forming the dummy active into a different conductivity type from the substrate, generating parasitic capacitance between the substrate and the dummy active, and using this to offset the capacitance between the dummy active metal wiring. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도2는 본 발명 반도체 장치의 단면 모식도로서, 이에 도시한 바와 같이 종래 도1에 도시한 기술구성과 동일하며, 단지 더미 액티브(5)를 기판(1)과는 반대도전형으로 형성한다.FIG. 2 is a schematic cross-sectional view of the semiconductor device of the present invention, as shown in FIG. 1, which is the same as the conventional technical configuration shown in FIG. 1, and merely forms a dummy active 5 in the opposite conductivity type to the substrate 1. As shown in FIG.
다시 말해서 기판(1)이 P형인 경우, 더미 액티브(5)에 N형 불순물 이온을 이온주입하며, 기판(1)이 N형인 경우 더미 액티브(5)에 P형 불순물 이온을 이온주입하여 더미 액티브(5)와 기판(1)이 서로 반대 도전형이 되도록 한다.In other words, when the substrate 1 is P type, N-type impurity ions are ion-implanted into the dummy active 5, and when the substrate 1 is N-type, P-type impurity ions are ion-implanted into the dummy active 5 to be dummy active. (5) and the board | substrate 1 are made to be mutually opposite conductivity types.
이와 같이 더미 액티브(5)를 기판(1)과 반대 도전형으로 형성할 경우, 그 더미 액티브(5)와 기판(1)의 사이에도 기생 커패시턴스(Cb)가 발생한다.When the dummy active 5 is formed in the opposite conductivity type to the substrate 1 as described above, parasitic capacitance Cb is generated between the dummy active 5 and the substrate 1.
또한, 더미 액티브(5)와 금속배선(4)의 사이에도 기생 커패시턴스(Ca)가 발생하며, 이때의 두 기생 커패시턴스(Cb),(Ca)는 서로 직렬연결된 형태이며, 이에 따라 그 기생 커패시턴스(Cb),(Ca)의 합은 각각의 기생 커패시턴스(Cb),(Ca)보다 작게 된다.In addition, a parasitic capacitance Ca is generated between the dummy active 5 and the metal wiring 4, and the two parasitic capacitances Cb and Ca are connected in series to each other, and thus, the parasitic capacitance C The sum of Cb) and Ca becomes smaller than the respective parasitic capacitances Cb and Ca.
다시 말해서, 상기 더미 액티브(5)를 기판(1)과 동일한 도전형으로 형성할 때에 비해 금속배선(4)과의 커패시턴스가 줄어들게 되며, 이에 따라 신호의 속도 지연을 방지하며, 신호의 왜곡또한 줄일 수 있게 된다.In other words, the capacitance with the metallization 4 is reduced compared to when the dummy active 5 is formed in the same conductivity type as the substrate 1, thereby preventing the signal delay and reducing the distortion of the signal. It becomes possible.
그리고, 더미 액티브(5)를 좀더 조밀하게 형성하여, 근본적으로 액티브의 면적과 밀도에 따라 평탄화 정도가 달라지는 화학적 기계적 연마공정으로 형성되는 필드산화막(2)을 안정적인 구조로 형성하여, 반도체 장치의 신뢰성을 향상시킬 수 있다.In addition, by forming the dummy active 5 more densely, the field oxide film 2 formed by the chemical mechanical polishing process of which the degree of planarization is fundamentally changed according to the area and density of the active is formed in a stable structure, thereby ensuring the reliability of the semiconductor device. Can improve.
상기한 바와 같이 본 발명 반도체 장치는 더미 액티브를 기판과 반대 도전형으로 형성하여 기판과 더미 액티브간에 기생 커패시턴스를 발생시켜, 더미 액티브와 금속배선간에 발생되는 기생 커패시턴스를 감소시킴으로써, 금속배선을 통해 전송되는 신호의 지연 및 왜곡을 방지하여 반도체 장치의 특성을 향상시키는 효과와 아울러 신뢰성을 향상시키는 효과가 있다.As described above, the semiconductor device of the present invention forms a dummy active in an opposite conductivity type to the substrate to generate parasitic capacitance between the substrate and the dummy active, thereby reducing the parasitic capacitance generated between the dummy active and the metal wiring, thereby transmitting through the metal wiring. By preventing delay and distortion of the signal, there is an effect of improving the characteristics of the semiconductor device and an effect of improving reliability.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980059379A KR20000043072A (en) | 1998-12-28 | 1998-12-28 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980059379A KR20000043072A (en) | 1998-12-28 | 1998-12-28 | Semiconductor device |
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| KR20000043072A true KR20000043072A (en) | 2000-07-15 |
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| KR1019980059379A KR20000043072A (en) | 1998-12-28 | 1998-12-28 | Semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8144538B2 (en) | 2008-01-25 | 2012-03-27 | Samsung Electronics Co., Ltd. | Semiconductor device |
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1998
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8144538B2 (en) | 2008-01-25 | 2012-03-27 | Samsung Electronics Co., Ltd. | Semiconductor device |
| US8345499B2 (en) | 2008-01-25 | 2013-01-01 | Samsung Electronics Co., Ltd. | Semiconductor device |
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