KR20000028654A - Method/structure for creating aluminum wirebond pad on copper beol - Google Patents

Method/structure for creating aluminum wirebond pad on copper beol Download PDF

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Publication number
KR20000028654A
KR20000028654A KR1019990038815A KR19990038815A KR20000028654A KR 20000028654 A KR20000028654 A KR 20000028654A KR 1019990038815 A KR1019990038815 A KR 1019990038815A KR 19990038815 A KR19990038815 A KR 19990038815A KR 20000028654 A KR20000028654 A KR 20000028654A
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South Korea
Prior art keywords
passivation layer
forming
stack
integrated circuit
wiring
Prior art date
Application number
KR1019990038815A
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Korean (ko)
Other versions
KR100354596B1 (en
Inventor
코스트리니그레고리
골드블레트로날드딘
하이덴레이츠존에드워드3세
맥데빗토마스레디
Original Assignee
포만 제프리 엘
인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR20000028654A publication Critical patent/KR20000028654A/en
Application granted granted Critical
Publication of KR100354596B1 publication Critical patent/KR100354596B1/en

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Abstract

PURPOSE: A preparation process of aluminum contact is provided to prepare aluminum contact in the structure of copper BEOL(back-of-the line) to prevent the destruction of low material layer when bonded in semiconductor package. CONSTITUTION: To acquire an aluminum contact, a passivating layer(14) is formed on a wafer(20) of an IC having a copper wire(22) inside. An aperture is formed by forming a terminal-via-aperture(26) through the passivating layer to expose the copper wire. A barrier layer(28) is formed on the region of the passivating layer adjacent to the terminal via aperture, on the side wall of the terminal-via-aperture and on the exposed copper wire. Then, an aluminum stack is formed on the region of the barrier layer and on the barrier layer in the terminal-via-aperture. The aluminum stack and the barrier layer are patterned and etched to form a second passivating layer(32) on the patterned aluminum stack. And, a second aperture is formed in the second passivating layer to expose the region of the aluminum stack placed on the upper portion of the patterned copper wire.

Description

알루미늄 콘택트 형성 방법 및 집적 회로 구조체{METHOD/STRUCTURE FOR CREATING ALUMINUM WIREBOND PAD ON COPPER BEOL}METHOD / STRUCTURE FOR CREATING ALUMINUM WIREBOND PAD ON COPPER BEOL}

본 발명은 집적 회로의 패키징(packaging)에 관한 것으로, 구체적으로는 집적 회로(IC) 소자의 구리(Cu) 상호 접속 배선과 전기적으로 도통되는 알루미늄 콘택트를 생성하는 방법에 관한 것이다. 본 발명의 일 실시예에서는, 큰 비아와 하부 구리 패드를 피복하는 알루미늄 플러그(plugg) 구조체가 채용된다. 제 2 실시예는 알루미늄 본드 패드로 이루어지는데, 그 알루미늄 본드 패드에서는 구리 알루미늄 비아 영역을 최소화하도록 하부 구리로의 개구가 본드 패드(bond pad)의 활성 영역으로부터 수평 방향으로 이동되어 있으며 구리 알루미늄 접속부를 규정하는 영역의 크기도 축소되어 있다. 본 발명에 기술된 알루미늄 콘택트의 목적은 노출된 구리를 피복하여 외적 요인에 의한 공격 및/또는 본드(bond)(즉, 납-주석)를 형성하는 데 사용된 재료와 하부 구리의 혼합을 방지하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the packaging of integrated circuits, and more particularly, to a method of producing an aluminum contact that is electrically conductive with copper (Cu) interconnect wiring of an integrated circuit (IC) device. In one embodiment of the present invention, an aluminum plugg structure is employed that covers the large vias and the lower copper pads. The second embodiment consists of an aluminum bond pad, in which the opening to the lower copper is moved horizontally from the active area of the bond pad to minimize the copper aluminum via area and the copper aluminum contacts The size of the prescribed area is also reduced. The purpose of the aluminum contacts described in the present invention is to cover the exposed copper to prevent attack by external factors and / or mixing of the underlying copper with the material used to form the bond (ie lead-tin). will be.

반도체 제조에 있어서, 제조된 집적 회로(integrated circuit: IC) 소자는 통상 패키지로 조립되어 보다 큰 회로의 일부분으로 인쇄 회로 기판 상에서 사용된다. 패키지의 리드(lead)가 제조된 IC 소자의 본딩 패드와 전기적으로 접촉하도록 하기 위하여, 금속 본드를 형성함으로써 IC 소자의 본딩 패드와 패키지 리드 프레임에 연장되어 있는 리드 사이에 접속이 이루어지게 하거나 세라믹 또는 폴리머성 칩 캐리어에 땜납 볼 접속이 이루어지게 한다.In semiconductor manufacturing, manufactured integrated circuit (IC) devices are typically assembled in a package and used on a printed circuit board as part of a larger circuit. In order for the leads of the package to be in electrical contact with the bonding pads of the manufactured IC device, a metal bond is formed to make a connection between the bonding pads of the IC device and the leads extending to the package lead frame or to make a ceramic or A solder ball connection is made to the polymeric chip carrier.

종래에는 Al과 Al 합금이 통상적인 칩 배선 재료로 사용되었다. Al 배선 재료가 Cu와 Cu 합금으로 대체되고 있는데, 이는 Cu 배선이 Al과 Al 합금에 비해 개선된 칩 성능과 뛰어난 신뢰성을 제공하기 때문이다. 구리 배선을 채용한 IC 소자의 패키징은 땜납 볼 공정에 사용되는 재료와의 구리의 반응 및/또는 외적 요인에 의한 공격과 부식에 대한 구리의 취약성과 관련된 많은 기술적 과제를 제기한다.Conventionally, Al and Al alloys have been used as conventional chip wiring materials. Al wiring materials are being replaced by Cu and Cu alloys, because Cu wiring provides improved chip performance and superior reliability over Al and Al alloys. Packaging of IC devices employing copper wiring presents a number of technical challenges associated with copper's susceptibility to attack and corrosion by external reactions and / or copper's reaction with materials used in the solder ball process.

도 1에는 패키지와 상호 접속되기 전의 전형적인 종래의 제조된 IC 구조체가 도시되어 있다. 구체적으로, 도 1에 도시한 종래의 제조된 IC 구조체는 적어도 하나의 Cu 배선 영역(12)이 표면 내에 매립되어 있는 반도체 웨이퍼(10)를 포함한다. 반도체 웨이퍼(10)는 그 내부에 다수의 IC 소자 영역을 포함한다는 것을 주목해야 한다. 명료함을 위해 이들 IC 소자 영역은 도면에 도시되어 있지 않다. 도 1에 도시한 종래의 IC 구조체는 반도체 웨이퍼(10)의 표면 상부에 형성되어 있으며 그 안에 Cu 배선 영역(12) 위에 연장되어 있는 개구를 갖는 부동화층(passivating layer)(14)을 더 포함한다. 개구 내에는 단자 비아 장벽층(16)이 도시되어 있는데, 단자 비아 장벽층(16) 또한 개구에 인접한 부분의 부동화층 위로 연장되어 있다. 전형적으로 폴리이미드 막과 같은 유기 재료로 구성되면서 Cu 배선(12) 상에 개구를 갖는 제 2 부동화층(18)이 부동화층(14)의 표면 상에 위치한다.1 shows a typical conventional manufactured IC structure before interconnecting with the package. Specifically, the conventional manufactured IC structure shown in FIG. 1 includes a semiconductor wafer 10 in which at least one Cu wiring region 12 is embedded in a surface. It should be noted that the semiconductor wafer 10 includes a plurality of IC device regions therein. For the sake of clarity, these IC device areas are not shown in the figures. The conventional IC structure shown in FIG. 1 further includes a passivating layer 14 formed over the surface of the semiconductor wafer 10 and having an opening therein extending over the Cu wiring region 12. . A terminal via barrier layer 16 is shown in the opening, which also extends over the passivation layer in the portion adjacent to the opening. A second passivation layer 18, which is typically made of an organic material such as a polyimide film and has an opening on the Cu wiring 12, is located on the surface of the passivation layer 14.

도 1에 도시한 종래 구조체는, 내부에 Cu 배선을 구비하는 평탄화된 IC 웨이퍼를 제공하는 단계와, 평탄화된 IC 웨이퍼의 표면 상에 부동화층을 형성하는 단계와, 부동화층을 반응성 이온 에칭(reactive ion etching: RIE)하여 하부의 Cu 배선 상에 단자 비아 개구를 형성하는 단계와, 상기 단자 비아 개구에 장벽층을 제공하는 단계와, 장벽층의 표면 상에 유기 부동화층을 형성하는 단계와, 외각 부동화층을 에칭하여 Cu 배선에 개구를 제공하는 단계에 의해 통상적으로 제조된다.The prior art structure shown in FIG. 1 includes providing a planarized IC wafer having Cu wiring therein, forming a passivation layer on the surface of the planarized IC wafer, and reactive ion etching the passivation layer. ion etching (RIE) to form terminal via openings on the lower Cu wiring, providing a barrier layer to the terminal via openings, forming an organic passivation layer on the surface of the barrier layer, and It is typically manufactured by etching the passivation layer to provide an opening in the Cu wiring.

현재 공정에서는 부동화층(14) 내에 (90μm의) 큰 단자 비아 개구를 형성하여 하부 Cu 배선 레벨에 생성된 패드를 노출시킨다. Cu BEOL(back-of-the line) 구조체에 대해 종래 기술에서 사용되는 이러한 공정은 와이어 본드 접속이 단자 비아 개구를 통해 하부 Cu 배선에 직접 이루어지는 예전의 BEOL 기법으로부터 개발되었다. 추가 Cu 배선 레벨들이 채용되는 현재의 응용예에서는 전술한 기법을 사용하는 데 여러 가지 문제점이 있다.In the current process, a large terminal via opening (90 μm) is formed in passivation layer 14 to expose the resulting pad at the lower Cu wiring level. This process, which is used in the prior art for Cu back-of-the line (BEOL) structures, was developed from previous BEOL techniques in which wire bond connections are made directly to the bottom Cu wiring through terminal via openings. In current applications where additional Cu wiring levels are employed, there are several problems with using the techniques described above.

첫째, 구리는 알루미늄과는 달리 자체 부동화 산화물층을 형성하지 않기 때문에, 구리가 대기 조건에 노출되면 수 천 옹스트롱(Å)의 깊이까지 부식되어 IC 소자의 신뢰도를 저하시킬 것이다. 둘째, 땜납 볼 응용예에서는, 통상적으로 사용되는 볼 제한 또는 장벽 금속이 구리 배선에 적절하지 않을 수도 있고, 납-주석(Pb-Sn) 땜납 재료가 하부 구리와 혼합될 수도 있다. 이런 경우 취성을 갖는 Cu-Sn 금속간 화합물이 형성되어 전기 저항을 증가시키고 상호 접속 기법의 신뢰도를 손상시킬 것이다.First, unlike aluminum, copper does not form its own passivated oxide layer, so if copper is exposed to atmospheric conditions it will corrode to depths of thousands of angstroms and degrade the reliability of IC devices. Second, in solder ball applications, conventionally used ball limiting or barrier metals may not be suitable for copper wiring, and lead-tin (Pb-Sn) solder material may be mixed with the underlying copper. In this case, brittle Cu-Sn intermetallic compounds will be formed that will increase the electrical resistance and compromise the reliability of the interconnect technique.

구리 배선 IC 구조체에 대한 패키징 접속의 종래 공정과 관련하여 언급된 결함을 고려하여, 종래 공정에 연관된 결점을 극복하기 위한 신규하고 개선된 공정을 개발할 필요성이 계속 제기되어 왔다. 이러한 구조체와 방법에서 요구되는 조건은 그 구조체와 방법이 통상적인 칩 패키징 및 테스트 방법론과 양립할 수 있어야 하고, 외적 요인에 의한 공격 및/또는 패키징 재료와의 반응으로부터 구리 배선을 보호해야 한다는 것이다.In view of the deficiencies mentioned in connection with conventional processes of packaging connections to copper interconnect IC structures, there has been a continuing need to develop new and improved processes to overcome the deficiencies associated with conventional processes. The requirements for such structures and methods are that they must be compatible with conventional chip packaging and testing methodologies, and protect copper wiring from external attack and / or reaction with packaging materials.

본 발명의 목적은 종래의 Al 콘택트 제조 방법과 연관된 모든 문제를 극복하는 Al 콘택트, 즉 본드 패드를 Cu BEOL 상에 제조하는 공정을 제공하는 것이다.It is an object of the present invention to provide a process for making Al contacts, ie bond pads, on Cu BEOL that overcomes all the problems associated with conventional Al contact manufacturing methods.

본 발명의 또다른 목적은 IC 구조체 내에 매립되어 있는 하부 Cu 배선과 전기적으로 도통하는 Al 콘택트를 제조하는 공정을 제공하는 것이다.It is yet another object of the present invention to provide a process for making an Al contact that is in electrical communication with a lower Cu interconnect embedded in an IC structure.

본 발명의 또다른 목적은 반도체 패키지로 본딩된 때 하부 재료층의 파괴가 일어나지 않도록 Cu BEOL 구조체 내에 Al 콘택트를 제조하는 공정을 제공하는 것이다.It is another object of the present invention to provide a process for making Al contacts in a Cu BEOL structure such that no breakage of the underlying material layer occurs when bonded to the semiconductor package.

본 발명의 또다른 목적은 구리 배선과 땜납 재료의 혼합을 방지하고 통상적으로 사용되는 땜납 및 BLM(ball limiting metallurgy) 재료를 구리 상호 접속 공정에서 사용할 수 있게 하는 땜납 볼 접속부를 형성하는 공정을 제공하는 것이다.It is another object of the present invention to provide a process for forming solder ball connections that prevents mixing of copper wiring and solder material and enables the use of conventionally used solder and ball limiting metallurgy (BLM) materials in copper interconnect processes. will be.

본 발명에서 이들 및 다른 측면과 장점은,These and other aspects and advantages in the present invention,

① 내부에 Cu 배선을 구비하는 집적 회로(IC) 반도체 웨이퍼 상에 부동화층을 형성하는 단계와,(1) forming a passivation layer on an integrated circuit (IC) semiconductor wafer having Cu wiring therein;

② 상기 부동화층을 통해 단자 비아 개구를 형성하여 상기 Cu 배선을 노출시키는 개구 형성 단계와,An opening forming step of forming a terminal via opening through the passivation layer to expose the Cu wiring;

③ 적어도 상기 노출된 Cu 배선 위와, 상기 단자 비아 개구의 측벽 위와, 상기 단자 비아 개구에 인접한 상기 부동화층의 영역 위에 장벽층을 형성하는 단계와,(3) forming a barrier layer on at least the exposed Cu wiring, on the sidewalls of the terminal via openings, and on the area of the passivation layer adjacent to the terminal via openings;

④ 적어도 상기 단자 비아 개구 내에 있는 상기 장벽층 위와, 상기 단자 비아 개구에 인접한 상기 장벽층의 영역 위에 Al 스택(stack)을 형성하는 단계와,(4) forming an Al stack over at least the barrier layer in the terminal via opening and over an area of the barrier layer adjacent the terminal via opening;

⑤ 상기 Al 스택과 상기 장벽층을 패터닝하고 에칭하는 단계와,Patterning and etching the Al stack and the barrier layer,

⑥ 상기 패터닝된 Al 스택 상에 제 2 부동화층을 형성하는 단계와,⑥ forming a second passivation layer on the patterned Al stack,

⑦ 상기 패터닝된 상기 Cu 배선의 상부에 위치하는 Al 스택의 영역을 노출시키도록 상기 제 2 부동화층 내에 제 2 개구를 제공하는 단계를 포함하는Providing a second opening in the second passivation layer to expose a region of an Al stack located on top of the patterned Cu wiring.

방법을 사용함으로써 달성될 수 있다.Can be achieved by using a method.

본 발명의 일 실시예에서, 전술한 단계 ⑦은 상기 Cu 배선의 상부에 위치하지 않은 상기 패터닝된 Al 스택 영역을 노출시키도록 상기 제 2 부동화층 내에 제 2 개구를 제공하는 것을 포함하는 단계 ⑦'로 대체된다.In one embodiment of the present invention, step ⑦ described above includes providing a second opening in the second passivation layer to expose the patterned Al stack region not located on top of the Cu wiring. Is replaced by.

본 발명의 또다른 실시예에서, 본 발명의 방법은 먼저 단계 ① 내지 단계 ⑦ 또는 단계 ① 내지 전술한 단계 ⑦'을 수행한 후 반도체 패키지에 IC 구조체를 상호 접속하는 수단을 제공하기 위하여 상기 노출된 Al 스택, 즉 Al 패드에 와이어 본드 또는 C4 땜납 재료를 제공하는 단계를 포함한다.In another embodiment of the present invention, the method of the present invention first performs steps ① through ⑦ or steps 1 through 7 above, and then provides the means for interconnecting the IC structure to the semiconductor package. Providing a wire bond or C4 solder material to the Al stack, ie the Al pad.

본 발명의 또다른 측면에 따라, 하부 Cu 배선과 전기적으로 도통되는 Al 콘택트를 포함하는 IC 구조체가 제공된다. 구체적으로, 본 발명의 IC 구조체는 내부에 Cu 배선을 구비하는 반도체 웨이퍼와, 상기 Cu 배선을 노출시키도록 상기 반도체 웨이퍼 상에 있으며 내부에 단자 비아 개구를 구비하는 부동화층과, 적어도 상기 노출된 Cu 배선 위와, 상기 단자 비아 개구의 측벽 위와, 상기 단자 비아 개구에 인접한 상기 부동화층 위에 위치하는 장벽층과, 상기 장벽층 상의 Al 스택과, 상기 Al 스택 상에 위치하여 상기 하부 Cu 배선의 상부의 상기 Al 스택 영역을 노출시키는 개구를 내부에 갖는 제 2 부동화층을 포함한다.In accordance with another aspect of the present invention, an IC structure is provided that includes an Al contact that is electrically conductive with a lower Cu interconnect. Specifically, the IC structure of the present invention includes a semiconductor wafer having Cu wiring therein, a passivation layer on the semiconductor wafer so as to expose the Cu wiring, and having a terminal via opening therein, and at least the exposed Cu. A barrier layer over a wiring, over a sidewall of the terminal via opening, over a passivation layer adjacent to the terminal via opening, an Al stack on the barrier layer, and a top of the lower Cu wiring over the Al stack. And a second passivation layer having an opening therein that exposes the Al stack region.

일 실시예에서, IC 구조체는 상기 패터닝된 Al 스택 상에 위치하며 하부 Cu 배선 상에 위치하지 않은 상기 패터닝된 Al 스택 영역을 노출시키는 개구를 내부에 구비하는 제 2 부동화층을 포함한다.In one embodiment, the IC structure includes a second passivation layer having an opening therein that exposes the patterned Al stack region located on the patterned Al stack and not on the lower Cu interconnection.

도 1은 하부 구리 상호 접속 도선에 직접적으로 와이어 본드를 접속하는 종래 기술의 IC BEOL 구조체에 대한 도면,1 is a diagram of a prior art IC BEOL structure for connecting wire bonds directly to a lower copper interconnect lead;

도 2a 내지 도 2d는 콘택트층이 노출된 구리 배선 상부에 위치하는 IC 구조체를 제조하기 위해 본 발명에서 채용되는 공정 단계를 도시한 도면,2A-2D show the process steps employed in the present invention to fabricate an IC structure overlying a copper wiring with contact layers exposed;

도 3a 내지 도 3d는 본드 패드의 콘택트 영역이 구리 접속부가 형성되어 있는 패드 영역으로부터 떨어져 있는 IC 구조체를 제조하기 위해 본 발명에서 채용되는 공정 단계를 도시한 도면,3A-3D illustrate process steps employed in the present invention to fabricate an IC structure in which the contact regions of the bond pads are separated from the pad regions in which copper connections are formed;

도 4a 내지 도 4d는 와이어 본딩과 C4(땜납 볼) 상호 접속 후의 도 2d 및 도 3d의 상호 접속 구조체를 도시한 도면,4A-4D show the interconnect structure of FIGS. 2D and 3D after wire bonding and C4 (solder ball) interconnects;

도 5a 및 도 5b는 본 발명에 따라 생성된 두 유형의 구조체에 대한 평면도.5A and 5B are plan views of two types of structures produced in accordance with the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

20: 웨이퍼 22: Cu 배선20: wafer 22: Cu wiring

24: 부동화층 26: 단자 비아 개구24: passivation layer 26: terminal via opening

28: 장벽층 30: Al 스택28: barrier layer 30: Al stack

32: 제 2 부동화층 34: 제 2 개구32: second passivation layer 34: second opening

첨부된 도면을 참조하여 본 발명을 보다 상세하게 기술할 것인데, 도면에서 동일한 대응되는 구성 요소에 대하여 동일한 도면 부호를 사용한다. Al 콘택트가 하부 Cu 배선과 전기적으로 도통되는 본 발명에 따른 IC 구조체를 제조하기 위해 본 발명에서 채용되는 두 실시예를 도시하는 도 2a 내지 도 2d와 도 3a 내지 도 3d를 먼저 참조한다. 도 2a 내지 도 2d에서 Al 콘택트는 하부 구리 배선의 상부에 바로 위치하는 반면, 도 3a 내지 도 3d에서 Al 콘택트는 하부 Cu 배선의 상부에 위치하지 않는다.DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in more detail with reference to the accompanying drawings in which like reference numerals are used for like corresponding components. Reference is first made to FIGS. 2A-2D and FIGS. 3A-3D, which show two embodiments employed in the present invention for fabricating an IC structure in accordance with the present invention in which Al contacts are electrically conductive with underlying Cu wiring. In FIGS. 2A-2D, the Al contact is located directly on top of the lower copper interconnection, while in FIGS. 3A-3D, the Al contact is not located on top of the lower Cu interconnection.

도 2a 및 도 3a에는 본 발명에서 채용될 수 있는 전형적인 IC 구조체가 도시되어 있다. 구체적으로, IC 구조체는 Cu 배선(22)이 자체 표면 내에 매립되어 있는 반도체 웨이퍼(20)와 그 상부에 형성되어 있는 부동화층(24)을 포함한다. 이러한 구조체는 반도체 웨이퍼(20) 내에 다수의 IC 소자 영역을 포함할 수도 있다. 명료함을 위해 이러한 IC 소자 영역을 도면에 도시하지 않는다.2A and 3A illustrate typical IC structures that may be employed in the present invention. Specifically, the IC structure includes a semiconductor wafer 20 in which the Cu wiring 22 is embedded in its surface and a passivation layer 24 formed thereon. Such a structure may include a plurality of IC device regions in the semiconductor wafer 20. For the sake of clarity, these IC element areas are not shown in the figure.

도 2a 또는 도 3a의 IC 구조체는 이러한 구조체를 생산하는 기술 분야의 당업자에게 잘 알려져 있는 방법을 사용하여 제조된다. 이는 표준 리소그래피 공정에 의해 반도체 웨이퍼 내에 비아 개구를 제공하는 단계와, 그 비아를 Cu로 충진하는 단계와, Cu가 충진된 구조체를 화학 기계 연마(chemical mechnical polishing: CMP) 또는 평탄화된 구조체를 형성할 수 있는 임의의 다른 연마 단계로 처리하는 단계와, 스퍼터링, 화학 기상 증착, 플라즈마 기상 증착과 같은 임의의 공지된 증착 기법을 사용하여 상기 구조체의 표면 상에 부동화층을 증착하는 단계를 포함하지만, 여기에 한정되지는 않는다.The IC structure of FIG. 2A or 3A is manufactured using methods well known to those skilled in the art of producing such structures. This provides a via opening in the semiconductor wafer by a standard lithography process, filling the via with Cu, and forming a chemical mechnical polishing (CMP) or planarized structure of the Cu-filled structure. Treating with any other polishing step that may be, and depositing a passivation layer on the surface of the structure using any known deposition technique, such as sputtering, chemical vapor deposition, plasma vapor deposition, It is not limited to.

웨이퍼(20)를 구성하는 반도체 재료는 반도체 성질을 갖는 어떠한 재료로도 구성될 수 있다. 이러한 재료는 Si, Ge, GaAs, GaP, InAs, InP는 물론 SiO2와 다이아몬드형 탄소와 같은 유전 재료를 포함한다. 이들 반도체 재료 중에서 Si를 웨이퍼(20)의 반도체 재료로 사용하는 것이 본 발명에서 매우 바람직하다.The semiconductor material constituting the wafer 20 may be composed of any material having semiconductor properties. Such materials include Si, Ge, GaAs, GaP, InAs, InP as well as dielectric materials such as SiO 2 and diamond-like carbon. Of these semiconductor materials, it is very preferable in the present invention to use Si as the semiconductor material of the wafer 20.

본 발명에 따라, 부동화층(24)은 습기 및/또는 이온이 Cu 배선(22)과 접촉할 수 없게 할 수 있는 적어도 하나의 재료를 포함한다. 적절한 재료에는 SiO2, Si3N4와 그 조합물이 포함되지만 여기에 한정되는 것은 아니다. 본 발명에서 채용될 수 있는 아주 바람직한 부동화층은 SiO2/Si3N4또는 Si3N4/SiO2/Si3N4와 같은 전술한 재료의 조합물이다.In accordance with the present invention, passivation layer 24 comprises at least one material that may prevent moisture and / or ions from contacting Cu wiring 22. Suitable materials include, but are not limited to, SiO 2 , Si 3 N 4 and combinations thereof. Very preferred passivating layers that can be employed in the present invention are combinations of the foregoing materials, such as SiO 2 / Si 3 N 4 or Si 3 N 4 / SiO 2 / Si 3 N 4 .

비록 부동화층의 두께가 그 부동화층을 형성하는 데 사용되는 재료의 유형에 따라 달라질 수 있지만, 부동화층의 전형적인 두께는 약 500Å 내지 약 20,000Å이다. 더욱 바람직하게는 부동화층의 두께는 전반적으로 약 5000Å 내지 약 10,000Å이다. 산화물과 질화물의 조합이 사용되는 실시예에서는, 부착층으로 작용하는 제 1 선택적 질화물층은 약 100Å, 혹은 그 미만, 내지 약 1000Å의 두께를 갖고, 산화물층은 약 5000Å 내지 약 10,000Å의 두께를 가지며, 다른 질화물층은 약 5000Å 내지 약 10,000Å의 두께를 갖는다. 질화물, 산화물, 질화물 부동화층을 사용하는 실시예에서 더욱 바람직하게는, 제 1 선택적 질화물층의 두께는 약 400Å 내지 약 900Å이고, 산화물층의 두께는 약 5000Å 내지 약 10,000Å이며, 다른 질화물의 두께는 약 5000Å 내지 약 10,000Å이다.Although the thickness of the passivation layer may vary depending on the type of material used to form the passivation layer, typical thicknesses of the passivation layer are from about 500 kPa to about 20,000 kPa. More preferably, the passivation layer has a thickness of about 5000 kPa to about 10,000 kPa overall. In embodiments where a combination of oxides and nitrides is used, the first selective nitride layer serving as an adhesion layer has a thickness of about 100 kPa, or less, to about 1000 kPa, and the oxide layer has a thickness of about 5000 kPa to about 10,000 kPa. And the other nitride layer has a thickness of about 5000 mm 3 to about 10,000 mm 3. More preferably in embodiments using nitride, oxide, or nitride passivation layers, the thickness of the first selective nitride layer is from about 400 kPa to about 900 kPa, the thickness of the oxide layer is from about 5000 kPa to about 10,000 kPa, and the thickness of other nitrides Is about 5000 kPa to about 10,000 kPa.

그 다음으로 도 2b 또는 도 3b에 도시한 바와 같이, 부동화층을 통하여 매립된 Cu 배선(22)을 노출시키는 단자 비아 개구(26)를 형성하도록 부동화층(24)을 패터닝한다. 단자 비아 개구는, 포토레지스트를 부동화층에 제공하는 단계와, 포토레지스트를 패터닝하는 단계와, RIE와 같은 건식 에칭 공정 또는 습식 화학 에칭 공정을 사용하여 패터닝된 포토레지스트를 에칭하는 단계와, 포토레지스트를 제거하는 단계를 포함하는 당업자에게 잘 알려져 있는 표준 리소그래피 기법을 사용하여 형성된다. 이렇게 하여 Cu 배선(22)을 노출시키는 단자 비아 개구(26)를 갖는 도 2b 또는 도 3b의 구조체가 제공된다.Next, as shown in FIG. 2B or 3B, the passivation layer 24 is patterned to form terminal via openings 26 exposing the embedded Cu wiring 22 through the passivation layer. The terminal via opening includes the steps of providing a photoresist to the passivation layer, patterning the photoresist, etching the patterned photoresist using a dry etching process or a wet chemical etching process such as RIE, and It is formed using standard lithography techniques that are well known to those skilled in the art including the step of removing. This provides the structure of FIG. 2B or 3B with terminal via openings 26 exposing the Cu wiring 22.

구조체 내에 단자 비아 개구(26)를 형성한 후에, 적어도 노출된 Cu 배선 영역 위와, 단자 비아 개구(26)의 측벽 위와, 단자 비아 개구에 인접한 부동화층(24)의 표면 위에 장벽층(28)을 형성한다. 당업자에게 알려져 있는 전류의 처리량을 보장하는 어떠한 장벽층도 본 발명에서 사용할 수 있다. 본 발명에 사용할 수 있는 적절한 장벽층의 예는 TaN, TiN, Ta, Cr, W와 그 조합물을 포함하지만 여기에 한정되지는 않는다. 이들 재료 중에서 TaN으로 장벽층(28)을 구성하는 것이 매우 바람직하다.After forming the terminal via opening 26 in the structure, a barrier layer 28 is formed over at least the exposed Cu wiring region, over the sidewall of the terminal via opening 26, and over the surface of the passivation layer 24 adjacent the terminal via opening. Form. Any barrier layer that ensures throughput of currents known to those skilled in the art can be used in the present invention. Examples of suitable barrier layers that can be used in the present invention include, but are not limited to, TaN, TiN, Ta, Cr, W and combinations thereof. Among these materials, it is highly desirable to configure the barrier layer 28 with TaN.

장벽층은 당업자에 잘 알려져 있는 침착(deposition) 기법을 사용하여 형성된다. 그러므로, 스퍼터링, 화학 기상 증착, 플라즈마 기상 증착, 전기 도금, 무전해 도금, 그 밖의 유사 침착 기법에 의해 장벽층을 형성할 수 있다. 본 발명에서 형성되는 장벽층의 두께가 변할 수 있지만, 장벽층의 두께는 전형적으로 약 100Å 내지 약 1500Å이다. 더욱 바람직하게는 장벽층(28)의 두께는 이 약 300Å 내지 약 800Å이다.The barrier layer is formed using deposition techniques well known to those skilled in the art. Therefore, the barrier layer can be formed by sputtering, chemical vapor deposition, plasma vapor deposition, electroplating, electroless plating, and other similar deposition techniques. Although the thickness of the barrier layer formed in the present invention may vary, the thickness of the barrier layer is typically from about 100 kPa to about 1500 kPa. More preferably, the thickness of the barrier layer 28 is about 300 kPa to about 800 kPa.

본 발명의 다음 단계에 따라, 적어도 단자 비아 개구(26) 내에 있는 장벽층(28)의 표면과 단자 비아 개구에 인접한 장벽층 영역 위에 Al 스택(30)을 형성한다. 본 명세서에서 Al 스택이란 용어는 최외각 층이 Al 또는 Al 합금을 포함하는 다수의 금속성층을 나타내는 데 사용된다. 도면에는 Al 스택이 한 층으로 도시되어 있다. 본 발명에서 채용할 수 있는 매우 바람직한 Al 스택 구성은 Ti/TiN/AlCu를 포함한다. Ti/AlCu/TiN, Ti/Al/TiN, Ti/TiN/AlCuSi/TiN 또는 Ti/AlCuSi와 같은 다른 Al 스택들도 본 발명에서 채용될 수 있다. Al-Cu-Si, Al-Cu 또는 Al의 합금 또한 가능한 Al 스택으로 본 명세서에서 고려된다.According to the next step of the present invention, an Al stack 30 is formed at least on the surface of the barrier layer 28 in the terminal via opening 26 and the barrier layer region adjacent to the terminal via opening. The term Al stack is used herein to refer to a plurality of metallic layers where the outermost layer comprises Al or an Al alloy. The Al stack is shown in one layer in the figure. Very preferred Al stack configurations that can be employed in the present invention include Ti / TiN / AlCu. Other Al stacks such as Ti / AlCu / TiN, Ti / Al / TiN, Ti / TiN / AlCuSi / TiN or Ti / AlCuSi may also be employed in the present invention. Al-Cu-Si, Al-Cu or alloys of Al are also contemplated herein as possible Al stacks.

Al 스택은 장벽층(28)을 형성하는 데 유용한 임의의 전술한 침착 기법을 사용하여 형성된다. 전형적으로 스퍼터링이 Al 스택(30)을 증착하는 바람직한 수단이다. Al 스택(30)의 두께가 변할 수도 있지만, 전반적으로 Al 스택은 약 1000Å 내지 20,000Å의 두께를 갖는다. 더욱 바람직하게는, Al 스택의 두께는 약 5000Å 내지 약 10,000Å이다.The Al stack is formed using any of the foregoing deposition techniques useful for forming barrier layer 28. Sputtering is typically the preferred means of depositing the Al stack 30. Although the thickness of the Al stack 30 may vary, overall the Al stack has a thickness of about 1000 GPa to 20,000 GPa. More preferably, the Al stack has a thickness of about 5000 mm 3 to about 10,000 mm 3.

그런 다음 당업계에 알려져 있는 표준 기법을 사용하여 Al 스택과 장벽층을 패터닝하고 에칭한다. 예를 들어, 통상적인 리소그래피에 의해 Al 스택과 장벽층을 패터닝하고, 반응성 이온 에칭에 의해 에칭할 수 있다.The Al stack and barrier layer are then patterned and etched using standard techniques known in the art. For example, the Al stack and barrier layer can be patterned by conventional lithography and etched by reactive ion etching.

부동화층(24)을 형성하는 데 사용된 전술한 임의의 공지된 증착 기법을 사용하여 제 2 부동화층(32)을 형성할 수 있다. 유기 부동화층은 물론 무기 부동화층을 부동화층(32)으로 채용될 수 있다. 무기 재료를 제 2 부동화층(32)으로 채용하는 경우, 산화물/질화물 조합을 사용한다. 무기 부동화층, 예를 들어 층(32)의 두께는 각각 약 2000Å 내지 약 10,000Å이고, 더욱 바람직한 두께는 각각 약 4000Å 내지 약 6000Å이다. 무기 부동화층을 단독으로 사용할 수도 있고, 유기 부동화 재료와 함께 사용할 수도 있다.The second passivation layer 32 can be formed using any of the known deposition techniques described above used to form the passivation layer 24. In addition to the organic passivation layer, an inorganic passivation layer may be employed as the passivation layer 32. When the inorganic material is employed as the second passivation layer 32, an oxide / nitride combination is used. The thickness of the inorganic passivation layer, for example layer 32, is from about 2000 kPa to about 10,000 kPa, and more preferably from about 4000 kPa to about 6000 kPa, respectively. The inorganic passivation layer may be used alone or in combination with an organic passivation material.

유기 부동화층을 층(32)으로 사용하는 경우에는 약 1 마이크론 내지 약 5 마이크론의 두께를 갖는 폴리이미드(polyimide) 또는 폴리실록산(polysiloxane)을 사용할 수 있다. 더욱 바람직하게는 유기 부동화층은 약 2 마이크론 내지 약 4 마이크론의 두께를 갖는다.When the organic passivation layer is used as the layer 32, polyimide or polysiloxane having a thickness of about 1 micron to about 5 microns may be used. More preferably, the organic passivation layer has a thickness of about 2 microns to about 4 microns.

패터닝된 장벽층(28), 패터닝된 Al 스택(30), 제 2 부동화층(32)을 포함하는 구조체가 도 2c 또는 도 3c에 도시되어 있다. 도 2d 또는 도 3d는 반도체 패키지와의 전기적 상호 접속부를 형성하기 전의 제조되어 있는 최종 구조체를 도시하고 있다. 구체적으로, 도 2d는 하부 Cu 배선(22) 상의 패터닝된 Al 스택(30) 영역을 노출시키도록 제 2 부동화층(32)의 표면 내에 제 2 개구(34)를 형성하는 본 발명에 따른 단계를 도시하고 있다. 도 3d에서는, 하부 Cu 배선(22) 상에 위치하지 않는 패터닝된 Al 스택 영역을 노출시키도록 제 2 개구(34)가 제 2 부동화층(32)의 표면 내에 형성된다.A structure comprising a patterned barrier layer 28, a patterned Al stack 30, and a second passivation layer 32 is shown in FIG. 2C or 3C. FIG. 2D or FIG. 3D shows the final structure being fabricated prior to forming the electrical interconnect with the semiconductor package. Specifically, FIG. 2D illustrates a step according to the present invention for forming a second opening 34 in the surface of the second passivation layer 32 to expose a region of the patterned Al stack 30 on the lower Cu interconnect 22. It is shown. In FIG. 3D, a second opening 34 is formed in the surface of the second passivation layer 32 to expose the patterned Al stack region not located on the lower Cu wiring 22.

본 발명에서, 최종 비아 개구로 지칭될 수도 있는 제 2 개구는 단자 비아 개구(26)를 형성하는 것과 관련하여 전술한 유형의 표준 리소그래피 기법을 사용하여 형성된다. 본 발명을 나타내는 도 2d 또는 도 3d에 도시되어 있는 구조체는 본 명세서에서 Al 콘택트 또는 Al 본드 패드로 지칭되는 패터닝된 Al 스택(30)의 노출 영역을 포함한다. 이 Al 콘택트는 하부 Cu 배선과 전기적으로 도통된다. 그러므로 Al 콘택트는 종래 기술의 구조체에서 언급한 결점을 극복한다.In the present invention, the second opening, which may be referred to as the final via opening, is formed using standard lithography techniques of the type described above in connection with forming the terminal via opening 26. The structure shown in FIG. 2D or FIG. 3D representing the present invention includes an exposed area of the patterned Al stack 30, referred to herein as an Al contact or an Al bond pad. This Al contact is electrically conductive with the lower Cu wiring. Al contacts therefore overcome the drawbacks mentioned in the prior art structures.

도 2d에 도시한 구조체의 평면도는 도 5a에 도시되어 있고, 도 3d에 도시한 구조체의 평면도는 도 5b에 도시되어 있다. 구체적으로, 도 5a 및 도 5b는 Al 콘택트 또는 패드(40), 제 2 부동화층 내에 있는 제 2 개구(34), 단자 비아 개구(26), 단자 비아 이미지(26a, 26b)를 포함한다. 도 5b에서, Al 콘택트는 단자 비아 개구에 가까운 곳에 위치하고 Al 콘택트의 짧은 부분과 접속한다.The top view of the structure shown in FIG. 2D is shown in FIG. 5A, and the top view of the structure shown in FIG. 3D is shown in FIG. 5B. Specifically, FIGS. 5A and 5B include an Al contact or pad 40, a second opening 34 in the second passivation layer, a terminal via opening 26, and terminal via images 26a and 26b. In FIG. 5B, the Al contact is located close to the terminal via opening and connects with a short portion of the Al contact.

본 발명의 또다른 측면이 도 4a 내지 도 4d에 도시되어 있다. 구체적으로, 도 4a 내지 도 4d는 (도 4a 및 도 4c에 도시한 바와 같이) 와이어 본드(36) 또는 (도 4b 및 도 4d에 도시한 바와 같이) C4 땜납 재료(38)를 포함하는 상호 접속 IC 구조체를 도시하고 있다.Another aspect of the invention is shown in FIGS. 4A-4D. Specifically, FIGS. 4A-4D are interconnects comprising wire bonds 36 (as shown in FIGS. 4A and 4C) or C4 solder material 38 (as shown in FIGS. 4B and 4D). An IC structure is shown.

와이어 본드가 사용되는 경우, 도선은 금 또는 금 합금과 같은 임의의 도전성 재료로 이루어질 수 있지만 여기에 한정되는 것은 아니며, 당업자에게 잘 알려져 있는 본딩 기법을 사용하여 본드가 형성된다. C4 땜납 재료를 채용하는 경우, ??납은 Pb-Sn과 같은 Pb 함유 합금을 포함한다. C4 상호 접속 역시 당업자에게 잘 알려져 있는 C4 공정 기법을 사용하여 형성된다.When wire bonds are used, the leads may be made of any conductive material, such as gold or gold alloy, but are not limited thereto, and the bonds are formed using bonding techniques well known to those skilled in the art. In the case of employing a C4 solder material, the lead includes a Pb-containing alloy such as Pb-Sn. C4 interconnects are also formed using C4 process techniques well known to those skilled in the art.

도 4a 내지 도 4d에서, Al 콘택트를 포함하는 것으로 도시된 상호 접속 구조체가 본 발명의 도면에 도시되지 않은 반도체 패키지에 본딩된다.In FIGS. 4A-4D, an interconnect structure shown as including Al contacts is bonded to a semiconductor package not shown in the drawings of the present invention.

본 발명에 따른 방법은 Cu-Al 상호 혼합 문제를 제거하는 것은 물론 Cu 배선이 에칭 화학 물질에 노출되거나 그에 의해 공격당할 위험을 상당히 줄인다는 것을 주목해야 한다. 또한, Al 콘택트 하부 영역이 Cu 배선 레벨 내에 와이어 채널을 제공하는 데 사용될 수도 있다.It should be noted that the method according to the present invention not only eliminates Cu-Al intermixing problems but also significantly reduces the risk of Cu wiring being exposed to or attacked by etching chemicals. In addition, an Al contact subregion may be used to provide a wire channel within the Cu wiring level.

특히 바람직한 실시예를 참조하여 본 발명을 도시하고 기술하였지만, 당업자라면 본 발명의 사상과 범주를 벗어나지 않고 형태와 상세한 내용에 대해 전술한 변경 및 다른 변경이 이루어질 수 있다는 것을 이해할 것이다. 그러므로 본 발명이 기술되고 도시된 그 형태에 한정되는 것이 아니라 첨부된 특허 청구 범위의 범주 내에 속하는 것으로 해석되어야 한다.While the present invention has been illustrated and described with reference to particularly preferred embodiments, those skilled in the art will understand that the foregoing and other changes may be made in form and detail without departing from the spirit and scope of the invention. Therefore, the present invention should not be limited to the forms described and illustrated, but should be construed as falling within the scope of the appended claims.

본 발명의 방법에 따라, IC 구조체의 하부 Cu 배선 영역을 포함하거나 또는 포함하지 않는 영역 내에 Al 콘택트가 형성됨으로써, 노출된 구리를 피복하여 외적 요인에 의한 공격이 방지되고 본드를 형성하는 데 사용된 재료와 하부 구리의 혼합이 방지되어 종래의 칩 패키징 기법을 사용하여 신뢰성있는 패키징을 수행할 수 있다.According to the method of the present invention, an Al contact is formed in an area including or not including the lower Cu wiring area of the IC structure, thereby covering the exposed copper to prevent attack by external factors and to form a bond. Mixing of the material with the underlying copper is prevented to enable reliable packaging using conventional chip packaging techniques.

Claims (34)

구리(Cu) 배선과 전기적으로 도통되는 알루미늄(Al) 콘택트를 형성하는 방법에 있어서,In the method of forming an aluminum (Al) contact electrically conductive with a copper (Cu) wiring, ① 자체 내부에 Cu 배선을 구비하는 집적 회로(integrated circuit: IC) 반도체 웨이퍼 상에 부동화층(passivating layer)을 형성하는 단계와,(1) forming a passivating layer on an integrated circuit (IC) semiconductor wafer having Cu wiring therein; ② 상기 부동화층을 통해 단자 비아 개구를 형성하여 상기 Cu 배선을 노출시키는 개구 형성 단계와,An opening forming step of forming a terminal via opening through the passivation layer to expose the Cu wiring; ③ 적어도 상기 노출된 Cu 배선 위와, 상기 단자 비아 개구의 측벽 위와, 상기 단자 비아 개구에 인접한 상기 부동화층의 영역 상에 장벽층을 형성하는 단계와,(3) forming a barrier layer on at least the exposed Cu wiring, on the sidewalls of the terminal via openings, and on the area of the passivation layer adjacent to the terminal via openings; ④ 적어도 상기 단자 비아 개구 내에 있는 상기 장벽층 위와, 상기 단자 비아 개구에 인접한 상기 장벽층의 영역 위에 Al 스택을 형성하는 단계와,(4) forming an Al stack over at least the barrier layer in the terminal via opening and over an area of the barrier layer adjacent the terminal via opening; ⑤ 상기 Al 스택과 상기 장벽층을 패터닝하고 에칭하는 단계와,Patterning and etching the Al stack and the barrier layer, ⑥ 상기 패터닝된 Al 스택 상에 제 2 부동화층을 형성하는 단계와,⑥ forming a second passivation layer on the patterned Al stack, ⑦ 상기 Cu 배선의 상부에 위치하는 상기 패터닝된 Al 스택의 영역을 노출시키도록 상기 제 2 부동화층 내에 제 2 개구를 제공하는 단계를 포함하는⑦ providing a second opening in the second passivation layer to expose a region of the patterned Al stack located on top of the Cu wiring; 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 1 항에 있어서,The method of claim 1, 상기 단계 ⑦에서, 상기 Cu 배선의 상부에 위치하지 않은 상기 패터닝된 Al 스택의 영역을 노출시키도록 상기 제 2 개구가 상기 제 2 부동화층 내에 제공되는In the step ⑦, the second opening is provided in the second passivation layer to expose an area of the patterned Al stack that is not located on top of the Cu wiring. 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 1 항에 있어서,The method of claim 1, 반도체 패키지와 전기적 상호 접속부를 형성하는 단계를 더 포함하는Further comprising forming an electrical interconnect with the semiconductor package 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 3 항에 있어서,The method of claim 3, wherein 상기 전기적 상호 접속부가 와이어 본딩(wirebonding) 또는 C4 땜납을 포함하는The electrical interconnects include wirebonding or C4 solder 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 2 항에 있어서,The method of claim 2, 반도체 패키지와 전기적 상호 접속부를 형성하는 단계를 더 포함하는Further comprising forming an electrical interconnect with the semiconductor package 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 5 항에 있어서,The method of claim 5, 상기 전기적 상호 접속부가 와이어 본딩 또는 C4 땜납을 포함하는The electrical interconnection comprises wire bonding or C4 solder 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 1 항에 있어서,The method of claim 1, 상기 IC 반도체 웨이퍼가 IC 소자 영역을 포함하는The IC semiconductor wafer includes an IC device region 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 1 항에 있어서,The method of claim 1, 상기 IC 반도체 웨이퍼가 SiO2, 다이아몬드형 탄소, Si, Ge, GaAs, GaP, InAs 또는 InP를 포함하는The IC semiconductor wafer comprises SiO 2 , diamond-like carbon, Si, Ge, GaAs, GaP, InAs or InP 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 8 항에 있어서,The method of claim 8, 상기 IC 반도체 웨이퍼가 Si를 포함하는The IC semiconductor wafer comprises Si 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 1 항에 있어서,The method of claim 1, 상기 부동화층이 SiO2, Si3N4또는 그 조합물을 포함하는The passivation layer comprises SiO 2 , Si 3 N 4, or a combination thereof 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 10 항에 있어서,The method of claim 10, 상기 부동화층이 SiO2/Si3N4또는 Si3N4/SiO2/Si3N4를 포함하는The passivation layer comprises SiO 2 / Si 3 N 4 or Si 3 N 4 / SiO 2 / Si 3 N 4 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 1 항에 있어서,The method of claim 1, 상기 장벽층이 TaN, TiN, Cr, Ta, W, Ti 또는 그 조합물을 포함하는The barrier layer comprises TaN, TiN, Cr, Ta, W, Ti or a combination thereof 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 12 항에 있어서,The method of claim 12, 상기 장벽층이 TaN을 포함하는The barrier layer comprises TaN 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 1 항에 있어서,The method of claim 1, 상기 Al 스택은 최외각층이 Al 또는 Al 합금을 구비하는 다수의 금속층을 포함하는The Al stack includes a plurality of metal layers whose outermost layers comprise Al or an Al alloy. 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 14 항에 있어서,The method of claim 14, 상기 Al 스택이 Ti/TiN/AlCu, Ti/AlCu/TiN, Ti/Al/TiN, Ti/TiN/AlCuSi/TiN 또는 Ti/AlCuSi인The Al stack is Ti / TiN / AlCu, Ti / AlCu / TiN, Ti / Al / TiN, Ti / TiN / AlCuSi / TiN or Ti / AlCuSi 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 1 항에 있어서,The method of claim 1, 상기 제 2 부동화층이 폴리이미드(polyimide)와 폴리실록산(polysiloxane)으로 이루어진 그룹에서 선택된 유기 폴리머인The second passivation layer is an organic polymer selected from the group consisting of polyimide and polysiloxane. 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 16 항에 있어서,The method of claim 16, 상기 제 2 부동화층이 폴리이미드인The second passivation layer is a polyimide 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 1 항에 있어서,The method of claim 1, 상기 제 2 부동화층이 SiO2, Si3N4, SiO2/Si3N4, Si3N4/SiO2/Si3N4로 이루어진 그룹에서 선택된 무기 재료인The second passivation layer is an inorganic material selected from the group consisting of SiO 2 , Si 3 N 4 , SiO 2 / Si 3 N 4 , Si 3 N 4 / SiO 2 / Si 3 N 4 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 제 1 항에 있어서,The method of claim 1, 상기 제 2 부동화층이 유기 폴리머와 무기 재료의 조합물인The second passivating layer is a combination of an organic polymer and an inorganic material. 알루미늄 콘택트 형성 방법.Method of forming aluminum contacts. 하부 Cu 배선과 전기적으로 도통되는 Al 콘택트를 포함하는 집적 회로(IC) 구조체에 있어서,An integrated circuit (IC) structure comprising an Al contact in electrical communication with a lower Cu interconnection, Cu 배선이 자체 내부에 매립된 IC 반도체 웨이퍼와,An IC semiconductor wafer having Cu wiring embedded therein, 상기 반도체 웨이퍼 위에 위치하며 상기 Cu 배선을 노출시키도록 자체 내부에 단자 비아 개구를 구비하는 제 1 부동화층과,A first passivation layer on the semiconductor wafer and having a terminal via opening therein to expose the Cu wiring; 적어도 상기 노출된 Cu 배선 위와, 상기 단자 비아 개구의 측벽 위와, 상기 단자 비아 개구에 인접한 상기 부동화층 위에 위치하는 장벽층과,A barrier layer over at least the exposed Cu wiring, over a sidewall of the terminal via opening, and over the passivation layer adjacent to the terminal via opening; 상기 장벽층 상의 Al 스택과,An Al stack on the barrier layer, 상기 Al 스택 위에 위치하며 자체 내부에 상기 Cu 배선을 덮고 있는 상기 Al 스택을 노출시키는 개구를 갖는 제 2 부동화층을 포함하는A second passivation layer over the Al stack and having an opening therein that exposes the Al stack overlying the Cu wiring; 집적 회로 구조체.Integrated circuit structure. 제 20 항에 있어서,The method of claim 20, 상기 제 2 부동화층이 상기 Cu 배선을 덮고 있지 않는 상기 Al 스택을 노출시키는 개구를 구비하는The second passivation layer having an opening that exposes the Al stack not covering the Cu wiring. 집적 회로 구조체.Integrated circuit structure. 제 20 항에 있어서,The method of claim 20, 상기 IC 반도체 웨이퍼가 IC 소자 영역을 포함하는The IC semiconductor wafer includes an IC device region 집적 회로 구조체.Integrated circuit structure. 제 22 항에 있어서,The method of claim 22, 상기 IC 반도체 웨이퍼가 SiO2, 다이아몬드형 탄소, Si, Ge, GaAs, GaP, InAs 또는 InP를 포함하는The IC semiconductor wafer comprises SiO 2 , diamond-like carbon, Si, Ge, GaAs, GaP, InAs or InP 집적 회로 구조체.Integrated circuit structure. 제 23 항에 있어서,The method of claim 23, 상기 IC 반도체 웨이퍼가 Si를 포함하는The IC semiconductor wafer comprises Si 집적 회로 구조체.Integrated circuit structure. 제 20 항에 있어서,The method of claim 20, 상기 제 1 부동화층이 SiO2, Si3N4또는 그 조합물을 포함하는The first passivation layer comprises SiO 2 , Si 3 N 4, or a combination thereof 집적 회로 구조체.Integrated circuit structure. 제 25 항에 있어서,The method of claim 25, 상기 제 1 부동화층이 SiO2/Si3N4또는 Si3N4/SiO2/Si3N4를 포함하는The first passivation layer comprises SiO 2 / Si 3 N 4 or Si 3 N 4 / SiO 2 / Si 3 N 4 집적 회로 구조체.Integrated circuit structure. 제 20 항에 있어서,The method of claim 20, 상기 장벽층이 TaN, TiN, Cr, Ta, W, Ti 또는 그 조합물을 포함하는The barrier layer comprises TaN, TiN, Cr, Ta, W, Ti or a combination thereof 집적 회로 구조체.Integrated circuit structure. 제 27 항에 있어서,The method of claim 27, 상기 장벽층이 TaN을 포함하는The barrier layer comprises TaN 집적 회로 구조체.Integrated circuit structure. 제 20 항에 있어서,The method of claim 20, 상기 Al 스택은 최외각층이 Al 또는 Al 합금을 구비하는 다수의 금속층을 포함하는The Al stack includes a plurality of metal layers whose outermost layers comprise Al or an Al alloy. 집적 회로 구조체.Integrated circuit structure. 제 29 항에 있어서,The method of claim 29, 상기 Al 스택이 Ti/TiN/AlCu, Ti/AlCu/TiN, Ti/Al/TiN, Ti/TiN/AlCuSi/TiN 또는 Ti/AlCuSi인The Al stack is Ti / TiN / AlCu, Ti / AlCu / TiN, Ti / Al / TiN, Ti / TiN / AlCuSi / TiN or Ti / AlCuSi 집적 회로 구조체.Integrated circuit structure. 제 20 항에 있어서,The method of claim 20, 상기 제 2 부동화층이 폴리이미드와 폴리실록산으로 이루어진 그룹에서 선택된 유기 폴리머인The second passivation layer is an organic polymer selected from the group consisting of polyimide and polysiloxane 집적 회로 구조체.Integrated circuit structure. 제 31 항에 있어서,The method of claim 31, wherein 상기 제 2 부동화층이 폴리이미드인The second passivation layer is a polyimide 집적 회로 구조체.Integrated circuit structure. 제 20 항에 있어서,The method of claim 20, 상기 제 2 부동화층이 SiO2, Si3N4, SiO2/Si3N4, Si3N4/SiO2/Si3N4로 이루어진 그룹에서 선택된 무기 재료인The second passivation layer is an inorganic material selected from the group consisting of SiO 2 , Si 3 N 4 , SiO 2 / Si 3 N 4 , Si 3 N 4 / SiO 2 / Si 3 N 4 집적 회로 구조체.Integrated circuit structure. 제 20 항에 있어서,The method of claim 20, 상기 제 2 부동화층이 유기 폴리머와 무기 재료의 조합물인The second passivating layer is a combination of an organic polymer and an inorganic material. 집적 회로 구조체.Integrated circuit structure.
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US6187680B1 (en) 2001-02-13

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