KR20000027924A - Method for forming metal line of semiconductor devices - Google Patents
Method for forming metal line of semiconductor devices Download PDFInfo
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- KR20000027924A KR20000027924A KR1019980045969A KR19980045969A KR20000027924A KR 20000027924 A KR20000027924 A KR 20000027924A KR 1019980045969 A KR1019980045969 A KR 1019980045969A KR 19980045969 A KR19980045969 A KR 19980045969A KR 20000027924 A KR20000027924 A KR 20000027924A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 접합 영역에 접속되는 금속 패드를 먼저 형성한 후 금속 패드 상부에 금속 배선을 형성하여 콘택의 형성 및 콘택의 매립을 용이하게 할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device. In particular, a metal pad connected to a junction region is first formed, and then a metal wiring is formed on the metal pad to facilitate contact formation and embedding of the contact. A metal wiring formation method of an element.
MOS 구조의 DRAM 소자는 캐패시터를 이용하여 정보를 저장하는 셀 영역과 정보의 입출력 및 증폭등에 관계된 각종 회로들로 구성된 주변 회로 영역으로 크게 나눌 수 있다. 주변 회로 영역에는 각 소자에 전원 공급 및 전기적 연결을 위한 금속 배선 공정이 반드시 실시되어야 한다. 금속 배선 공정은 보통 금속선이 형성되는 소오스/드레인 영역에 콘택을 형성하는 공정, 콘택을 금속으로 매립하는 공정 및 식각 공정을 실시하여 금속선을 형성하는 공정으로 이루어진다.A DRAM device having a MOS structure can be roughly divided into a cell area for storing information using a capacitor and a peripheral circuit area including various circuits related to input / output and amplification of information. In the peripheral circuit area, a metal wiring process must be performed for powering and electrical connection to each device. The metal wiring process usually includes a process of forming a contact in a source / drain region where a metal line is formed, a process of filling a contact with a metal, and a process of forming a metal line by performing an etching process.
DRAM 소자는 셀 영역쪽에 형성되는 캐패시터로 인하여 셀 영역과 주변 회로의 영역의 높이에 차이가 발생하게 된다. 현재 개발중인 64M 및 그 이후의 DRAM 소자에서는 주변 회로 영역의 소오스/드레인 영역에 형성되는 금속선 콘택의 높이가 캐패시터의 구조에 따라 2∼3㎛의 높은 값을 가질 것으로 예상된다. 한편, 한 웨이퍼당 생산되는 소자의 개수를 늘이기 위해 소자의 집적도가 크게 요구됨에 따라 콘택의 크기도 0.3㎛ 이하로 축소될 것이므로 콘택의 종횡비(aspect ratio)는 7∼10 정도 될 것으로 예상된다.The DRAM device has a difference in height between the cell area and the area of the peripheral circuit due to the capacitor formed on the cell area side. It is expected that the height of the metal wire contact formed in the source / drain region of the peripheral circuit region may have a high value of 2 to 3 μm in the DRAM device under development of 64M and later. On the other hand, as the integration degree of the device is required to increase the number of devices produced per wafer, the contact size will also be reduced to 0.3 μm or less, so the aspect ratio of the contact is expected to be about 7-10.
콘택을 매립하는 방법은 스퍼터링에 의한 알루미늄 증착, CVD 방법에 의한 텅스텐 증착, 텅스텐 및 알루미늄을 같이 사용하는 텅스텐 플러그 공정등이 있다. 한편, 상기와 같은 금속을 증착하기 전에 접촉 저항의 감소 및 접착력의 증가를 위해 배리어 메탈(barrier metal) 공정이 반드시 선행되어야 하며, Ti/TiN이 가장 널리 사용된다.Methods of filling the contact include aluminum deposition by sputtering, tungsten deposition by CVD, tungsten plug process using tungsten and aluminum together. On the other hand, a barrier metal process must be preceded to reduce contact resistance and increase adhesion before depositing such a metal, and Ti / TiN is most widely used.
스퍼터링에 의한 알루미늄 증착 공정은 저항이 낮아 소자의 속도 측면에서 유리하지만, 스퍼터링의 공정 특성상 콘택의 종횡비가 약 3 이상일 때는 완벽한 콘택의 매립이 불가능한 측면이 있다. 따라서, 종횡비가 4∼7인 콘택에는 CVD 방법에 의한 텅스텐 매립이나 텅스텐 플러그 방법이 사용되고 있다.Although the aluminum deposition process by sputtering is advantageous in terms of device speed due to low resistance, when the aspect ratio of the contact is about 3 or more, perfect contact is not possible. Therefore, a tungsten buried or tungsten plug method by the CVD method is used for contacts having an aspect ratio of 4 to 7.
콘택의 종횡비가 7 이상일 경우에는 여러 가지 문제점이 발생하게 된다. 즉 산화막의 식각시 재현성이 있는 콘택 프로파일 및 배리어 메탈의 증착시 양호한 기저부의 스텝 커버러지(bottom step coverage)의 확보의 어려움이 있으며, 텅스텐의 경우에도 콘택의 중간에 텅스텐이 채워지지 않는 심(seam) 현상이 발생할 가능성이 있다.When the aspect ratio of the contact is 7 or more, various problems occur. In other words, it is difficult to secure a good contact profile at the time of deposition of the oxide film and a good bottom step coverage during deposition of the barrier metal. ) May occur.
따라서, 본 발명은 소자의 집적도가 증가함에 따라 생성된 콘택이 높은 종횡비를 갖는 경우에도 콘택의 식각 및 매립을 용이하게 할 수 있어 소자의 동작 및 신뢰도를 확보할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Therefore, the present invention can facilitate the etching and filling of the contact even when the contact formed as the integration degree of the device has a high aspect ratio, thereby ensuring the operation and reliability of the device, the metal wiring formation method of the semiconductor device The purpose is to provide.
상술한 목적을 달성하기 위한 본 발명은 반도체 기판 상부의 선택된 영역에 게이트 전극 및 접합 영역을 형성한 후 전체 구조 상부에 층간 절연막을 형성하는 단계와, 상기 층간 절연막을 소정의 두께로 식각한 후 상기 층간 절연막의 선택된 영역을 식각하여 상기 접합 영역을 노출시키는 제 1 콘택 홀을 형성하는 단계와, 전체 구조 상부에 배리어 메탈 및 제 1 금속층을 형성한 후 상기 금속층을 소정 두께로 식각하는 단계와, 상기 소정 두께로 식각된 제 1 금속층을 패터닝하여 금속 패드를 형성한 후 전체 구조 상부에 절연 산화막을 형성하는 단계와, 상기 절연 산화막의 선택된 영역을 식각하여 상기 금속 패드를 노출시키는 제 2 콘택 홀을 형성하는 단계와, 상기 콘택 홀이 매립되도록 전체 구조 상부에 제 2 금속층을 형성한 후 패터닝하여 금속 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is formed by forming a gate electrode and a junction region in the selected region on the semiconductor substrate, and forming an interlayer insulating film on the entire structure, and etching the interlayer insulating film to a predetermined thickness after Etching the selected region of the interlayer insulating layer to form a first contact hole exposing the junction region, forming a barrier metal and a first metal layer over the entire structure, and then etching the metal layer to a predetermined thickness; Patterning the first metal layer etched to a predetermined thickness to form a metal pad, and then forming an insulating oxide film over the entire structure, and forming a second contact hole for etching the selected region of the insulating oxide film to expose the metal pad. And forming a second metal layer on the entire structure such that the contact hole is filled and patterning the metal wiring. Characterized in that it comprises a step of forming.
도 1(a) 내지 도 1(e)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (e) are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 게이트 산화막11 semiconductor substrate 12 gate oxide film
13 : 폴리실리콘막 14 : 텅스텐 실리사이드막13: polysilicon film 14: tungsten silicide film
15 : 마스크 산화막 16 : 스페이서15 mask oxide film 16 spacer
17 : 접합 영역 18 : 산화막17 junction region 18 oxide film
19 : 층간 절연막 20 : 콘택 홀19: interlayer insulating film 20: contact hole
21 : 배리어 메탈 22 : 금속층21 barrier metal 22 metal layer
23 : 금속 패드 24 : 절연 산화막23: metal pad 24: insulating oxide film
25 : 금속 배선25: metal wiring
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 1(a) 내지 도 1(e)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도로서, DRAM의 주변 회로 영역을 도시한 것이다.1 (a) to 1 (e) are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention, showing a peripheral circuit region of a DRAM.
도 1(a)를 참조하면, 반도체 기판(11) 상부에 게이트 산화막(12), 폴리실리콘막(13), 텅스텐 실리사이드막(14) 및 마스크 산화막(15)을 순차적으로 형성한 후 패터닝하여 폴리사이드 구조의 게이트 전극을 형성한다. 게이트 전극 측벽에 스페이서(16)을 형성한 후 불순물 이온 주입 공정을 실시하여 반도체 기판(11)상에 접합 영역(17)을 형성하고, 전체 구조 상부에 산화막(18)을 형성한다. 이후, 셀 영역(A)에는 캐패시터 형성 공정이 진행된다. 셀 영역(A)에 캐패시터가 형성된 후 전체 구조 상부에 층간 절연막(19)을 도포한 후 평탄화 공정을 실시한다.Referring to FIG. 1A, a gate oxide layer 12, a polysilicon layer 13, a tungsten silicide layer 14, and a mask oxide layer 15 are sequentially formed on a semiconductor substrate 11, and then patterned to form a poly A gate electrode of the side structure is formed. After the spacers 16 are formed on the gate electrode sidewalls, an impurity ion implantation process is performed to form the junction regions 17 on the semiconductor substrate 11, and the oxide films 18 are formed over the entire structure. Thereafter, a capacitor forming process is performed in the cell region A. After the capacitor is formed in the cell region A, the interlayer insulating film 19 is applied over the entire structure, and then the planarization process is performed.
도 1(b)를 참조하면, 셀 영역(A) 상부에만 감광막 패턴을 형성한 후 이를 마스크로 주변 회로 영역(B)의 층간 절연막(19)을 소정 두께 식각한다. 주변 회로 영역(B)의 층간 절연막(19)의 선택된 영역을 식각하여 접합 영역(17)을 노출시키는 콘택 홀(20)을 형성한다.Referring to FIG. 1B, after the photoresist pattern is formed only on the cell region A, the interlayer insulating layer 19 of the peripheral circuit region B is etched by a mask with a predetermined thickness. The selected region of the interlayer insulating film 19 in the peripheral circuit region B is etched to form a contact hole 20 exposing the junction region 17.
도 1(c)를 참조하면, 전체 구조 상부에 100∼1000Å 두께의 Ti/TiN막으로 배리어 메탈(21)을 형성한 후 금속층(22)을 형성한다. CMP 공정을 실시하여 셀 영역(A)에 형성된 금속층(22)은 완전히 제거하고 주변 회로 영역(B)은 평탄화시킨다. 셀 영역(A) 상부에 감광막 패턴(도시안됨)을 형성한 후 주변 회로 영역(B)의 금속층(22)을 소정의 두께로 식각한다. 금속층(22)은 텅스텐, 알루미늄 및 알루미늄 합금중 어느 하나를 10000∼30000Å의 두께로 형성한다. 알루미늄 합금은 알루미늄에 구리 또는 실리콘이 함유된 금속이다. 또한, 금속층(22)은 300℃ 이하의 온도에서 6∼20keV의 전력으로 증착한다.Referring to FIG. 1 (c), a barrier metal 21 is formed of a Ti / TiN film having a thickness of 100 to 1000 에 on an entire structure, and then a metal layer 22 is formed. The CMP process is performed to completely remove the metal layer 22 formed in the cell region A and to planarize the peripheral circuit region B. FIG. After forming a photoresist pattern (not shown) on the cell region A, the metal layer 22 of the peripheral circuit region B is etched to a predetermined thickness. The metal layer 22 forms any one of tungsten, aluminum, and an aluminum alloy in thickness of 10000-30000 kPa. Aluminum alloys are metals in which aluminum contains copper or silicon. The metal layer 22 is deposited at a power of 6 to 20 keV at a temperature of 300 ° C. or lower.
도 1(d)를 참조하면, 주변 회로 영역(B)에 잔류하는 금속층(22)을 패터닝하여 금속 패드(23)를 형성한다. 전체 구조 상부에 절연 산화막(24)을 형성한다. 절연 산화막은 접합 영역의 열화를 방지하기 위해 고밀도 플라즈마(High Density Plasma ; HDP) 산화막으로 형성한다. CMP 공정을 실시하여 절연 산화막(24)을 평탄화시킨다. HDP 산화막은 450℃ 이하의 온도에서 15000∼30000Å의 두께로 형성한다.Referring to FIG. 1D, the metal layer 22 remaining in the peripheral circuit region B is patterned to form a metal pad 23. An insulating oxide film 24 is formed over the entire structure. The insulating oxide film is formed of a high density plasma (HDP) oxide film to prevent deterioration of the junction region. The CMP process is performed to planarize the insulating oxide film 24. The HDP oxide film is formed at a thickness of 15000 to 30000 Pa at a temperature of 450 占 폚 or lower.
도 1(e)를 참조하면, 절연 산화막(24)의 선택된 영역을 식각하여 하부의 금속 패드(23)을 노출시키는 콘택 홀을 형성한다. 콘택 홀이 매립되도록 전체 구조 상부에 금속층을 형성한 후 패터닝하여 금속 패드(23) 상부에 금속 배선(25)을 형성한다. 금속층은 텅스텐, 알루미늄 및 알루미늄 합금중 어느 하나를 2000∼10000Å의 두께로 형성한다. 알루미늄 합금은 실리콘 함유 알루미늄 또는 실리콘 및 구리 함유 알루미늄이다.Referring to FIG. 1E, the selected region of the insulating oxide layer 24 is etched to form a contact hole exposing the lower metal pad 23. The metal layer is formed on the entire structure to fill the contact hole, and then patterned to form the metal wire 25 on the metal pad 23. The metal layer forms any one of tungsten, aluminum, and an aluminum alloy to a thickness of 2000-10000 kPa. Aluminum alloys are silicon containing aluminum or silicon and copper containing aluminum.
상술한 바와 같이 본 발명에 의하면 DRAM 소자의 고집적화에 따라 주변 회로 영역의 콘택 홀의 종횡비가 커짐으로 인해 발생되는 콘택의 형성 및 매립 공정의 곤란함을 금속 패드를 형성한 후 금속 배선을 형성하므로써 해결할 수 있다. 즉, 게이트 전극 사이에 형성된 접합 영역과 접속되는 금속 패드는 접합 영역을 노출시키는 콘택 홀의 높이가 낮으므로 용이하게 형성할 수 있다. 또한, 일단 금속 패드가 형성되면 금속 패드의 크기가 접합 영역을 노출시키는 제 1 콘택 홀보다 크므로 이 금속 패드에 연결되는 제 2 콘택 홀은 게이트 전극 사이의 접합 영역에 바로 금속 배선 공정을 실시할 때보다 더 크게 형성할 수 있다. 한편, 산화막의 높이도 감소하므로 훨씬 용이하게 콘택 홀의 형성 및 매립을 가능하게 한다. 이러한 효과는 소자의 크기가 감소됨에 따라 배선 공정의 한계를 극복하여 고집적화에 기여한다.As described above, according to the present invention, it is possible to solve the difficulty of forming and filling the contact, which is caused by the increase in the aspect ratio of the contact hole in the peripheral circuit area due to the high integration of the DRAM device, by forming the metal pad and then forming the metal wiring. have. That is, the metal pads connected to the junction region formed between the gate electrodes can be easily formed because the height of the contact hole exposing the junction region is low. In addition, once the metal pad is formed, the size of the metal pad is larger than that of the first contact hole exposing the junction region, so that the second contact hole connected to the metal pad may be subjected to the metal wiring process directly in the junction region between the gate electrodes. It can be made larger than ever. On the other hand, since the height of the oxide film is also reduced, it is possible to form and fill contact holes much more easily. This effect contributes to high integration by overcoming the limitations of the wiring process as the size of the device is reduced.
Claims (6)
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| KR1019980045969A KR100284138B1 (en) | 1998-10-29 | 1998-10-29 | Metal wiring formation method of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100423619B1 (en) * | 2000-12-27 | 2004-03-22 | 미쓰비시덴키 가부시키가이샤 | Semiconductor integrated circuit device and fabrication process for the same |
| KR100871354B1 (en) * | 2002-06-28 | 2008-12-02 | 매그나칩 반도체 유한회사 | Method for decreasing charging damage using metal dummy pattern |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100423619B1 (en) * | 2000-12-27 | 2004-03-22 | 미쓰비시덴키 가부시키가이샤 | Semiconductor integrated circuit device and fabrication process for the same |
| KR100871354B1 (en) * | 2002-06-28 | 2008-12-02 | 매그나칩 반도체 유한회사 | Method for decreasing charging damage using metal dummy pattern |
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