KR20000027092A - Die bond structure of semiconductor package and manufacturing method thereof - Google Patents
Die bond structure of semiconductor package and manufacturing method thereof Download PDFInfo
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- KR20000027092A KR20000027092A KR1019980044926A KR19980044926A KR20000027092A KR 20000027092 A KR20000027092 A KR 20000027092A KR 1019980044926 A KR1019980044926 A KR 1019980044926A KR 19980044926 A KR19980044926 A KR 19980044926A KR 20000027092 A KR20000027092 A KR 20000027092A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로서, 보다 상세하게는 리드 프레임에 칩(다이)을 접착시킬 때 그 결합력을 강화시킬 수 있는 반도체 패키지의 다이 본드 구조 및 공정 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a die bond structure and a process method of a semiconductor package capable of strengthening a bonding force when bonding a chip (die) to a lead frame.
일반적으로 반도체 제조 공정을 거쳐 생성된 칩(Chip)의 형태는 오염이 되기 쉽고, 전기적인 배선이 형성되어 있지 않다. 이러한 반도체 칩(Chip)을 외부 환경으로부터 보호하고 사용이 용이하도록 모양화(형상화)시킬 뿐만 아니라 동작 기능을 보호할 목적으로 행해지는 어셈블리 작업으로써 반도체 패키지(Package)가 형성된다.In general, the shape of the chip generated through the semiconductor manufacturing process tends to be contaminated and no electrical wiring is formed. A semiconductor package is formed by an assembly operation performed for the purpose of protecting the semiconductor chip from the external environment and shaping (shaping) the device for ease of use and protecting the operation function.
반도체 패키지는 여러 단계의 조립 공정을 거쳐 완성되는데, 예를 들어 웨이퍼의 절단 및 세정 공정, 다이(칩) 본드(Die Bond) 공정, 와이어 본드(Wire Bond) 공정, 몰드(Mold) 공정 기타 후처리 공정 및 검사 공정 등을 행하게 된다.The semiconductor package is completed through several stages of assembly process, for example, cutting and cleaning wafer, die bond process, wire bond process, mold process and other post-treatment. Process, inspection process, etc. are performed.
도 1 은 종래의 반도체 패키지의 다이 본드 구조를 나타낸 단면도로서, 여기에서 보면 리드 프레임(1)은 다이(칩)(2)를 탑재할 수 있는 패드부(1a)와, 다이(2)의 회로단자의 게이트 역할을 하는 리드부(1b)로 구분될 수 있다. 상기 리드 프레임(1)은 주로 구리 합금 소재로 이루어지고, 패드부(1a) 및 리드부(1b)의 소정 부분에는 각 각 은(Ag)으로 도금된 도금부(3a)(3b)를 갖추고 있다. 여기서, 은 도금부(3a)(3b)는 안정적인 본딩 작업을 확보하기 위한 것이다.1 is a cross-sectional view showing a die bond structure of a conventional semiconductor package. Here, the lead frame 1 includes a pad portion 1a on which a die (chip) 2 can be mounted, and a circuit of the die 2. It may be divided into a lead portion 1b serving as a gate of a terminal. The lead frame 1 is mainly made of a copper alloy material, and the pad portion 1a and the predetermined portion of the lead portion 1b are provided with plating portions 3a and 3b each plated with silver (Ag). . Here, the silver plating parts 3a and 3b are for ensuring a stable bonding operation.
다이(2)는 리드 프레임 패드부(1a)의 도금부(3a) 위에 열 경화성 수지재와 같은 접착제(4)를 사용하여 본딩된다. 이 후, 다이(2)와 리드부(1b)의 도금부(3b) 사이에는 전기적 접속을 위하여 와이어(5)가 본딩된다.The die 2 is bonded using an adhesive 4 such as a thermosetting resin material on the plating portion 3a of the lead frame pad portion 1a. Thereafter, a wire 5 is bonded between the die 2 and the plating portion 3b of the lead portion 1b for electrical connection.
그러나, 은(Ag) 도금 자체는 화학적으로 매우 안정적이고 내산화성이 있으므로 화학적 상호 작용력은 다른 물질과 비교하면 현저하게 낮지만 상대적으로 접착력이 떨어지는 결점을 내포하고 있다.However, silver (Ag) plating itself is chemically very stable and resistant to oxidation, so the chemical interaction force is significantly lower than that of other materials, but has a disadvantage of relatively poor adhesion.
더욱이, 은(Ag) 도금된 리드 프레임(1)과 몰딩 포장재인 EMC(Epoxy Mold Compound)(도시 생략) 사이나, 특히 패드부(1a)의 은 도금부(3a)와 접착제(4) 사이의 접착력 약화로 인하여 증기압시험(PCT; Pressure Cooker Test) 및 열 충격시험(T/S;Thermal Shock) 등의 가혹 신뢰성 조건에서 접착층에 계면박리(Dilamination) 현상이 생기면서 다이(칩)(2) 및 와이어(5)에 스트레스(Stress)가 발생하여 니트라이드(Nitride; Si3N4), 메탈(Metal), 와이어(5) 등에 미세한 균열을 유발하게 되면 패키지 제품 전체의 치명적인 불량을 일으킬 수 있다.Furthermore, between the silver (Ag) plated lead frame 1 and an epoxy mold compound (EMC) (not shown) which is a molding packaging material, or in particular, between the silver plated portion 3a of the pad portion 1a and the adhesive 4. Due to the weakening of the adhesive force, the die (chip) 2 and the dilamination phenomenon occur in the adhesive layer under severe reliability conditions such as a pressure cooker test (PCT) and a thermal shock (T / S). If stress is generated in the wire 5 to cause fine cracks such as nitride (Si 3 N 4 ), metal, metal, wire 5, or the like, a fatal defect of the entire packaged product may be caused.
따라서, 본 발명은 상술한 문제점을 해소하기 위하여 창작된 것으로서, 본 발명의 목적은 리드 프레임과 다이나 몰딩 포장재(EMC) 사이의 접착력을 강화시켜 고 신뢰성을 확보함과 동시에 고가의 도금 소재의 첨가량을 줄임으로써 조립 원가를 절감시킬 수 있도록 하는 반도체 패키지의 다이 본드 구조 및 공정 방법을 제공하는 데 있다.Therefore, the present invention was created to solve the above-mentioned problems, and an object of the present invention is to increase the adhesion between the lead frame and the dynamo-molding packaging material (EMC) to secure high reliability and at the same time increase the amount of expensive plating material added. The present invention provides a die bond structure and a process method of a semiconductor package that can reduce assembly costs by reducing the assembly cost.
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 패키지의 다이 본드 구조는, 리드 프레임의 패드부에 다이를 탑재하여 결합시키는 반도체 패키지의 다이 본드 구조에 있어서, 상기 리드 프레임의 패드부 위에는 은(Ag) 도금이 되지 않은 상태에서 접착제에 의해서만 다이를 직접 결합시키는 것을 특징으로 한다.A die bond structure of a semiconductor package according to the present invention for achieving the above object is a die bond structure of a semiconductor package in which a die is mounted and bonded to a pad portion of a lead frame, wherein a silver (Ag) is formed on the pad portion of the lead frame. It is characterized in that the die is directly bonded only by the adhesive in the non-plating state.
한편, 본 발명에 따른 반도체 패키지의 다이 본드 공정 방법은, 리드 프레임의 리드부에만 은(Ag) 도금을 시킬 수 있는 노광 홀을 가진 마스크를 제작하여 도금하는 단계와, 밀폐실 내에 밀봉된 열전판 위에 상기 리드 프레임을 로딩시켜 가스 공급관을 통하여 리드 프레임의 세정 및 산화 방지를 위하여 질소(N2) 및 수소(H2)의 혼합 가스를 공급하는 단계와, 리드 프레임의 도금되지 않은 패드부 위에 접착제가 도포되어 열전판의 가열에 따라 상기 접착제만으로 다이를 접착시키는 단계를 포함하는 것을 특징으로 한다.On the other hand, the die bond process method of the semiconductor package according to the present invention comprises the steps of manufacturing and plating a mask having an exposure hole capable of plating silver (Ag) only in the lead portion of the lead frame, and a thermoelectric plate sealed in a sealed chamber Loading the lead frame thereon to supply a mixed gas of nitrogen (N 2 ) and hydrogen (H 2 ) to clean and prevent oxidation of the lead frame through a gas supply pipe, and an adhesive on the unplated pad portion of the lead frame. It is characterized in that it comprises the step of adhering the die with only the adhesive in accordance with the heating of the thermoelectric plate.
도 1 은 종래의 반도체 패키지의 다이 본드 구조를 나타낸 단면도.1 is a cross-sectional view showing a die bond structure of a conventional semiconductor package.
도 2 는 본 발명에 따른 반도체 패키지의 다이 본드 구조를 나타낸 단면도.2 is a cross-sectional view showing a die bond structure of a semiconductor package according to the present invention.
도 3a ∼ 도 3d 는 본 발명에 따른 반도체 패키지의 다이 본드 공정 과정을 개략적으로 나타낸 단면도.3A to 3D are cross-sectional views schematically illustrating a die bond process of a semiconductor package according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 리드 프레임, 12 : 패드부,10: lead frame, 12: pad portion,
14 : 리드부, 20 : 다이,14: lead portion, 20: die,
30 : 도금부, 40 : 접착제,30: plating portion, 40: adhesive,
60 : 마스크, 62 : 노광 홀,60 mask, 62 exposure hole,
70 : 열전판, 80 : 밀폐실,70: thermoelectric plate, 80: airtight chamber,
90 : 가스 공급관, G : 가스.90: gas supply pipe, G: gas.
이하, 본 발명의 바람직한 실시예를 첨부된 도면에 의하여 더욱 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.
도 2 는 본 발명에 따른 반도체 패키지의 다이 본드 구조를 나타낸 단면도이다.2 is a cross-sectional view illustrating a die bond structure of a semiconductor package according to the present invention.
상기 도면에서, 부호 10 은 주로 구리 합금 소재로 이루어진 리드 프레임을 나타낸 것으로서, 이는 다이(칩)(20)를 탑재할 수 있는 패드부(12)와, 다이(20)의 회로단자의 게이트 역할을 하는 리드부(14)로 구분될 수 있다.In the figure, reference numeral 10 denotes a lead frame mainly made of a copper alloy material, which serves as a pad portion 12 on which a die (chip) 20 can be mounted and a gate of a circuit terminal of the die 20. The lead portion 14 can be divided into.
특히 본 실시예의 리드 프레임(10)은 그 리드부(14)에만 은(Ag)으로 도금된 도금부(30)를 갖추고 있고, 패드부(12)에는 도금부가 형성되어 있지 않다.In particular, the lead frame 10 of the present embodiment includes the plating portion 30 plated with silver (Ag) only in the lead portion 14, and the plating portion is not formed in the pad portion 12.
이러한 리드 프레임(10)의 패드부(12) 위에 다이(칩)(20)가 접착제(40)만으로 부착 결합된다. 그리고, 다이(20)의 회로 단자(도시 생략)와 리드부(14)의 도금부(30) 사이에 와이어(50)가 전기적 접속을 위하여 결합된다.The die (chip) 20 is attached to the pad portion 12 of the lead frame 10 only by the adhesive 40. A wire 50 is coupled between the circuit terminal (not shown) of the die 20 and the plating portion 30 of the lead portion 14 for electrical connection.
이와 같은 본 실시예에 따른 반도체 패키지의 다이 본드 공정 과정을 도 3a ∼ 도 3d 를 참조하여 살펴보면 다음과 같다.The die bonding process of the semiconductor package according to the present exemplary embodiment will be described with reference to FIGS. 3A to 3D.
도 3a 에서, 리드 프레임(10)의 소재에 은(Ag) 도금을 하기 위한 마스크(Mask)(60)를 제작할 때 리드부(14)에만 도금되도록 노광 홀(62)을 형성한다. 이러한 리드 프레임(10)의 도금 공정과 기계적 가공 분야인 스탬핑(Stamping) 공정 등의 제조 공정을 거쳐 출하 한 후, 후술하는 다이 본드 공정을 위하여 로딩된다.In FIG. 3A, an exposure hole 62 is formed so as to be plated only on the lead 14 when a mask 60 for plating silver on the material of the lead frame 10 is manufactured. After the lead frame 10 is shipped through a manufacturing process such as a plating process and a stamping process, which is a mechanical processing field, it is loaded for a die bond process to be described later.
도 3b 에서, 리드부(14)에만 도금부(30)가 형성된 리드 프레임(10)은 밀폐 공간(S)을 이루는 밀폐실(80) 내에서 밀봉 상태의 열전판(70) 위에 로딩되어 외부 공기에 노출되지 않도록 한다. 이렇게 밀폐 상태로 두는 것은 도금되지 않은 부분이 산화되어 산화막이 생성되는 현상을 저지하기 위함이다.In FIG. 3B, the lead frame 10 having the plating portion 30 formed only in the lead portion 14 is loaded on the thermoelectric plate 70 in a sealed state in the sealed chamber 80 forming the sealed space S, thereby providing external air. Avoid exposure to The sealing state is to prevent the phenomenon that the unplated portion is oxidized to form an oxide film.
상기 열전판(70)에는 가스 유통공(72)이 형성되고, 여기에 질소(N2)와 수소(H2)의 혼합 가스인 포밍 가스(Forming Gas)(G)를 리드 프레임(10) 쪽으로 공급할 수 있도록 가스 공급관(90)이 연결된다. 여기서, 상기 가스(G)의 혼합 비율이 N2: H2= 7 : 1 이면 매우 바람직하다.A gas distribution hole 72 is formed in the thermoelectric plate 70, and forming gas G, which is a mixed gas of nitrogen (N 2 ) and hydrogen (H 2 ), is directed to the lead frame 10. The gas supply pipe 90 is connected to supply. Here, it is very preferable that the mixing ratio of the gas G is N 2 : H 2 = 7: 1.
이렇게 포밍 가스(G)를 밀폐실(80) 내부에 공급하여 리드 프레임(10)을 세정함과 동시에 산화를 예방하는 공정을 거치게 한다.The forming gas G is supplied into the sealed chamber 80 to clean the lead frame 10 and to prevent oxidation.
도 3c 에서, 리드 프레임(10)의 도금되지 않은 패드부(12) 위에 열 경화성 수지재인 접착제(40)를 도포한 후, 여기에 다이(칩)(20)를 접착시킨다. 이 때, 열전판(70)을 통하여 약 360℃ 정도의 온도로 열(H)을 가하게 되면 접착제(40)가 경화된다.In FIG. 3C, after the adhesive 40, which is a thermosetting resin material, is applied on the unplated pad portion 12 of the lead frame 10, the die (chip) 20 is adhered thereto. At this time, when heat (H) is applied at a temperature of about 360 ° C. through the thermoelectric plate 70, the adhesive 40 is cured.
이어서, 도 3d 에서와 같이, 리드 프레임(10)에 탑재된 다이(20)와 리드부(14) 상호 간에 전기적 접속을 위하여 금(Au)이나 알루미늄(Al) 소재로 된 와이어(50)가 은 도금부(30)에 결합되는 와이어 본드 공정을 행하게 된다.Subsequently, as shown in FIG. 3D, the wire 50 made of gold (Au) or aluminum (Al) is made of silver for electrical connection between the die 20 mounted on the lead frame 10 and the lead portion 14. The wire bonding process coupled to the plating part 30 is performed.
결국, 본 실시예의 다이 본드 공정을 중심으로 살펴본 바와 같이, 주로 구리 소재의 리드 프레임(10)은 바늘 모양의 편상 형태로 산화막이 형성되어 접착제(40)와 수소 결합을 통하여 접착 강도를 더욱 높이는 작용을 하게 된다.As a result, as described with reference to the die bond process of the present embodiment, the lead frame 10 mainly made of copper is formed with an oxide film in the form of needle-like shape to further increase the adhesive strength through hydrogen bonding with the adhesive 40. Will be
상술한 본 발명에 의하면, 리드 프레임에 은 도금을 하지 않고 소정의 공정 과정을 거쳐 다이(칩)를 접착제로 직결시킴으로써 결합력의 강화로 인한 고 신뢰성을 확보함은 물론, 고가의 도금재 사용을 감축시킴으로써 조립 원가를 더욱 절감시킬 수 있다.According to the present invention as described above, the die (chip) is directly connected to the lead frame through a predetermined process without applying silver plating to the lead frame to ensure high reliability due to the strengthening of the bonding force, as well as to reduce the use of expensive plating material By doing so, assembly costs can be further reduced.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980044926A KR20000027092A (en) | 1998-10-27 | 1998-10-27 | Die bond structure of semiconductor package and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980044926A KR20000027092A (en) | 1998-10-27 | 1998-10-27 | Die bond structure of semiconductor package and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| KR20000027092A true KR20000027092A (en) | 2000-05-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019980044926A KR20000027092A (en) | 1998-10-27 | 1998-10-27 | Die bond structure of semiconductor package and manufacturing method thereof |
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| Country | Link |
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| KR (1) | KR20000027092A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160076174A (en) | 2014-12-22 | 2016-06-30 | 주식회사 포스코 | Apparatus for sensing level of melted steel |
-
1998
- 1998-10-27 KR KR1019980044926A patent/KR20000027092A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160076174A (en) | 2014-12-22 | 2016-06-30 | 주식회사 포스코 | Apparatus for sensing level of melted steel |
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