KR20000026934A - Method and apparatus for marking chip size package - Google Patents

Method and apparatus for marking chip size package Download PDF

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Publication number
KR20000026934A
KR20000026934A KR1019980044691A KR19980044691A KR20000026934A KR 20000026934 A KR20000026934 A KR 20000026934A KR 1019980044691 A KR1019980044691 A KR 1019980044691A KR 19980044691 A KR19980044691 A KR 19980044691A KR 20000026934 A KR20000026934 A KR 20000026934A
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South Korea
Prior art keywords
marking
wafer
chip
size package
chip size
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KR1019980044691A
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Korean (ko)
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KR100274206B1 (en
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백정민
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한효용
주식회사 트라이맥스
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE: A method and an apparatus for marking a chip size package are provided to improve a marking speed and a marking accuracy by performing a direct marking on a wafer before cutting a wafer. CONSTITUTION: A method for marking a chip size package comprises the steps of: marking a name or a trademark of a company on a wafer(1) before cutting a wafer; cutting the wafer to be divided into each chips; adhering the divided chips to a plastic IC tape; and performing a beam lead bonding process and a capsulization process. An apparatus for marking a chip size package comprises an on-loading device(10), a guide rail(20), a pattern vis ion (22), a marking device(24), a transferring device(21), a marking vis ion (26), and an off-loading device(30).

Description

칩사이즈패키지의 마킹방법 및 장치Marking method and device for chip size package

본 발명은 칩사이즈패키지의 마킹방법 및 장치에 관한 것으로서, 보다 상세하게는 공정이 단순하며 불량률이 낮은 새로운 칩사이즈패키지의 마킹방법 및 장치에 관한 것이다.The present invention relates to a method and apparatus for marking a chip size package, and more particularly, to a method and apparatus for marking a new chip size package having a simple process and a low defect rate.

근래에는 반도체 칩이 점차 소형화되어 가고 있는데, 칩사이즈패키지(CSP)는 이러한 반도체 칩의 소형화경향에 따라 기존의 수지몰딩부없이 칩사이즈 그대로 패키지 된 것이다.In recent years, semiconductor chips are gradually miniaturized, and chip size packages (CSPs) are packaged as they are without the conventional resin molding part according to the miniaturization trend of the semiconductor chips.

이러한 CSP는 일반적으로 도 2에 도시된 바와 같은 공정으로 이루어진다.This CSP generally consists of a process as shown in FIG. 2.

먼저, 도 1에 도시된 바와 같은, 회로가 내장되며 패턴화된 웨이퍼(1)를 패턴에 따라 절단하여 개별의 칩(2)을 만든다. 그런 다음 도 2의 (A)와 같이 칩캐리어(3)에 P.I테이프(Plastic IC tape)(4)를 부착하고 (B)에 도시된 바와 같이 P.I테이프(4)에 각각의 칩(2)을 부착한 후, (C)와 같이 칩(2)과 P.I테이프(4)를 빔리드로 본딩한다. 그런 다음 각각의 칩(2)을 캡슐화하기 위하여 (D),(E),(F)에 도시된 바와 같이, P.I테이프(4)위에 커버필름(5)을 부착하여 용가제로 캡슐화하고 커버테이프(5)를 제거한다. 이와 같이 칩(2)의 캡슐화과정에서 P.I테이프(4)위에 커버필름(5)을 부착하는 것은 P.I테이프(4)에는 솔더볼(8)을 부착하기 위한 미세한 구멍들이 형성되어 있는데 칩(2)의 캡슐화과정에서 이 미세공을 통해 용가제가 방출되는 것을 방지하기 위한 것이다. 이와 같이 캡슐화과정이 끝나면 (G)에 도시된 바와 같이 칩패키지(7)를 회로기판에 부착하기 위한 솔더볼(8)을 P.I테이프(4)위에 붙이는데, 먼저 P.I테이프(4)위에 용제를 바른 다음에 솔더볼(8)을 부착한다. 그리고 (H)에 도시된 바와 같이, 레이저 등의 마킹수단(6)으로 각각의 칩(2)배면에 회사로고나 상표명 등을 마킹한 후, (I)와 같이 P.I테이프(4)를 잘라 개별의 칩패키지(7)를 완성한다.First, as shown in FIG. 1, a circuit-embedded and patterned wafer 1 is cut according to a pattern to make individual chips 2. Then, a PI tape (Plastic IC tape) 4 is attached to the chip carrier 3 as shown in FIG. 2A, and each chip 2 is attached to the PI tape 4 as shown in (B). After attaching, the chip 2 and the PI tape 4 are bonded with the beam lead as shown in (C). Then, as shown in (D), (E), and (F) to encapsulate each chip 2, the cover film 5 is attached on the PI tape 4, encapsulated with a solvent, and the cover tape ( 5) Remove. As described above, attaching the cover film 5 on the PI tape 4 in the encapsulation process of the chip 2 includes fine holes for attaching the solder balls 8 to the PI tape 4. This is to prevent the release of the solvent through the micropores in the encapsulation process. After the encapsulation process is completed, a solder ball 8 for attaching the chip package 7 to the circuit board is attached on the PI tape 4, as shown in (G). First, a solvent is applied on the PI tape 4 Next, the solder ball 8 is attached. And as shown in (H), after marking the company logo or brand name on the back of each chip (2) with a marking means (6), such as a laser, and cut the PI tape (4) as shown in (I) The chip package 7 is completed.

이와 같이 종래의 칩사이즈패키지(CSP) 공정에서는 마킹과정이 전체패키지 공정의 후반에서 이루어진다. 따라서 마킹전의 여러과정에서 칩의 위치가 변동되어 칩이 일정한 간격으로 배치되지 않으므로 마킹속도가 떨어질 뿐만 아니라 마킹위치의 정밀도가 떨어져서 마킹불량의 원인이 되었다.As described above, in the conventional chip size package (CSP) process, the marking process is performed later in the entire package process. Therefore, since the position of the chip is changed at various stages before the marking, the chip is not arranged at regular intervals, so that the marking speed is lowered and the precision of the marking position is lowered, which causes the marking defect.

본 발명은 전술한 바와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 웨이퍼를 개별의 칩으로 절단하기 전에 웨이퍼에 직접 마킹하므로 공정이 단순하고 불량률이 낮은 새로운 칩사이즈패키지의 마킹방법 및 장치를 제공하기 위한 것이다.The present invention has been made to solve the above problems, and an object of the present invention is to mark a new chip size package with a simple process and low defect rate since the marking is performed directly on the wafer before cutting the wafer into individual chips. It is to provide.

도 1은 일반적인 웨이퍼를 보인 사시도1 is a perspective view showing a typical wafer

도 2는 종래 칩사이즈패키지의 공정을 보인 개략도2 is a schematic view showing a process of a conventional chip size package

도 3은 본 발명에 따른 장치의 일실시예를 보인 개략도3 is a schematic view showing one embodiment of an apparatus according to the present invention;

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

1. 웨이퍼 2. 칩1. Wafer 2. Chip

3. 칩캐리어 4. P.I테이프3. Chip carrier 4. P.I tape

7. 칩패키지 10. 온로딩장치7. Chip Package 10. On-loading Device

12. 제1픽업기구 14. 공급매거진12. First Pickup Organization 14. Supply Magazine

20. 가이드레일 22. 패턴비젼20. Guide Rail 22. Pattern Vision

24. 마킹수단 26. 마킹비젼24. Marking means 26. Marking vision

30. 오프로딩장치 32. 제2픽업기구30. Off-loading device 32. Second pick-up mechanism

34. 배출매거진 40. 콘트롤부34. Emission magazine 40. Control unit

본 발명에 따르면, 칩사이즈패키지(CSP)공정에 있어서, 회로가 내장된 웨이퍼(1)를 개별의 칩(2)으로 절단하기 전에 웨이퍼(1)에 직접 회사명이나 상표 등을 마킹한 후, 웨이퍼(1)를 개별의 칩(2)으로 절단하여서 P.I테이프(4)에 부착하고 빔리드본딩과 캡슐화하는 등의 과정으로 칩(1)을 패키지하는 것을 특징으로 하는 칩사이즈패키지의 마킹방법이 제공된다.According to the present invention, in the chip size package (CSP) process, before cutting the wafer 1 with the circuit into the individual chip 2, the company name or trademark is directly marked on the wafer 1, The chip size package marking method is characterized by cutting the wafer 1 into individual chips 2, attaching them to the PI tape 4, and packaging the chips 1 by beam lead bonding and encapsulation. Is provided.

본 발명의 다른 특징에 따르면, 웨이퍼(1)가 순차적으로 공급되는 온로딩장치(10)와, 상기 온로딩장치(10)에 의해 웨이퍼(1)가 탑재되는 가이드레일(20)과, 상기 가이드레일(20)에 탑재된 웨이퍼(1)의 패턴을 인식하는 패턴비젼(22)과, 상기 패턴비젼(22)에 의해 인식된 자료에 의해 상기 웨이퍼(1)의 배면에 회사명이나 상표 등을 마킹하는 마킹수단(24)과, 상기 마킹수단(24)에 의해 마킹된 웨이퍼(1)를 가이드레일(20)상에서 이동시키는 이동수단(21)과, 상기 이동수단(21)에 의해 이동된 웨이퍼(1)의 마킹상태를 검사하는 마킹비젼(26)과, 상기 마킹비젼(26)에 의해 마킹상태가 검사된 웨이퍼(1)를 반출하는 오프로딩장치(30)를 포함하는 것을 특징으로 하는 칩사이즈패키지의 마킹장치가 제공된다.According to another feature of the invention, the on-loading device 10, the wafer 1 is sequentially supplied, the guide rail 20 on which the wafer 1 is mounted by the on-loading device 10, and the guide The pattern vision 22 which recognizes the pattern of the wafer 1 mounted on the rail 20, and the company name, a trademark, etc. are put on the back surface of the wafer 1 by the data recognized by the said pattern vision 22. Marking means 24 for marking, a moving means 21 for moving the wafer 1 marked by the marking means 24 on the guide rail 20, and a wafer moved by the moving means 21. And a marking vision 26 for inspecting the marking state of (1) and an offloading device 30 for carrying out the wafer 1 whose marking state is inspected by the marking vision 26. A marking device of a size package is provided.

이하, 본 발명의 바람직한 실시예를 첨부한 도면에 의거하여 설명하면 다음과 같다. 도 3은 본 발명에 따른 마킹장치를 도시한 개략도이다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. 3 is a schematic view showing a marking apparatus according to the present invention.

본 발명에 따르면, 회로가 내장된 웨이퍼(1)를 개별의 칩(2)으로 절단하기 전에 웨이퍼(1)에 직접 회사명이나 상표 등을 마킹하는데, 이러한 과정은 상기와 같은 장치에서 이루어진다.According to the present invention, the company name or trademark is marked directly on the wafer 1 before cutting the wafer 1 having the circuit into the individual chip 2, which is performed in the above apparatus.

상기 온로딩장치(10)는 바람직하게는 웨이퍼(1)가 적층되는 공급매거진(14)과 이 공급매거진(14)에 적층되는 웨이퍼(1)를 순차적으로 픽업하여 상기 가이드레일(20)에 탑재시키는 제1픽업기구(12)로 이루어진다. 따라서 제1픽업기구(12)는 공급매거진(14)에 적층된 웨이퍼(1)를 픽업하여 상기 가이드레일(20)에 탑재하며, 공급매거진(14)에 적층된 웨이퍼(1)가 제1픽업수단(12)에 의해 순차적으로 가이드레일(20)에 탑재됨에 따라 공급매거진(14)의 베이스(18)는 실린더(16)에 의해 한 피치씩 상승된다.The on-loading device 10 preferably picks up the supply magazine 14 on which the wafer 1 is stacked and the wafer 1 stacked on the supply magazine 14 sequentially and mounts them on the guide rail 20. It consists of a first pick-up mechanism (12). Accordingly, the first pickup mechanism 12 picks up the wafer 1 stacked on the supply magazine 14 and mounts the wafer 1 on the guide rail 20, and the wafer 1 stacked on the supply magazine 14 is first picked up. As it is sequentially mounted on the guide rail 20 by the means 12, the base 18 of the feed magazine 14 is raised by the cylinder 16 by one pitch.

상기 가이드레일(20)의 반입부는 상기 공급매거진(14)에 근접하고 타측은 상기 오프로딩장치(30)에 근접하도록 배치되며, 상기 제1픽업수단(12)에 의해 픽업된 웨이퍼(1)는 가이드레일(20)의 반입부에 탑재된다. 한편, 가이드레일(20)의 반입부주변에는 웨이퍼(1)에 새겨진 패턴을 인식하는 패턴비젼(22)이 설치되어 있으며, 이 패턴비젼(22)에 의해 인식된 자료는 콘트롤부(40)에서 처리되어 그 제어신호는 마킹수단(24)으로 전해진다.The carrying part of the guide rail 20 is disposed to be close to the supply magazine 14 and the other side is to be close to the offloading device 30. The wafer 1 picked up by the first pickup means 12 is It is mounted to the loading part of the guide rail 20. On the other hand, a pattern vision 22 for recognizing a pattern engraved on the wafer 1 is installed around the carry-in portion of the guide rail 20, and the data recognized by the pattern vision 22 is controlled by the controller 40. The control signal is transmitted to the marking means 24.

상기 마킹수단(24)은 레이저헤드로 이루어진 것으로서, 상기 패턴비젼(28)의 대향측에 설치되어 콘트롤부(40)를 통해 입력된 제어신호에 의해 웨이퍼(1)의 배면에 회사명이나 상표 등을 마킹한다. 즉, 웨이퍼(1)가 패턴면의 아래쪽으로 향하도록 가이드레일(20)에 탑재된 경우에는, 상기 패턴비젼(22)은 반입부의 하부에 설치되고 마킹수단(24)은 반입부의 상부에 설치된다. 이와 같이 마킹수단(24)에 의래 마킹이 끝나면 웨이퍼(1)는 워킹빔 등과 같은 이동수단(21)에 의해 가이드레일(20)상에서 오프로딩장치(30)쪽으로 한 스텝 이동하게 된다.The marking means 24 is formed of a laser head, which is installed on the opposite side of the pattern vision 28 and is placed on the back of the wafer 1 by a control signal input through the control unit 40. Mark That is, when the wafer 1 is mounted on the guide rail 20 so as to face downward of the pattern surface, the pattern vision 22 is installed below the carrying part and the marking means 24 is installed above the carrying part. . When the marking means 24 is finished, the wafer 1 is moved one step from the guide rail 20 toward the offloading device 30 by the moving means 21 such as a walking beam.

이와 같이 마킹이 끝나 이동된 웨이퍼(1)는 가이드레일(20)의 주변에 설치된 마킹비젼(26)에 의해 마킹의 불량여부가 검사되며, 상기 마킹비젼(26)에 의해 마킹정도가 양호하다고 판정이 된 웨이퍼(1)는 오프로딩장치(30)로 반출된다. 상기 오프로딩장치(30)는 바람직하게는 가이드레일(20)에서 마킹검사가 끝난 웨이퍼(1)를 픽업하는 제2픽업기구(32)와 제2픽업기구(32)에 의해 픽업된 웨이퍼(1)가 적재되는 배출매거진(34)으로 이루어진다.Thus, the marking 1 is moved and the wafer 1 is inspected whether or not the marking is defective by the marking vision 26 installed around the guide rail 20, and the marking vision 26 determines that the marking accuracy is good. This wafer 1 is carried out to the offloading apparatus 30. The offloading device 30 preferably includes a second pick-up mechanism 32 and a second pick-up mechanism 32 for picking up the wafer 1 after the marking inspection from the guide rail 20. ) Is composed of a discharge magazine 34 is loaded.

한편, 마킹비젼(26)에 의해 마킹불량판정이 난 웨이퍼(1)는 제2픽업기구(32)나 기타의 픽업수단에 의해 외부로 반출된다. 그리고 상기 배출매거진(34)은 공급매거진(14)과는 반대로 웨이퍼(1)가 적재됨에 따라 배출매거진(34)의 베이스(38)가 실린더(36)에 의해 한 피치씩 하강된다.On the other hand, the wafer 1 which has been determined to be poorly marked by the marking vision 26 is carried out to the outside by the second pickup mechanism 32 or other pickup means. In addition, as the discharge magazine 34 is loaded with the wafer 1 as opposed to the supply magazine 14, the base 38 of the discharge magazine 34 is lowered by one pitch by the cylinder 36.

이상과 같이하여 웨이퍼(1)자체에 마킹이 이루어지면 웨이퍼(1)를 잘라 개별의 칩(2)을 형성하고 전술한 바와 같이, 칩(2)을 칩캐리어(3)에 부착된 P.I테이프(4)에 부착하여 칩(2)과 P.I테이프(4)를 빔리드 본딩하고 캡슐화한 후, 솔더볼을 부착하여 P.I테이프(4)를 자르는 과정으로 칩(2)을 패키지한다.When the marking is made on the wafer 1 itself as described above, the wafer 1 is cut to form individual chips 2, and as described above, the PI tape having the chip 2 attached to the chip carrier 3 ( 4) The chip 2 and the PI tape 4 are beam-lead bonded and encapsulated, and then the solder 2 is attached to package the chip 2 by cutting the PI tape 4.

이러한 본 발명에 의하면, 웨이퍼를 자르기 전에 마킹작업이 이루어지므로 마킹정밀도와 마킹속도가 향상되고 마킹방향에 따른 칩의 방향을 손쉽게 구별할 수 있어 칩패키지작업이 용이해진다.According to the present invention, since the marking operation is performed before cutting the wafer, the marking accuracy and the marking speed are improved, and the chip direction can be easily distinguished according to the marking direction, thereby facilitating the chip package operation.

이상에서와 같이 본 발명에 의하면, 회로가 내장된 웨이퍼를 자르기 전에 와이퍼에 직접 마킹하게 되므로 마킹속도와 마킹정밀도 등이 향상되며, 따라서 불량률을 낮출 수 있어서 원가절감을 꾀할 수 있다. 또한, 마킹공정이 이루어진 후에 웨이퍼를 개별의 칩으로 절단하고 패키지작업이 이루어지므로 마킹방향에 따른 칩의 방향을 손쉽게 구별할 수 있어서 칩패키지작업이 용이해진다.As described above, according to the present invention, since the marking is directly performed on the wiper before cutting the wafer in which the circuit is embedded, the marking speed, the marking accuracy, and the like are improved, so that the defect rate can be lowered, thereby reducing the cost. In addition, since the wafer is cut into individual chips after the marking process and packaged, the chip direction can be easily distinguished according to the marking direction, thereby facilitating chip packaging.

Claims (2)

칩사이즈패키지(CSP)공정에 있어서, 회로가 내장된 웨이퍼(1)를 개별의 칩(2)으로 절단하기 전에 웨이퍼(1)에 직접 회사명이나 상표 등을 마킹한 후, 웨이퍼(1)를 개별의 칩(2)으로 절단하여서 P.I테이프(4)에 부착하고 빔리드본딩과 캡슐화하는 등의 과정으로 칩(1)을 패키지하는 것을 특징으로 하는 칩사이즈패키지의 마킹방법In the chip size package (CSP) process, before cutting the wafer 1 having a circuit therein into an individual chip 2, the company name or trademark is directly marked on the wafer 1, and then the wafer 1 is Marking method of chip size package, characterized in that the chip (1) is packaged by cutting into individual chips (2), attaching to PI tape (4), beam lead bonding and encapsulation. 웨이퍼(1)가 순차적으로 공급되는 온로딩장치(10)와, 상기 온로딩장치(10)에 의해 웨이퍼(1)가 탑재되는 가이드레일(20)과, 상기 가이드레일(20)에 탑재된 웨이퍼(1)의 패턴을 인식하는 패턴비젼(22)과, 상기 패턴비젼(22)에 의해 인식된 자료에 의해 상기 웨이퍼(1)의 배면에 회사명이나 상표 등을 마킹하는 마킹수단(24)과, 상기 마킹수단(24)에 의해 마킹된 웨이퍼(1)를 가이드레일(20)상에서 이동시키는 이동수단(21)과, 상기 이동수단(21)에 의해 이동된 웨이퍼(1)의 마킹상태를 검사하는 마킹비젼(26)과, 상기 마킹비젼(26)에 의해 마킹상태가 검사된 웨이퍼(1)를 반출하는 오프로딩장치(30)를 포함하는 것을 특징으로 하는 것을 칩사이즈패키지의 마킹장치On-loading apparatus 10 to which the wafer 1 is sequentially supplied, a guide rail 20 on which the wafer 1 is mounted by the on-loading apparatus 10, and a wafer mounted on the guide rail 20. A pattern vision (22) for recognizing the pattern of (1), marking means (24) for marking a company name or a trademark on the back of the wafer (1) by the data recognized by the pattern vision (22); Inspecting a marking state of the moving means 21 for moving the wafer 1 marked by the marking means 24 on the guide rail 20 and the wafer 1 moved by the moving means 21. Marking vision 26 and an off-loading device 30 for carrying out the wafer 1, the marking state is checked by the marking vision 26, characterized in that it comprises a chip size package
KR1019980044691A 1998-10-21 1998-10-21 Marking method and marking system of chip size package KR100274206B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040011923A (en) * 2002-07-31 2004-02-11 삼성전자주식회사 Table for wafer labeling
KR100461024B1 (en) * 2002-04-15 2004-12-13 주식회사 이오테크닉스 Chip-scale marker and marking method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379084B1 (en) * 1998-08-31 2003-07-07 앰코 테크놀로지 코리아 주식회사 Semiconductor Package Manufacturing Method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100461024B1 (en) * 2002-04-15 2004-12-13 주식회사 이오테크닉스 Chip-scale marker and marking method
KR20040011923A (en) * 2002-07-31 2004-02-11 삼성전자주식회사 Table for wafer labeling

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