KR20000004252A - Method for forming a transistor of semiconductor devices - Google Patents
Method for forming a transistor of semiconductor devices Download PDFInfo
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- KR20000004252A KR20000004252A KR1019980025682A KR19980025682A KR20000004252A KR 20000004252 A KR20000004252 A KR 20000004252A KR 1019980025682 A KR1019980025682 A KR 1019980025682A KR 19980025682 A KR19980025682 A KR 19980025682A KR 20000004252 A KR20000004252 A KR 20000004252A
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- silicon epitaxial
- type silicon
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- 238000000034 method Methods 0.000 title claims abstract description 68
- 239000004065 semiconductor Substances 0.000 title claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 50
- 239000010703 silicon Substances 0.000 claims abstract description 50
- 125000006850 spacer group Chemical group 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 30
- 238000011065 in-situ storage Methods 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- -1 phosphorus ions Chemical class 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 36
- 239000011229 interlayer Substances 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000004913 activation Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 230000005465 channeling Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 접합부 영역상에 단결정 실리콘막을 성장시켜 엘리베이티드 소오스/드레인 영역을 형성하므로서 소자의 신뢰성을 향상시킬 수 있는 트랜지스터 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a transistor capable of improving the reliability of a device by growing a single crystal silicon film on a junction region to form an elevated source / drain region.
일반적으로, 반도체 소자가 고집적화 되어감에 따라 트랜지스터는 얕은 깊이를 갖는 소오스/드레인 영역의 형성이 요구되고 있다. 얕은 소오스/드레인 영역(shallow source/drain)를 형성하기 위한 방법으로, 저에너지의 이온주입에 의한 방법과 이를 응용한 이중 이온주입(double implantation) 방법, 선 비정질화에 의한 채널링 효과(channeling effect) 억제 방법 등이 제안되고 있다. 이러한 방법들은 0.1㎛ 이하 급의 반도체 소자의 얕은 접합 형성을 위해서 주입된 이온에 의한 결함 형성에 따른 물리적, 화학적 특성 규명이 아직 미흡한 실정이다. 또한 접합부 콘택을 위한 콘택홀 형성시 식각 손상으로 인한 숏트 채널 효과(short channel effect)로 인하여 소자의 신뢰성이 저하되는 문제가 있다.In general, as semiconductor devices become highly integrated, transistors are required to form source / drain regions having a shallow depth. A method for forming a shallow source / drain, using a method of low energy ion implantation, a double implantation method using the same, and suppressing channeling effects by line amorphous Methods and the like have been proposed. These methods still lack the physical and chemical characterization of defect formation by implanted ions for the formation of shallow junctions of semiconductor devices of 0.1 μm or less. In addition, there is a problem that the reliability of the device is deteriorated due to a short channel effect due to etching damage when forming a contact hole for contact contact.
이와 같은 종래의 반도체 소자의 트랜지스터 형성 방법은 다음과 같다. 웰이 형성된 실리콘 기판에 필드 산화막을 형성하여 액티브 영역을 형성한다. 상기 액티브 영역상에 게이트 산화막 및 게이트 전극을 형성한다. 불순물 이온주입 공정을 통해 소오스/드레인 접합영역을 형성한 후, 상기 전체 구조상에 층간 절연막을 형성한다. 이후, 콘택 형성 공정 및 금속배선 형성 공정 등을 실시하여 트랜지스터를 완성한다.The transistor formation method of the conventional semiconductor element is as follows. A field oxide film is formed on the well formed silicon substrate to form an active region. A gate oxide film and a gate electrode are formed on the active region. After the source / drain junction region is formed through an impurity ion implantation process, an interlayer insulating layer is formed on the entire structure. Subsequently, a transistor is formed by performing a contact forming process, a metal wiring forming process, or the like.
상기와 같이 형성된 종래의 트랜지스터 등은 소자의 집적도가 증가함에 따라 디자인 룰이 점차 축소되고, 따라서 트랜지스터의 채널 길이도 감소하게 된다. 트랜지스터의 채널 길이가 감소하게 되면, 문턱 전압(Threshold) 특성에서 숏 채널 효과(Short Channel Effect)가 크게 나타나게 되고, 접합의 깊이가 보다 짧아지게 되어 누설 전류가 증가하게 된다.In the conventional transistor or the like formed as described above, the design rule is gradually reduced as the degree of integration of the device is increased, and thus, the channel length of the transistor is also reduced. When the channel length of the transistor is reduced, the short channel effect is large in the threshold voltage characteristic, and the depth of the junction is shortened, thereby increasing leakage current.
따라서, 본 발명은 트랜지스터의 접합부 형성시에 저농도 불순물 영역의 기판상에 다결정 실리콘 에피택셜막을 성장시킨 후, 인-시투 공정 또는 단결정 실리콘막 성장후의 이온 주입 공정 등을 통해 엘리베이티드 접합부 영역을 형성하므로서, 충분한 채널 길이 및 접합 깊이를 획득할 수 있는 반도체 소자의 트랜지스터 형성 방법을 제공하는데 그 목적이 있다.Therefore, the present invention forms an elevated junction region by growing a polycrystalline silicon epitaxial film on a substrate of a low concentration impurity region at the time of forming a junction of a transistor, and then performing an in-situ process or an ion implantation process after growth of a single crystal silicon film. It is an object of the present invention to provide a method for forming a transistor of a semiconductor device capable of obtaining a sufficient channel length and junction depth.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 트랜지터 형성 방법의 한 예는 NMOS 지역 및 PMOS 지역의 액티브 영역에 게이트 산화막, 게이트 및 저농도 불순물 영역이 각각 형성되는 기판이 제공되는 단계; NMOS 지역의 상기 게이트 측벽에만 스페이서를 형성한 후, 상기 NMOS 지역의 상기 게이트 양측의 기판상에 N-타입 실리콘 에피택셜막을 형성하는 단계; PMOS 지역의 상기 게이트 측벽에 스페이서를 형성한 후, PMOS 지역의 상기 게이트 양측의 기판상에 P-타입 실리콘 에피택셜막을 형성하는 단계; 및 열처리 공정을 통해 엘리베이티드 소오스/드레인 영역을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.One example of a method for forming a transistor of a semiconductor device according to the present invention for achieving the above object is providing a substrate in which a gate oxide film, a gate and a low concentration impurity region are respectively formed in an active region of an NMOS region and a PMOS region; Forming a spacer only on the gate sidewall of the NMOS region, and then forming an N-type silicon epitaxial film on the substrate on both sides of the gate of the NMOS region; Forming a spacer on the gate sidewall of the PMOS region, and then forming a P-type silicon epitaxial film on the substrate on either side of the gate of the PMOS region; And forming an elevated source / drain region through a heat treatment process.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 트랜지터 형성 방법의 다른 예는 NMOS 지역 및 PMOS 지역의 액티브 영역에 게이트 산화막, 게이트 및 저농도 불순물 영역이 각각 형성되는 기판이 제공되는 단계; NMOS 지역의 상기 게이트 측벽에만 스페이서를 형성한 후, NMOS 지역 및 PMOS 지역의 상기 전체 구조상에 N-타입 실리콘 에피택셜막을 형성하는 단계; PMOS 지역의 상기 N-타입 실리콘 에피택셜막을 제거하고, PMOS 지역의 상기 게이트 측벽에 스페이서를 형성한 후, NMOS 지역 및 PMOS 지역의 상기 전체 구조상에 P-타입 실리콘 에피택셜막을 형성하는 단계; NMOS 지역의 상기 P-타입 실리콘 에피택셜막을 제거하고, NMOS 지역의 상기 N-타입 실리콘 에피택셜막을 노출시킨 후, 식각 공정을 통해 상기 게이트 상부가 개방된 N-타입 및 P-타입 실리콘 에피택셜막을 형성하는 단계; 및 열처리 공정을 통해 엘리베이티드 소오스/드레인 영역을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.Another example of a method for forming a transistor of a semiconductor device according to the present invention for achieving the above object is providing a substrate in which a gate oxide film, a gate and a low concentration impurity region are respectively formed in an active region of an NMOS region and a PMOS region; Forming a spacer only on the gate sidewalls of the NMOS region, and then forming an N-type silicon epitaxial film on the entire structure of the NMOS region and the PMOS region; Removing the N-type silicon epitaxial film of the PMOS region, forming a spacer on the gate sidewall of the PMOS region, and then forming a P-type silicon epitaxial film on the entire structure of the NMOS region and the PMOS region; After removing the P-type silicon epitaxial layer in the NMOS region, exposing the N-type silicon epitaxial layer in the NMOS region, an N-type and P-type silicon epitaxial layer in which the gate top is opened through an etching process is removed. Forming; And forming an elevated source / drain region through a heat treatment process.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 트랜지스터 형성 방법의 한 예를 설명하기 위한 단면도.1 (a) to 1 (d) are cross-sectional views for explaining one example of a method for forming a transistor of a semiconductor device according to the present invention.
도 2(a) 내지 도 2(e)는 본 발명에 따른 반도체 소자의 트랜지스터 형성 방법의 다른 예를 설명하기 위한 단면도.2A to 2E are cross-sectional views for explaining another example of the method for forming a transistor of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
10 및 110 : 실리콘 기판 20 및 120 : 필드 산화막10 and 110: silicon substrate 20 and 120: field oxide film
22 및 122 : 게이트 산화막 24 및 124 : 게이트22 and 122: gate oxide films 24 and 124: gate
26 및 126 : 저농도 불순물 영역 28 및 128 : 스페이서용 산화막26 and 126: low concentration impurity regions 28 and 128: oxide films for spacers
29, 30, 129 및 130 : 스페이서 35 및 135 : 층간 절연막29, 30, 129, and 130: spacers 35 and 135: interlayer insulating film
32, 132 및 133 : N-타입 실리콘 에피택셜막32, 132 and 133: N-type silicon epitaxial film
37, 137 및 138 : P-타입 실리콘 에피택셜막37, 137 and 138: P-type silicon epitaxial film
40, 50, 140 및 150 : 마스크층40, 50, 140, and 150: mask layer
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
(제 1 실시예)(First embodiment)
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 트랜지스터 형성 방법의 한 예를 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating an example of a method of forming a transistor of a semiconductor device according to the present invention.
도 1(a)를 참조하면, NMOS 지역 및 PMOS 지역이 형성되는 실리콘 기판(10)에 필드 산화막(20)을 형성하여 액티브 영역을 정의한다. 상기 액티브 영역상에 게이트 산화막 및 게이트용 폴리실리콘을 증착한 후, 마스크를 이용한 식각 공정을 통해 게이트용 폴리실리콘 및 게이트 산화막을 순차적으로 식각하여 게이트 산화막(22) 및 게이트(24)를 각각 형성한다. 이후, 라이틀리 도프트 드레인(Lighty Doped Drain; LDD) 이온주입 공정을 실시하여 저농도 불순물 영역(26)을 형성한 후, 상기 전체 구조상에 스페이서용 산화막(28)을 증착한다. PMOS 지역의 스페이서용 산화막(28)상에 포토레지스터를 이용한 제 1 마스크층(40)을 형성한다.Referring to FIG. 1A, a field oxide film 20 is formed on a silicon substrate 10 in which an NMOS region and a PMOS region are formed to define an active region. After the gate oxide film and the gate polysilicon are deposited on the active region, the gate polysilicon and the gate oxide film are sequentially etched through an etching process using a mask to form the gate oxide film 22 and the gate 24, respectively. . Thereafter, a lightly doped drain (LDD) ion implantation process is performed to form a low concentration impurity region 26, and then an oxide layer 28 for spacers is deposited on the entire structure. A first mask layer 40 using a photoresist is formed on the spacer oxide film 28 in the PMOS region.
상기에서, 게이트용 폴리실리콘은 텅스텐 실리사이드를 증착할 수 있다.In the above, the gate polysilicon may deposit tungsten silicide.
도 1(b)를 참조하면, 상기 제 1 마스크층(40)을 이용한 식각 공정을 통해 NMOS 지역의 스페이서용 산화막(28)을 식각하고, 이로 인하여 게이트(24) 측벽에 스페이서(29)가 형성된 후, 제 1 마스크(40)를 제거한다. 이후, 세정 공정을 실시한 후, NMOS 지역의 저농도 불순물 영역(26)상에 N-타입 실리콘 에피택셜막(32)을 형성한다.Referring to FIG. 1B, an oxide layer 28 for spacers in an NMOS region is etched through an etching process using the first mask layer 40, and thus spacers 29 are formed on sidewalls of the gate 24. After that, the first mask 40 is removed. Thereafter, after the cleaning process, an N-type silicon epitaxial film 32 is formed on the low concentration impurity region 26 in the NMOS region.
상기에서, N-타입 실리콘 에피택셜막(32)은 50 내지 2000Å의 두께로 형성되며, 단결정 실리콘막 성장시에 PH3가스를 주입하는 인-시투 도핑에 의해 형성되거나, 단결정 실리콘막 성장 후 N-타입 이온주입이 실시되어 형성된다. 인-시투 도핑 공정은 NMOS 지역의 단결정 실리콘막 성장시, 전기적 저항 감소를 위해 PH3가스가 증착 챔버에 주입되고 이때, 인 이온이 도핑되도록 실시된다. 또한, NMOS 지역의 단결정 실리콘막 성장후, 전기적 저항 감소를 위한 N-타입 도펀트는 비소 및 인 등의 5 족 이온이 사용된다. 도핑 레벨은 1.0×1018내지 1021atoms/㎤이다.In the above, the N-type silicon epitaxial film 32 is formed to have a thickness of 50 to 2000 GPa, and is formed by in-situ doping which injects PH 3 gas during growth of the single crystal silicon film, or N after growth of the single crystal silicon film. It is formed by -type ion implantation. The in-situ doping process is performed so that, upon growth of a single crystal silicon film in an NMOS region, a PH 3 gas is injected into the deposition chamber to reduce the electrical resistance, at which time phosphorus ions are doped. In addition, after the growth of the single crystal silicon film in the NMOS region, Group 5 ions such as arsenic and phosphorus are used as the N-type dopant for reducing the electrical resistance. The doping level is 1.0 × 10 18 to 10 21 atoms / cm 3.
도 1(c)를 참조하면, 상기 N-타입 실리콘 에피택셜막(32)이 형성된 전체 구조상에 층간 절연막(35)를 형성한 후, NMOS 지역의 층간 절연막(35)상에 포토레지스터를 이용한 제 2 마스크층(50)을 형성한다.Referring to FIG. 1C, after the interlayer insulating layer 35 is formed on the entire structure of the N-type silicon epitaxial layer 32, a photoresist is used on the interlayer insulating layer 35 in the NMOS region. 2 mask layer 50 is formed.
상기에서, 층간 절연막(35; IOP: Inter Poly Oxide)은 BPSG 또는 열산화막(Thermal Oxide)을 사용한다.In the above, the interlayer insulating layer 35 (Inter Poly Oxide (IOP)) uses BPSG or Thermal Oxide.
도 1(d)를 참조하면, 상기 제 2 마스크층(40)을 이용한 식각 공정을 통해 PMOS 지역의 층간 절연막(35) 및 스페이서용 산화막(28)을 순차적으로 식각하고, 이로 인하여 게이트(24) 측벽에 스페이서(30)가 형성된 후, 제 2 마스크(50)를 제거한다. 이후, 세정 공정을 실시한 후, PMOS 지역의 저농도 불순물 영역(26)상에 P-타입 실리콘 에피택셜막(37)을 형성한다.Referring to FIG. 1D, through the etching process using the second mask layer 40, the interlayer insulating layer 35 and the oxide layer 28 for spacers in the PMOS region are sequentially etched, thereby causing the gate 24 to be etched. After the spacers 30 are formed on the sidewalls, the second mask 50 is removed. Thereafter, after the cleaning process, a P-type silicon epitaxial film 37 is formed on the low concentration impurity region 26 in the PMOS region.
상기에서, P-타입 실리콘 에피택셜막(32)은 50 내지 2000Å의 두께로 형성되며, 단결정 실리콘막 성장시에 B2H6가스를 주입하는 인-시투 도핑에 의해 형성되거나, 단결정 실리콘막 성장 후 P-타입 이온주입이 실시되어 형성된다. 인-시투 도핑 공정은 PMOS 지역의 단결정 실리콘막 성장시, 전기적 저항 감소를 위해 B2H6가스가 증착 챔버에 주입되고 이때, 붕소 이온이 도핑되도록 실시된다. 또한, PMOS 지역의 단결정 실리콘막 성장후, 전기적 저항 감소를 위한 P-타입 도펀트는 붕소 등의 3 족 이온이 사용된다. 도핑 레벨은 1.0×1018내지 1021atoms/㎤이다.In the above description, the P-type silicon epitaxial film 32 is formed to have a thickness of 50 to 2000 GPa, and is formed by in-situ doping which injects B 2 H 6 gas when the single crystal silicon film is grown, or grows a single crystal silicon film. P-type ion implantation is then performed to form. The in-situ doping process is performed to inject a B 2 H 6 gas into the deposition chamber to reduce the electrical resistance during growth of the monocrystalline silicon film in the PMOS region, at which time boron ions are doped. In addition, after the growth of the single crystal silicon film in the PMOS region, Group 3 ions such as boron are used as the P-type dopant for reducing the electrical resistance. The doping level is 1.0 × 10 18 to 10 21 atoms / cm 3.
이후, 후속 열처리 공정을 실시하여 주입된 불순물의 액티베이션 및 확산 등을 통해 엘리베이티드 소오스/드레인 영역을 완성한다.Subsequently, a subsequent heat treatment process is performed to complete the elevated source / drain region through activation and diffusion of the implanted impurities.
(제 2 실시예)(Second embodiment)
도 2(a) 내지 도 2(e)는 본 발명에 따른 반도체 소자의 트랜지스터 형성 방법의 다른 예를 설명하기 위한 단면도이다.2 (a) to 2 (e) are cross-sectional views for explaining another example of a method for forming a transistor of a semiconductor device according to the present invention.
도 2(a)를 참조하면, NMOS 지역 및 PMOS 지역이 형성되는 실리콘 기판(110)에 필드 산화막(120)을 형성하여 액티브 영역을 정의한다. 상기 액티브 영역상에 게이트 산화막 및 게이트용 폴리실리콘을 증착한 후, 마스크를 이용한 식각 공정을 통해 게이트용 폴리실리콘 및 게이트 산화막을 순차적으로 식각하여 게이트 산화막(122) 및 게이트(124)를 각각 형성한다. 이후 라이틀리 도프트 드레인(Lighty Doped Drain; LDD) 이온주입 공정을 실시하여 저농도 불순물 영역(126)을 형성한 후, 상기 전체 구조상에 스페이서용 산화막(128)을 증착한다. PMOS 지역의 스페이서용 산화막(128)상에 포토레지스터를 이용한 제 1 마스크층(140)을 형성한다.Referring to FIG. 2A, a field oxide layer 120 is formed on a silicon substrate 110 in which an NMOS region and a PMOS region are formed to define an active region. After the gate oxide film and the gate polysilicon are deposited on the active region, the gate polysilicon and the gate oxide film are sequentially etched through an etching process using a mask to form the gate oxide film 122 and the gate 124, respectively. . Thereafter, a lightly doped drain (LDD) ion implantation process is performed to form a low concentration impurity region 126, and then a spacer oxide layer 128 is deposited on the entire structure. A first mask layer 140 using a photoresist is formed on the spacer oxide layer 128 in the PMOS region.
상기에서, 게이트용 폴리실리콘은 텅스텐 실리사이드를 증착할 수 있다.In the above, the gate polysilicon may deposit tungsten silicide.
도 2(b)를 참조하면, 상기 제 1 마스크층(40)을 이용한 식각 공정을 통해 NMOS 지역의 스페이서용 산화막(128)을 식각하고, 이로 인하여 게이트(124) 측벽에 스페이서(129)가 형성된 후, 제 1 마스크(140)를 제거한다. 이후, 세정 공정을 실시한 후, NMOS 지역의 저농도 불순물 영역(126)상에 N-타입 실리콘 에피택셜막(132)을 형성한다.Referring to FIG. 2 (b), the spacer oxide layer 128 in the NMOS region is etched through an etching process using the first mask layer 40, whereby the spacer 129 is formed on the sidewall of the gate 124. After that, the first mask 140 is removed. Thereafter, after the cleaning process, an N-type silicon epitaxial film 132 is formed on the low concentration impurity region 126 in the NMOS region.
상기에서, N-타입 실리콘 에피택셜막(132)은 50 내지 2000Å의 두께로 형성되며, 단결정 실리콘막 성장시에 PH3가스를 주입하는 인-시투 도핑에 의해 형성되거나, 단결정 실리콘막 성장 후 N-타입 이온주입이 실시되어 형성된다. 인-시투 도핑 공정은 NMOS 지역의 단결정 실리콘막 성장시, 전기적 저항 감소를 위해 PH3가스가 증착 챔버에 주입되고 이때, 인 이온이 도핑되도록 실시된다. 또한, NMOS 지역의 단결정 실리콘막 성장후, 전기적 저항 감소를 위한 N-타입 도펀트는 비소 및 인 등의 5 족 이온이 사용된다. 도핑 레벨은 1.0×1018내지 1021atoms/㎤이다.In the above description, the N-type silicon epitaxial film 132 is formed to have a thickness of 50 to 2000 GPa, and is formed by in-situ doping that injects PH 3 gas during growth of the single crystal silicon film, or after growth of the single crystal silicon film. It is formed by -type ion implantation. The in-situ doping process is performed so that, upon growth of a single crystal silicon film in an NMOS region, a PH 3 gas is injected into the deposition chamber to reduce the electrical resistance, at which time phosphorus ions are doped. In addition, after the growth of the single crystal silicon film in the NMOS region, Group 5 ions such as arsenic and phosphorus are used as the N-type dopant for reducing the electrical resistance. The doping level is 1.0 × 10 18 to 10 21 atoms / cm 3.
상기의 경우, 형성되는 실리콘 에피택셜막 및 불순물의 도핑 정도는 게이트의 높이와 형성될 접합의 깊이를 고려하여 결정한다.In this case, the degree of doping of the silicon epitaxial film and the impurities to be formed is determined in consideration of the height of the gate and the depth of the junction to be formed.
도 1(c)를 참조하면, 상기 N-타입 실리콘 에피택셜막(132)이 형성된 전체 구조상에 층간 절연막(135)를 형성한 후, NMOS 지역의 층간 절연막(135)상에 포토레지스터를 이용한 제 2 마스크층(150)을 형성한다.Referring to FIG. 1C, after the interlayer insulating layer 135 is formed on the entire structure where the N-type silicon epitaxial layer 132 is formed, a photoresist is used on the interlayer insulating layer 135 in the NMOS region. 2 mask layer 150 is formed.
상기에서, 층간 절연막(135; IOP: Inter Poly Oxide)은 BPSG 또는 열산화막(Thermal Oxide)을 사용한다.In the above, the interlayer insulating layer 135 (Inter Poly Oxide (IOP)) uses BPSG or Thermal Oxide.
도 1(d)를 참조하면, 상기 제 2 마스크층(140)을 이용한 식각 공정을 통해 PMOS 지역의 층간 절연막(135), N-타입 실리콘 에피택셜막(132) 및 스페이서용 산화막(28)을 순차적으로 식각하고, 이로 인하여 게이트(124) 측벽에 스페이서(130)가 형성된 후, 제 2 마스크(150)를 제거한다. 이후, 세정 공정을 실시한 후, NMOS 지역 및 PMOS 지역의 전체 구조상에 P-타입 실리콘 에피택셜막(137)을 형성한다.Referring to FIG. 1D, an interlayer insulating layer 135, an N-type silicon epitaxial layer 132, and an oxide oxide layer 28 for a spacer are formed through an etching process using the second mask layer 140. After etching sequentially, a spacer 130 is formed on the sidewall of the gate 124, and then the second mask 150 is removed. Thereafter, after performing the cleaning process, the P-type silicon epitaxial film 137 is formed on the entire structure of the NMOS region and the PMOS region.
상기에서, P-타입 실리콘 에피택셜막(132)은 50 내지 2000Å의 두께로 형성되며, 단결정 실리콘막 성장시에 B2H6가스를 주입하는 인-시투 도핑에 의해 형성되거나, 단결정 실리콘막 성장 후 P-타입 이온주입이 실시되어 형성된다. 인-시투 도핑 공정은 PMOS 지역의 단결정 실리콘막 성장시, 전기적 저항 감소를 위해 B2H6가스가 증착 챔버에 주입되고 이때, 붕소 이온이 도핑되도록 실시된다. 또한, PMOS 지역의 단결정 실리콘막 성장후, 전기적 저항 감소를 위한 P-타입 도펀트는 붕소 등의 3 족 이온이 사용된다. 도핑 레벨은 1.0×1018내지 1021atoms/㎤이다.In the above description, the P-type silicon epitaxial film 132 is formed to have a thickness of 50 to 2000 GPa, and is formed by in-situ doping which injects B 2 H 6 gas during single crystal silicon film growth, or grows a single crystal silicon film. P-type ion implantation is then performed to form. The in-situ doping process is performed to inject a B 2 H 6 gas into the deposition chamber to reduce the electrical resistance during growth of the monocrystalline silicon film in the PMOS region, at which time boron ions are doped. In addition, after the growth of the single crystal silicon film in the PMOS region, Group 3 ions such as boron are used as the P-type dopant for reducing the electrical resistance. The doping level is 1.0 × 10 18 to 10 21 atoms / cm 3.
도 2(e)를 참조하면, NMOS 지역의 N-타입 실리콘 에피택셜막(132)이 노출되도록 하기 위해, P-타입 실리콘 에피택셜막(137) 및 층간 절연막(135)을 순차적으로 식각한다. 이후, 마스크를 이용한 식각 공정으로 게이트(124) 상부가 개방된 N-타입 및 P-타입 실리콘 에피택셜막(133 및 138)을 형성한다.Referring to FIG. 2E, the P-type silicon epitaxial layer 137 and the interlayer insulating layer 135 are sequentially etched to expose the N-type silicon epitaxial layer 132 in the NMOS region. Subsequently, an N-type and P-type silicon epitaxial layer 133 and 138 having an open upper portion of the gate 124 are formed by an etching process using a mask.
이후, 후속 열처리 공정을 실시하여 주입된 불순물의 액티베이션 및 확산 등을 통해 엘리베이티드 소오스/드레인 영역을 완성한다.Subsequently, a subsequent heat treatment process is performed to complete the elevated source / drain region through activation and diffusion of the implanted impurities.
상술한 바와 같이, 본 발명에 의하면 게이트 너비가 감소해도 충분한 채널 길이와 접합 깊이를 확보할 수 있으므로 숏트 채널 효과 개선 및 접합 누설전류의 감소에 탁월한 효과가 있다.As described above, according to the present invention, even if the gate width is reduced, sufficient channel length and junction depth can be secured, thereby providing an excellent effect on short channel effect improvement and junction leakage current reduction.
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