KR20000003941A - Barrier metal of semiconductor devices - Google Patents
Barrier metal of semiconductor devices Download PDFInfo
- Publication number
- KR20000003941A KR20000003941A KR1019980025249A KR19980025249A KR20000003941A KR 20000003941 A KR20000003941 A KR 20000003941A KR 1019980025249 A KR1019980025249 A KR 1019980025249A KR 19980025249 A KR19980025249 A KR 19980025249A KR 20000003941 A KR20000003941 A KR 20000003941A
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- South Korea
- Prior art keywords
- thin film
- barrier metal
- tan
- tin
- metal
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 30
- 239000002184 metal Substances 0.000 title claims abstract description 30
- 230000004888 barrier function Effects 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 239000010409 thin film Substances 0.000 claims abstract description 39
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 5
- 239000002994 raw material Substances 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 10
- 150000002739 metals Chemical class 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- OEIMLTQPLAGXMX-UHFFFAOYSA-I tantalum(v) chloride Chemical compound Cl[Ta](Cl)(Cl)(Cl)Cl OEIMLTQPLAGXMX-UHFFFAOYSA-I 0.000 abstract description 3
- 230000035515 penetration Effects 0.000 abstract description 2
- 229910004537 TaCl5 Inorganic materials 0.000 abstract 1
- 239000007789 gas Substances 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007736 thin film deposition technique Methods 0.000 description 1
- 239000006200 vaporizer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 고집적 메모리소자의 베리어메탈 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a barrier metal of a highly integrated memory device.
잘 알려진 바와 같이, 고집적 메모리소자의 금속배선 또는 금속 비트라인을 형성함에 있어, 접합층(즉, 트랜지스터의 소스/드레인)의 실리콘과 배선용 금속간의 상호원자확산을 방지하고, 배선용 금속의 접착력을 향상시키며, 또한 접합층과의 접촉저항을 낮추기 위해서, 베리어메탈을 사용하고 있음은 주지의 사실이다.As is well known, in forming the metal wiring or the metal bit line of the highly integrated memory device, it is possible to prevent mutual atom diffusion between the silicon of the bonding layer (ie, the source / drain of the transistor) and the wiring metal, and to improve the adhesion of the wiring metal. It is well known that barrier metal is used to reduce the contact resistance with the bonding layer.
도1에는 종래기술에 따른 베리어메탈 구조가 도시되어 있다. 도1을 참조하면, 실리콘기판(1)의 접합층(2)이 노출되도록 절연막(3)이 식각되어 콘택홀이 형성되고, 이 콘택홀을 통해 내부연결배선용 또는 비트라인용 금속막(6)이 콘택될 때, 금속막 하부에 베리어메탈로서 Ti 박막(4)과 TiN 박막(5)이 차례로 적층된다.1 shows a barrier metal structure according to the prior art. Referring to FIG. 1, an insulating film 3 is etched to expose a bonding layer 2 of a silicon substrate 1 to form a contact hole, and a metal film 6 for internal connection wiring or a bit line is formed through the contact hole. When this contact is made, the Ti thin film 4 and the TiN thin film 5 are sequentially stacked as a barrier metal under the metal film.
그런데, TiN 박막은 수분 및 산소를 잘 흡수하여 후속 공정을 거치면서 접합층에 있는 실리콘(Si)과 반응하여 SiO2를 형성하게 되며, 이에 의해 접촉저항이 커지므로써 소자의 동작 속도를 저해하거나 오동작을 일으키는 원인을 제공하게 된다.However, the TiN thin film absorbs moisture and oxygen well and reacts with silicon (Si) in the bonding layer during the subsequent process to form SiO 2 , thereby increasing the contact resistance, thereby inhibiting the operation speed of the device or malfunctioning. To provide a cause.
본 발명은 상기 문제점을 해결하기 위하여 안출된 것으로써, 메탈이 콘택된 접합층으로 외부의 수분 및 산소가 침투하는 것을 최대한 억제하여 산화막이 생성되는 것을 방지하므로써, 소자의 특성을 개선하는 반도체소자의 베리어메탈을 제공함을 목적으로 한다.The present invention has been made in order to solve the above problems, the metal of the semiconductor device that improves the characteristics of the device by preventing the formation of an oxide film to minimize the penetration of external moisture and oxygen into the contact layer The purpose is to provide a barrier metal.
도1은 종래기술에 따른 베리어메탈 구조를 나타내는 단면도.1 is a cross-sectional view showing a barrier metal structure according to the prior art.
도2a 내지 도2c는 본 발명의 일실시예에 따른 베리어메탈 형성방법을 나타내는 공정 단면도.Figures 2a to 2c is a cross-sectional view showing a barrier metal forming method according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 접합층1 silicon substrate 2 bonding layer
3 : 절연막 4 : Ti 박막3: insulating film 4: Ti thin film
5 : TiN 박막 6 : 금속막5: TiN thin film 6: Metal film
20 : TaN 박막20: TaN thin film
상기 목적을 달성하기 위한 본 발명은, 금속막과 실리콘층 간에 형성되는 베리어메탈에 있어서, 상기 베리어메탈이 하부로부터 차례로 적층된 Ti 박막과 TaN 박막 및 TiN 박막을 포함하여 이루어지는 것을 특징으로 한다.In the barrier metal formed between the metal film and the silicon layer, the present invention for achieving the above object is characterized in that the barrier metal comprises a Ti thin film, a TaN thin film and a TiN thin film sequentially stacked from the bottom.
바람직하게, 제1항에 있어서, 상기 Ti 박막과 TaN 박막 및 TiN 박막은 각각 100∼500Å, 100∼300Å, 및 200∼500Å의 두께를 가지는 것을 특징으로 한다.Preferably, the Ti thin film, the TaN thin film, and the TiN thin film are characterized in that they have a thickness of 100 to 500 GPa, 100 to 300 GPa, and 200 to 500 GPa, respectively.
또한, 상기 TaN 박막은 기상상태의 TaCl5를 원료로하여 LPCVD 방법으로 형성되어진 것을 특징으로 한다.In addition, the TaN thin film is characterized in that formed by the LPCVD method using TaCl 5 in the gaseous state as a raw material.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2c는 본 발명의 일실시예에 따른 베리어메탈 형성방법을 나타내는 공정 단면도이다. 종래기술과 동일한 구성요소(박막)에 대해서는 동일한 도면부호를 인용하였다.2A through 2C are cross-sectional views illustrating a barrier metal forming method according to an embodiment of the present invention. The same reference numerals are used for the same components (thin films) as in the prior art.
도2a에는 실리콘기판(1)의 접합층(2)이 노출되도록 절연막(3)이 식각되어 콘택홀이 형성되고, Ti 박막(4)이 형성된 상태가 도시되어 있다. Ti 박막(4)의 증착조건은 온도를 25∼700℃, 압력을 0.2∼10Torr, 유량을 10∼100sccm으로 하여 100∼500Å 증착한다.FIG. 2A illustrates a state in which the insulating film 3 is etched to form a contact hole and the Ti thin film 4 is formed so that the bonding layer 2 of the silicon substrate 1 is exposed. The deposition conditions for the Ti thin film 4 are 100 to 500 kPa deposited at a temperature of 25 to 700 DEG C, a pressure of 0.2 to 10 Torr, and a flow rate of 10 to 100 sccm.
도2b에는 100∼300Å의 두께로 TaN 박막(20)이 형성된 상태가 도시되어 있다. 구체적으로, TaN 박막 증착 방법 및 증착조건은 다음과 같다.2B shows a state in which the TaN thin film 20 is formed to a thickness of 100 to 300 GPa. Specifically, TaN thin film deposition method and deposition conditions are as follows.
실온에서 고체 상태인 탄탈륨클로라이드(TaCl5)를 140℃ 이상으로 유지되는 기화기에서 기상 상태로 만들어, 이 기상 상태의 탄탈륨클로라이드(TaCl5)를 반응원료로 사용한다. 반응 개스로는 10∼1000sccm 정도의 NH3를 사용한다. 반응로 내의 압력을 0.1∼1.2 Torr로 유지하고 웨이퍼를 350∼450℃로 가열한 상태에서 TaN 박막이 증착되도록 한다. TaN 박막을 LPCVD법으로 증착할 경우 RF 파워를 50∼400Watt로 유지하여 증착한다. 그리고, RF 파워 인가시 기판히터를 접지하고 샤워헤드를 전극으로 한다.Tantalum chloride (TaCl 5 ), which is in solid state at room temperature, is brought to a gaseous state in a vaporizer maintained at 140 ° C. or higher, and the gaseous tantalum chloride (TaCl 5 ) is used as a reaction raw material. As the reaction gas, NH 3 of about 10 to 1000 sccm is used. The pressure in the reactor is maintained at 0.1 to 1.2 Torr and the TaN thin film is deposited while the wafer is heated to 350 to 450 ° C. When the TaN thin film is deposited by LPCVD, it is deposited while maintaining RF power at 50 to 400 Watts. When the RF power is applied, the substrate heater is grounded and the shower head is used as the electrode.
도2c에는 200∼500Å의 두께로 TiN 박막(5)이 증착된 상태가 도시되어 있다. TiN 박막(5)의 증착은 온도 250℃∼700℃, 압력 0.2∼10 Torr, 유량 10∼100sccm에서 실시한다.2C shows a state in which the TiN thin film 5 is deposited to a thickness of 200 to 500 kPa. The TiN thin film 5 is deposited at a temperature of 250 ° C. to 700 ° C., a pressure of 0.2 to 10 Torr, and a flow rate of 10 to 100 sccm.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 내산화성과 열적 안정성이 우수한 TaN 박막이 추가되어 "Ti/TaN/TiN" 구조를 갖는 베리어메탈을 제공하므로써, 콘택저부의 접합층 표면에서 발생되는 산화막(SiO2) 생성을 방지하여 배선용 금속의 접촉저항을 줄일 수 있다.The present invention provides a barrier metal having a "Ti / TaN / TiN" structure by adding a TaN thin film having excellent oxidation resistance and thermal stability, thereby preventing the formation of an oxide film (SiO 2 ) generated on the contact layer surface of the contactor part. The contact resistance of metal can be reduced.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1998-0025249A KR100463236B1 (en) | 1998-06-30 | 1998-06-30 | Barrier Metals of Semiconductor Devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1998-0025249A KR100463236B1 (en) | 1998-06-30 | 1998-06-30 | Barrier Metals of Semiconductor Devices |
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| Publication Number | Publication Date |
|---|---|
| KR20000003941A true KR20000003941A (en) | 2000-01-25 |
| KR100463236B1 KR100463236B1 (en) | 2005-04-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1998-0025249A KR100463236B1 (en) | 1998-06-30 | 1998-06-30 | Barrier Metals of Semiconductor Devices |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100379522B1 (en) * | 2000-11-29 | 2003-04-10 | 주식회사 하이닉스반도체 | Method for fabricating bit line in semiconductor device |
| KR100440468B1 (en) * | 2001-12-21 | 2004-07-14 | 아남반도체 주식회사 | Formation method of semiconductor device |
| KR100529646B1 (en) * | 2001-12-21 | 2005-11-17 | 동부아남반도체 주식회사 | Formation method of semiconductor device |
-
1998
- 1998-06-30 KR KR10-1998-0025249A patent/KR100463236B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100379522B1 (en) * | 2000-11-29 | 2003-04-10 | 주식회사 하이닉스반도체 | Method for fabricating bit line in semiconductor device |
| KR100440468B1 (en) * | 2001-12-21 | 2004-07-14 | 아남반도체 주식회사 | Formation method of semiconductor device |
| KR100529646B1 (en) * | 2001-12-21 | 2005-11-17 | 동부아남반도체 주식회사 | Formation method of semiconductor device |
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| Publication number | Publication date |
|---|---|
| KR100463236B1 (en) | 2005-04-06 |
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