KR20000003643A - Method for forming a contact of semiconductor devices - Google Patents
Method for forming a contact of semiconductor devices Download PDFInfo
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- KR20000003643A KR20000003643A KR1019980024905A KR19980024905A KR20000003643A KR 20000003643 A KR20000003643 A KR 20000003643A KR 1019980024905 A KR1019980024905 A KR 1019980024905A KR 19980024905 A KR19980024905 A KR 19980024905A KR 20000003643 A KR20000003643 A KR 20000003643A
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- Prior art keywords
- contact
- conductive layer
- forming
- contact hole
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Abstract
Description
본 발명은 반도체소자의 콘택 제조방법에 관한 것으로, 특히 고집적 소자의 콘택 제조 공정시 아르곤을 사용한 스퍼터링공정으로 콘택홀의 양측벽에 도전층의 잔류물이 증착되게 함으로써 콘택홀 내부에서의 접촉면적을 넓혀 콘택 저항을 감소시켜 소자의 특성 및 신뢰성을 향상시키고, 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact of a semiconductor device. In particular, a contact sputtering process using argon during the contact manufacturing process of a highly integrated device allows a residue of conductive layer to be deposited on both side walls of the contact hole, thereby increasing the contact area inside the contact hole. The present invention relates to a technology for reducing contact resistance, improving device characteristics and reliability, and thereby enabling high integration of semiconductor devices.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture:NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.
[R=k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선, 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하거나, 공정 상의 방법으로는 노광마스크를 위상 반전 마스크를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer: 이하 CEL이라 함) 방법이나 두층의 감광막 사이에 에스.오.지.(spin on glass: SOG) 등의 중간층을 개재시킨 삼층레지스트(Tri layer resist: 이하 TLR 라 함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. In order to form a fine pattern of 0.5 μm or less, the micrometer has a limit of about μm, and an exposure apparatus using an ultraviolet ray having a small wavelength, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source, or a process As a method of imaging, a method of using a phase inversion mask as an exposure mask and a method of forming a separate thin film on the wafer which can improve image contrast can be used. A tri layer resist method (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers or silicon on a photoresist layer selectively. It has been developed, such as silico-migration method for injection may lower the resolution limit.
또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들 간의 정확하고, 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이러한 콘택홀은 간격 유지를 위하여 마스크 정렬시의 오배열의 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화, 마스크간의 정합 등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes have factors such as misalignment tolerance during mask alignment, lens distortion during exposure process, threshold size change during mask fabrication and photolithography process, and matching between masks to maintain gaps. Consider these to form a mask.
종래기술에 따른 반도체소자의 콘택 제조방법은, 고집적화에 따라 소자간의 간격이 계속 좁아져 콘택홀내의 접촉면적이 작아지고 그에 따라 콘택의 크기가 작아지기 때문에 콘택 저항이 증가하여 공정 수율 및 소자동작의 신뢰성을 떨어드리는 문제점이 있다.In the conventional method for manufacturing a contact of a semiconductor device, the gap between the devices continues to narrow with high integration, so that the contact area in the contact hole decreases and the size of the contact decreases, thereby increasing the contact resistance and improving the process yield and device operation. There is a problem of lowering reliability.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 콘택홀에 의해 노출된 도전층을 아르곤 스퍼터링하여 상기 콘택홀의 양측벽 하단에 상기 도전층의 잔류물을 증착시킴으로써 콘택면적을 증가시켜 콘택 저항을 감소시키고, 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 콘택 제조방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by argon sputtering the conductive layer exposed by the contact hole to deposit the residue of the conductive layer on the bottom of both side walls of the contact hole to increase the contact area to increase the contact resistance SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a contact for a semiconductor device, which reduces the number of semiconductor devices and enables high integration of the semiconductor device.
도 1a 내지 도 1c 는 본 발명에 따른 반도체소자의 콘택 제조방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a method for manufacturing a contact of a semiconductor device according to the present invention.
◈ 도면의 주요부분에 대한 부호의 설명◈ Explanation of symbols for the main parts of the drawings
11 : 반도체기판 13 : 도전층11: semiconductor substrate 13: conductive layer
15 : 층간절연막 17 : 감광막 패턴15: interlayer insulating film 17: photosensitive film pattern
19 : 도전층의 잔류물19: residue of conductive layer
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 콘택 제조방법은,Contact manufacturing method of a semiconductor device according to the present invention for achieving the above object,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 도전층을 형성하는 공정과,Forming a conductive layer on top of the semiconductor substrate on which a predetermined substructure is formed;
상기 도전층 상부에 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a contact hole exposing a portion intended to be a contact on the conductive layer;
상기 콘택홀에 의해 노출되어 있는 도전층을 아르곤가스를 사용한 스퍼터링공정으로 상기 콘택홀의 측벽에 상기 도전층의 잔류물을 증착시킴으로써 콘택면적을 증가시키는 공정을 포함하는 것을 특징으로 한다.And depositing a residue of the conductive layer on the sidewall of the contact hole by a sputtering process using argon gas on the conductive layer exposed by the contact hole.
이하, 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 1a 내지 도 1c 은 본 발명에 따른 반도체소자의 콘택 제조방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method for manufacturing a contact of a semiconductor device according to the present invention.
먼저, 소정의 하부구조물이 형성되어 있는 반도체기판(11) 상부에 상기 하부구조물과 접속되는 도전층(13)을 형성한다. 상기 도전층(13)은 다결정실리콘층이나 텅스텐실리사이드층을 사용하여 형성한다.First, a conductive layer 13 connected to the lower structure is formed on the semiconductor substrate 11 on which a predetermined lower structure is formed. The conductive layer 13 is formed using a polysilicon layer or a tungsten silicide layer.
다음, 상기 도전층(13) 상부에 층간절연막(15)을 형성하고, 상기 층간절연막(15) 상부에 콘택으로 예정되는 부분의 상기 도전층(13)을 노출시키는 감광막 패턴(17)을 형성한다. (도 1a참조)Next, an interlayer insulating film 15 is formed on the conductive layer 13, and a photosensitive film pattern 17 is formed on the interlayer insulating film 15 to expose the conductive layer 13 in a portion to be contacted. . (See FIG. 1A)
그 다음, 상기 감광막 패턴(17)을 식각마스크로 상기 층간절연막(15)을 식각하여 콘택홀을 형성하고, 상기 감광막 패턴(17)을 제거한다. (도 1b참조)Next, the interlayer insulating layer 15 is etched using the photoresist pattern 17 as an etch mask to form a contact hole, and the photoresist pattern 17 is removed. (See FIG. 1B)
그 후, 상기 콘택홀에 의해 노출되는 도전층(13)을 아르곤을 이용하여 소정 두께 스퍼터링한다. 상기 스퍼터링 공정은 상기 감광막 패턴을 제거하기 전에 실시할 수도 있다.Thereafter, the conductive layer 13 exposed by the contact hole is sputtered by a predetermined thickness using argon. The sputtering process may be performed before removing the photosensitive film pattern.
이때, 소정 두께의 도전층(13)이 식각되면서 다시 상기 콘택홀의 양측벽 하단에 상기 도전층의 잔류물(19)이 증착되어 콘택면적이 증가되는 현상이 발생한다. (도 1c참조)At this time, as the conductive layer 13 having a predetermined thickness is etched, a residue 19 of the conductive layer is deposited on both lower ends of the contact holes, thereby increasing the contact area. (See FIG. 1C)
상기와 같은 콘택홀 형성방법은 반도체기판을 노출시키는 콘택형성공정 및 금속콘택 형성공정시 사용될 수 있다.The contact hole forming method as described above may be used in a contact forming process and a metal contact forming process for exposing a semiconductor substrate.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 콘택 제조방법은, 콘택으로 예정되는 부분의 도전층을 노출시키는 콘택홀을 형성한 다음, 상기 콘택홀에 의해 노출된 도전층을 아르곤으로 스퍼터링하여 소정 두께 제거하면 다시 상기 콘택홀의 양측벽 하단에 도전층의 잔류물을 증착시킴으로써 콘택면적을 증가시켜 콘택 저항을 감소시키고, 상기 콘택홀을 매립하는 공정시 층덮힘을 개선하여 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 이점이 있다.As described above, in the method for manufacturing a contact of a semiconductor device according to the present invention, a contact hole for exposing a conductive layer of a portion to be defined as a contact is formed, and then the conductive layer exposed by the contact hole is sputtered with argon. When the thickness is removed, the residue of the conductive layer is deposited on the bottom of both side walls of the contact hole, thereby increasing the contact area to reduce the contact resistance and improving the layer covering during the process of filling the contact hole, thereby improving the characteristics and reliability of the device. And thereby high integration of the semiconductor device is possible.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024905A KR100333537B1 (en) | 1998-06-29 | 1998-06-29 | Contact manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024905A KR100333537B1 (en) | 1998-06-29 | 1998-06-29 | Contact manufacturing method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR20000003643A true KR20000003643A (en) | 2000-01-25 |
| KR100333537B1 KR100333537B1 (en) | 2002-09-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019980024905A KR100333537B1 (en) | 1998-06-29 | 1998-06-29 | Contact manufacturing method of semiconductor device |
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| KR (1) | KR100333537B1 (en) |
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- 1998-06-29 KR KR1019980024905A patent/KR100333537B1/en not_active IP Right Cessation
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