KR19990071554A - 어드레스충돌검출기능을갖는멀티포트캐시메모리 - Google Patents

어드레스충돌검출기능을갖는멀티포트캐시메모리 Download PDF

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Publication number
KR19990071554A
KR19990071554A KR1019980703828A KR19980703828A KR19990071554A KR 19990071554 A KR19990071554 A KR 19990071554A KR 1019980703828 A KR1019980703828 A KR 1019980703828A KR 19980703828 A KR19980703828 A KR 19980703828A KR 19990071554 A KR19990071554 A KR 19990071554A
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KR
South Korea
Prior art keywords
bank
port
access
cache
memory
Prior art date
Application number
KR1019980703828A
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English (en)
Korean (ko)
Inventor
아이노 야콥스
Original Assignee
요트.게.아. 롤페즈
코닌클리케 필립스 일렉트로닉스 엔.브이.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 요트.게.아. 롤페즈, 코닌클리케 필립스 일렉트로닉스 엔.브이. filed Critical 요트.게.아. 롤페즈
Publication of KR19990071554A publication Critical patent/KR19990071554A/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1019980703828A 1996-09-25 1997-09-23 어드레스충돌검출기능을갖는멀티포트캐시메모리 KR19990071554A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US71960996A 1996-09-25 1996-09-25
US8/719,609 1996-09-25
PCT/IB1997/001146 WO1998013763A2 (fr) 1996-09-25 1997-09-23 Memoire cache a acces multiples avec detection de conflits d'adresse

Publications (1)

Publication Number Publication Date
KR19990071554A true KR19990071554A (ko) 1999-09-27

Family

ID=24890679

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980703828A KR19990071554A (ko) 1996-09-25 1997-09-23 어드레스충돌검출기능을갖는멀티포트캐시메모리

Country Status (4)

Country Link
EP (1) EP0875030A2 (fr)
JP (1) JP2000501539A (fr)
KR (1) KR19990071554A (fr)
WO (1) WO1998013763A2 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100780621B1 (ko) * 2005-09-29 2007-11-29 주식회사 하이닉스반도체 멀티 포트 메모리 소자
US7613065B2 (en) 2005-09-29 2009-11-03 Hynix Semiconductor, Inc. Multi-port memory device
KR100955722B1 (ko) * 2002-11-26 2010-05-03 어드밴스드 마이크로 디바이시즈, 인코포레이티드 사이클당 복수의 액세스를 지원하는 캐시 메모리를 구비한마이크로프로세서
KR100974024B1 (ko) * 2004-03-24 2010-08-05 콸콤 인코포레이티드 내장형 디지털 신호 처리기용 캐시 메모리 시스템 및 캐시제어기
US8583873B2 (en) 2010-03-10 2013-11-12 Samsung Electronics Co., Ltd. Multiport data cache apparatus and method of controlling the same
KR20140011929A (ko) * 2012-07-19 2014-01-29 에이알엠 리미티드 멀티포트 메모리에서의 액세스시의 충돌 처리
WO2016089020A1 (fr) * 2014-12-05 2016-06-09 삼성전자 주식회사 Procédé et appareil de commande d'accès mémoire

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19809640A1 (de) * 1998-03-06 1999-09-09 Pact Inf Tech Gmbh Geschwindigkeitsoptimiertes Cachesystem
US6539457B1 (en) * 2000-02-21 2003-03-25 Hewlett-Packard Company Cache address conflict mechanism without store buffers
US6557078B1 (en) * 2000-02-21 2003-04-29 Hewlett Packard Development Company, L.P. Cache chain structure to implement high bandwidth low latency cache memory subsystem
US6606684B1 (en) 2000-03-31 2003-08-12 Intel Corporation Multi-tiered memory bank having different data buffer sizes with a programmable bank select
US6446181B1 (en) 2000-03-31 2002-09-03 Intel Corporation System having a configurable cache/SRAM memory
KR100754359B1 (ko) * 2006-03-29 2007-09-03 엠텍비젼 주식회사 복수의 공유 블록을 포함하는 다중 포트 메모리 장치
KR101788245B1 (ko) 2011-02-25 2017-11-16 삼성전자주식회사 다중 포트 캐시 메모리 장치 및 그 구동 방법
CN102622192B (zh) * 2012-02-27 2014-11-19 北京理工大学 一种弱相关多端口并行存储控制器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0668735B2 (ja) * 1987-02-09 1994-08-31 日本電気アイシーマイコンシステム株式会社 キヤツシユメモリ−
US5276850A (en) * 1988-12-27 1994-01-04 Kabushiki Kaisha Toshiba Information processing apparatus with cache memory and a processor which generates a data block address and a plurality of data subblock addresses simultaneously
JP2822588B2 (ja) * 1990-04-30 1998-11-11 日本電気株式会社 キャッシュメモリ装置
US5434989A (en) * 1991-02-19 1995-07-18 Matsushita Electric Industrial Co., Ltd. Cache memory for efficient access with address selectors

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100955722B1 (ko) * 2002-11-26 2010-05-03 어드밴스드 마이크로 디바이시즈, 인코포레이티드 사이클당 복수의 액세스를 지원하는 캐시 메모리를 구비한마이크로프로세서
KR100974024B1 (ko) * 2004-03-24 2010-08-05 콸콤 인코포레이티드 내장형 디지털 신호 처리기용 캐시 메모리 시스템 및 캐시제어기
US8316185B2 (en) 2004-03-24 2012-11-20 Qualcomm Incorporated Cached memory system and cache controller for embedded digital signal processor
KR100780621B1 (ko) * 2005-09-29 2007-11-29 주식회사 하이닉스반도체 멀티 포트 메모리 소자
US7613065B2 (en) 2005-09-29 2009-11-03 Hynix Semiconductor, Inc. Multi-port memory device
US8583873B2 (en) 2010-03-10 2013-11-12 Samsung Electronics Co., Ltd. Multiport data cache apparatus and method of controlling the same
KR20140011929A (ko) * 2012-07-19 2014-01-29 에이알엠 리미티드 멀티포트 메모리에서의 액세스시의 충돌 처리
WO2016089020A1 (fr) * 2014-12-05 2016-06-09 삼성전자 주식회사 Procédé et appareil de commande d'accès mémoire
KR20160068479A (ko) * 2014-12-05 2016-06-15 삼성전자주식회사 메모리 접근 제어 방법 및 장치
US10983723B2 (en) 2014-12-05 2021-04-20 Samsung Electronics Co., Ltd. Memory access control method and apparatus

Also Published As

Publication number Publication date
JP2000501539A (ja) 2000-02-08
WO1998013763A3 (fr) 1998-06-04
EP0875030A2 (fr) 1998-11-04
WO1998013763A2 (fr) 1998-04-02

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