KR19990030505A - Capacitor Formation Method - Google Patents
Capacitor Formation Method Download PDFInfo
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- KR19990030505A KR19990030505A KR1019970050717A KR19970050717A KR19990030505A KR 19990030505 A KR19990030505 A KR 19990030505A KR 1019970050717 A KR1019970050717 A KR 1019970050717A KR 19970050717 A KR19970050717 A KR 19970050717A KR 19990030505 A KR19990030505 A KR 19990030505A
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- insulating layer
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- forming
- polycrystalline silicon
- sidewall
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000003990 capacitor Substances 0.000 title claims abstract description 22
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 239000010410 layer Substances 0.000 abstract description 127
- 239000011229 interlayer Substances 0.000 abstract description 27
- 238000003860 storage Methods 0.000 abstract description 14
- 239000007788 liquid Substances 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 102000004169 proteins and genes Human genes 0.000 description 1
- 108090000623 proteins and genes Proteins 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 캐패시터 형성방법에 관한 것으로, 트랜지스터가 형성된 반도체기판 상에 불순물확산영역과 연결되는 접속구가 형성된 제 1절연층을 형성하는 공정과, 제 1절연층의 일부를 노출시키고 접속구를 채우는 제 1다결정실리콘층 및 제 2절연층을 순차적으로 형성하는 공정과, 제 1다결정실리콘층 및 제 2절연층의 측면에 측벽 형상의 제 2다결정실리콘층을 형성하는 공정과, 제 2다결정실리콘층 측면에 측벽 형상의 버퍼층을 형성하는 공정과, 버퍼층을 마스크로 제 2절연층을 제거한 후에 버퍼층을 제거하는 공정을 구비한 것이 특징이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor, the method comprising: forming a first insulating layer having a connection hole connected to an impurity diffusion region on a semiconductor substrate on which a transistor is formed; and a first opening exposing a portion of the first insulating layer and filling the connection hole. Forming a polysilicon layer and a second insulating layer in sequence, forming a sidewall-shaped second polycrystalline silicon layer on the side surfaces of the first polycrystalline silicon layer and the second insulating layer, and at the side of the second polycrystalline silicon layer And a step of forming a sidewall-shaped buffer layer and a step of removing the buffer layer after removing the second insulating layer using the buffer layer as a mask.
따라서, 본 발명에서는 적층구조의 캐패시터에서 스토리지전극으로 사용될 다결정실리콘층 및 측벽 내부에 형성된 절연층 제거 시, 절연층 측면에 상기 절연층과 다른 식각선택성을 갖는 물질을 적층함으로써, 습식액이 침투하여 하부의 층간절연층이 노출되는 것을 방지한다. 따라서, 비트라인과 캐패시터의 플레이트전극이 쇼트되는 것을 방지가능한 잇점이 있다.Accordingly, in the present invention, when a polysilicon layer to be used as a storage electrode and an insulating layer formed inside the sidewall are removed from the capacitor of the stacked structure, the wet liquid penetrates by stacking a material having an etching selectivity different from that of the insulating layer on the side of the insulating layer. The lower interlayer insulating layer is prevented from being exposed. Therefore, there is an advantage in that the bit electrodes and the plate electrodes of the capacitors can be prevented from shorting.
Description
본 발명은 캐패시터 형성방법에 관한 것으로, 특히, 메모리 셀(memory cell)에 있어서 트랜지스터(transistor)의 소오스나 드레인전극에 연결되는 적층구조의 캐패시터의 스토리지전극 제조공정 중에 절연층과 포토레지스트와의 접촉불량으로 인해 그 틈새 사이로 습식액이 침투됨으로써 발생되는 하부의 층간절연층 손실을 방지하기에 적당한 캐패시터 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor, and in particular, a contact between an insulating layer and a photoresist during a manufacturing process of a storage electrode of a stacked capacitor connected to a source or a drain electrode of a transistor in a memory cell. The present invention relates to a method for forming a capacitor suitable for preventing the loss of the lower interlayer insulating layer caused by penetration of a wet liquid between the gaps due to a defect.
반도체 소자가 고집적화됨에 따라 메모리 셀에 있어서도 캐패시터가 일정한 축전용량을 갖도록 축전용량을 증가시키기 위한 많은 연구가 진행되고 있다.As semiconductor devices are highly integrated, many studies have been conducted to increase the capacitance so that a capacitor has a constant capacitance in a memory cell.
이러한 결과로 축전용량을 증가시키기 위해서 캐패시터의 유전층의 유전율을 증대시키거나 축전전극의 구조를 적층(stack)하거나 또는 트렌치(trench)를 이용하여 3차원 구조로 형성하여 축전전극의 표면적을 개선하는 연구가 진행된다.As a result, in order to increase the capacitance, a study of improving the dielectric constant of the capacitor dielectric layer, stacking the structure of the storage electrode, or forming a three-dimensional structure using a trench to improve the surface area of the storage electrode Proceeds.
그리고 상기 3차원 구조를 갖는 캐패시터 중 적층 구조를 갖는 것은 제조공정이 용이하고 대량 생산성에 적합한 구조로서 축전 용량을 증대시키는 동시에 알파입자에 의한 전하 정보 혼란에 대하여 면역성을 가질 수 있으므로 유리하다.In addition, the laminated structure among the capacitors having the three-dimensional structure is advantageous in that the manufacturing process is easy and suitable for mass productivity, which increases the storage capacity and can be immune to charge information disturbance caused by alpha particles.
이러한 적층 구조 캐패시터는 스토리지전극의 형태에 따라 2중 적층구조, 핀(fin)구조 또는 크라운(crown)구조 등으로 구별된다.Such stacked structure capacitors are classified into a double stacked structure, a fin structure, or a crown structure according to the shape of the storage electrode.
도 1a 내지 도 1e 는 종래기술에 따른 캐패시터 형성을 위한 공정도이다.1A to 1E are process diagrams for forming a capacitor according to the prior art.
도 1a 와 같이, 도면에 도시되지 않았지만, 반도체기판 상에 소자의 활성영역과 필드영역을 한정하는 필드산화층을 형성한 후, 소자의 활성영역 상에 게이트산화층을 개재시키어 비트라인(bit line)을 형성하며, 이 비트라인 양측의 활성영역에 소오스/드레인(source/drain)영역으로 이용되는 불순물확산영역을 형성함으로써 트랜지스터(transistor)를 형성한다.Although not shown in FIG. 1A, as shown in FIG. 1A, a field oxide layer defining an active region and a field region of an element is formed on a semiconductor substrate, and then a bit line is formed by interposing a gate oxide layer on the active region of the element. A transistor is formed by forming an impurity diffusion region used as a source / drain region in the active regions on both sides of the bit line.
이어서, 트랜지스터가 형성된 기판(100)에 화학기상증착(Chemical Vapor Deposition: 이하 CVD라 칭함) 방법으로 산화실리콘을 충분한 두께로 증착하여 층간절연층(102)을 형성한 후, 열처리 또는 화학-기계적 연마(Chemical-Mechanical Polishing)방법을 적용하여 층간절연층의 표면을 평탄화한다.Subsequently, silicon oxide is deposited to a sufficient thickness by chemical vapor deposition (CVD) on the substrate 100 on which the transistor is formed to form an interlayer insulating layer 102, and then subjected to heat treatment or chemical-mechanical polishing. (Chemical-Mechanical Polishing) is applied to planarize the surface of the interlayer insulating layer.
그리고 층간절연층(102) 상에 불순물확산영역(도면에 조시되지 않음)을 노출시키는 접속구(contact hole)(H1)를 형성한다.A contact hole H1 is formed on the interlayer insulating layer 102 to expose the impurity diffusion region (not shown in the figure).
도 1b 와 같이, 층간절연층(102) 상에 접속구(H1)를 덮도록 다결정실리콘층(104)을 증착한 후, 그 상부에 절연층(oxide)(106) 및 HSG(Hemi-Spherical Glass)(108)를 순차적으로 적층한다.As illustrated in FIG. 1B, after the polysilicon layer 104 is deposited on the interlayer insulating layer 102 to cover the connection hole H1, an insulating layer 106 and an HSG (Hemi-Spherical Glass) are deposited thereon. 108 is sequentially stacked.
다음에, HSG(108) 상에 포토레지스트를 도포한 후, 노광 및 현상하여 접속구(H1)와 대응되는 제 1다결정실리콘층(104)과 절연층(106)과 HSG(108)의 일정부위를 잔류시키고 나머지 부분을 제거하여 제 1마스크패턴(110)을 형성한다. 상기에서, 층간절연층(102)과 절연층(106)은 모두 옥사이드 성분으로 동일물질로 형성된다.Next, after the photoresist is applied on the HSG 108, the photoresist is exposed and developed to form a predetermined portion of the first polysilicon layer 104, the insulating layer 106, and the HSG 108 corresponding to the connector H1. The first mask pattern 110 is formed by remaining and removing the remaining portion. In the above, the interlayer insulating layer 102 and the insulating layer 106 are both formed of the same material as an oxide component.
이어서, 제 1마스크패턴(110)을 마스크로 제 1다결정실리콘층(104)과 절연층(106)과 HSG(108)를 제거하여 층간절연층(102)을 노출시킨다.Subsequently, the first polycrystalline silicon layer 104, the insulating layer 106, and the HSG 108 are removed using the first mask pattern 110 as a mask to expose the interlayer insulating layer 102.
이 때, HSG(108)는 포토레지스트 표면에 굴곡이 형성되어 토포로지(topology)가 저하됨으로 인해 노광 시 빛이 반사되는 것을 방지하기 위한 반사방지층으로 사용된다.In this case, the HSG 108 is used as an anti-reflection layer to prevent light from being reflected upon exposure due to the formation of a bend on the surface of the photoresist to decrease the topology.
도 1c 와 같이, 제 1마스크패턴(110)을 제거한다.As shown in FIG. 1C, the first mask pattern 110 is removed.
그리고 층간절연층(102)상에 HSG(108)를 덮도록 제 2다결정실리콘층을 형성한 후, 에치백하여 잔류된 제 1다결정실리콘층(104) 및 절연층(106)의 측면에 측벽(112)을 형성한다. 이 때, 잔류된 HSG(108)는 제 2다결정실리콘층을 에치백하는 과정에서 함께 제거가 된다.After the second polysilicon layer is formed on the interlayer insulating layer 102 to cover the HSG 108, the sidewalls of the first polycrystalline silicon layer 104 and the insulating layer 106 are etched back to form sidewalls ( 112). At this time, the remaining HSG 108 is removed together in the process of etching back the second polysilicon layer.
이어서, 층간절연층(102) 상에 포토레지스트를 도포한 후, 노광 및 현상하여 측벽(112)을 덮는 제 2마스크패턴(114)을 형성한다.Subsequently, a photoresist is applied on the interlayer insulating layer 102, and then exposed and developed to form a second mask pattern 114 covering the sidewall 112.
그리고 제 2마스크패턴(114)을 마스크로 잔류된 절연층(106)을 건식식각 방법으로 제거한 후, 습식식각 방법으로 제거하여서 잔류된 제 1다결정실리콘층(112) 및 측벽(112)의 일부위를 노출시킨다.After the insulating layer 106 remaining as the mask of the second mask pattern 114 is removed by a dry etching method, a portion of the first polycrystalline silicon layer 112 and the sidewall 112 remaining by removing the insulating layer 106 by a wet etching method is removed. Expose
이 때, 포토레지스트를 도포하여 노광 및 현상공정을 거쳐 제 2마스크패턴(114) 형성 시에 발생되는 스컴(scum)은 상기 건식식각 시에 절연층(106)과 함께 제거되며, 또한, 건식식각 방법만으로는 접속구(H1)에 채우진 절연층(108)이 모두 제거가 되지 않기 때문에 별도로 습식액인 HF 또는 BOE 용액 등을 이용하여 습식식각 공정을 거친다.At this time, the scum generated when the second mask pattern 114 is formed by applying a photoresist and undergoing an exposure and development process is removed together with the insulating layer 106 during the dry etching, and further, dry etching. Since only the method does not remove all of the insulating layer 108 filled in the connector (H1), the wet etching process is performed using a separate HF or BOE solution, which is a wet solution.
도 1d 와 같이, 제 2마스크패턴(114)을 제거하여 잔류된 제 1다결정실리콘층(104)과 측벽(112)으로 이루어진 스토리지전극(116)을 완전히 노출시킨다.As shown in FIG. 1D, the second mask pattern 114 is removed to completely expose the storage electrode 116 including the remaining first polysilicon layer 104 and the sidewalls 112.
도 1e 와 같이, 층간절연층(102)상에 스토리지전극(116)을 덮도록 유전층(118)을 적층하여 패터닝한다.As shown in FIG. 1E, the dielectric layer 118 is stacked and patterned on the interlayer insulating layer 102 to cover the storage electrode 116.
그리고 층간절연층(102) 상에 잔류된 유전층(118)을 덮도록 제 3다결정실리콘층을 형성하여 플레이트전극(120)을 형성함으로써 캐패시터 형성공정을 완료한다.Then, the third polycrystalline silicon layer is formed to cover the dielectric layer 118 remaining on the interlayer insulating layer 102 to form the plate electrode 120 to complete the capacitor forming process.
그러나, 종래의 기술에서는 스토리지전극 형성을 위한 제 1다결정실리콘층 및 측벽 내부의 절연층을 식각할 시, 제 2마스크패턴과 측벽형상의 다결정실리콘층과의 접촉불량에 의해 그 틈새로 습식액이 침투되어 상기 절연층과 동일성분인 층간절연층이 손실됨으로써 비트라인이 노출되었다. 따라서, 이후의 공정에서 비트라인과 플레이트전극이 쇼트되어 불량을 유발하는 문제점이 발생되었다.However, in the related art, when the first polysilicon layer and the insulating layer inside the sidewall are etched to form the storage electrode, the wet liquid is formed in the gap due to the poor contact between the second mask pattern and the sidewall polycrystalline silicon layer. The bit line was exposed by the penetration of the interlayer insulating layer which is the same as the insulating layer. Therefore, in the subsequent process, the bit line and the plate electrode are short-circuited to cause a problem.
따라서, 본 발명은 상기의 문제점을 해결하고자, 적층구조의 캐패시터의 스토리지전극으로 사용될 다결정실리콘층 내부에 형성된 절연층을 제거할 시, 이 다결정실리콘층의 일부를 덮는 포토레지스트와의 접촉불량으로 인해 그 틈새 사이로 습식액이 침투됨으로써 발생되는 하부의 층간절연층의 손실을 방지가능한 캐패시터 형성방법을 제공하는 데 그 목적이 있다.Therefore, in order to solve the above problem, when the insulating layer formed inside the polysilicon layer to be used as the storage electrode of the capacitor of the laminated structure is removed, due to a poor contact with the photoresist covering a part of the polysilicon layer. It is an object of the present invention to provide a method for forming a capacitor capable of preventing the loss of an interlayer insulating layer caused by penetration of a wet liquid between the gaps.
상기의 목적을 달성하고자, 본 발명의 캐패시터 형성방법은 트랜지스터가 형성된 반도체기판 상에 불순물확산영역과 연결되는 접속구가 형성된 제 1절연층을 형성하는 공정과, 제 1절연층의 일부를 노출시키고 접속구를 채우는 제 1다결정실리콘층 및 제 2절연층을 순차적으로 형성하는 공정과, 제 1다결정실리콘층 및 제 2절연층의 측면에 측벽 형상의 제 2다결정실리콘층을 형성하는 공정과, 제 2다결정실리콘층 측면에 측벽 형상의 버퍼층을 형성하는 공정과, 버퍼층을 마스크로 제 2절연층을 제거한 후에 버퍼층을 제거하는 공정을 구비한 것이 특징으로 한다.In order to achieve the above object, the method of forming a capacitor of the present invention comprises the steps of forming a first insulating layer having a connection hole connected to an impurity diffusion region on a semiconductor substrate on which a transistor is formed, exposing a portion of the first insulating layer and Sequentially forming a first polycrystalline silicon layer and a second insulating layer filling the gap; forming a second polycrystalline silicon layer having sidewalls on the side surfaces of the first polycrystalline silicon layer and the second insulating layer; and a second polycrystalline And a step of forming a sidewall-shaped buffer layer on the side of the silicon layer, and a step of removing the buffer layer after removing the second insulating layer using the buffer layer as a mask.
도 1a 내지 도 1e 는 종래기술에 따른 캐패시터 형성을 위한 공정도이고,1a to 1e is a process chart for forming a capacitor according to the prior art,
도 2a 내지 도 2e 는 본 발명에 따른 캐패시터 형성을 위한 공정도이다.2A to 2E are process diagrams for forming a capacitor according to the present invention.
*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100, 200. 트랜지스터가 형성된 기판100, 200. Substrate with formed transistor
102, 202. 층간절연층102, 202. Interlayer insulating layer
104, 204, 112, 212, 120, 220. 다결정실리콘층104, 204, 112, 212, 120, 220. Polycrystalline silicon layer
106, 206. 절연층106, 206. Insulation layer
108, 208. HSG108, 208.HSG
110, 210, 114, 214. 마스크패턴110, 210, 114, 214. Mask Pattern
116, 216. 스토리지전극116, 216. Storage electrode
118, 218. 유전물질118, 218. Genetic material
213. 버퍼층213.Buffer layer
120, 220. 플레이트전극120, 220. Plate electrode
이하, 첨부된 도면을 참조하여 본 발명을 설명하겠다.Hereinafter, the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2e 는 본 발명에 따른 캐패시터 형성을 위한 공정도이다.2A to 2E are process diagrams for forming a capacitor according to the present invention.
도 2a 와 같이, 상술한 종래기술과 마찬가지 방법을 이용하여 트랜지스터가 형성된 기판(200)에 충분한 두꼐로 옥사이드 성분인 층간절연층(202)을 적층한 후, 트랜지스터의 불순물확산영역 (도면에 도시되지 않음) 을 노출시키기 위한 접속구(H2)를 형성한다.As shown in FIG. 2A, after the interlayer insulating layer 202 of an oxide component is sufficiently stacked on the substrate 200 on which the transistor is formed by using the same method as the above-described conventional technique, the impurity diffusion region of the transistor (not shown in the drawing). To form a connector H2 for exposing).
도 2b 와 같이, 층간절연층(202) 상에 접속구(H2)를 채우도록 제 1다결정실리콘층(204)을 형성한 후, 그 상부에 절연층(206) 및 HSG(208)를 순차적으로 적층한다. 이 때, 절연층(206)은 옥사이드 성분으로, 층간절연층(202)과 동일물질로 형성된다.As shown in FIG. 2B, after forming the first polysilicon layer 204 on the interlayer insulating layer 202 to fill the connection hole H2, the insulating layer 206 and the HSG 208 are sequentially stacked on the first polycrystalline silicon layer 204. do. At this time, the insulating layer 206 is formed of an oxide component and the same material as the interlayer insulating layer 202.
다음에, HSG(208) 상에 포토레지스트를 도포한 후, 노광 및 현상하여 접속구(H2)와 대응되는 제 1다결정실리콘층(204) 및 절연층(206) 및 HSG(208)의 일정부위를 덮는 제 1마스크패턴(110)을 형성한다.Next, after the photoresist is applied on the HSG 208, the photoresist is exposed and developed to provide a portion of the first polycrystalline silicon layer 204 and the insulating layer 206 and the HSG 208 corresponding to the connector H2. A covering first mask pattern 110 is formed.
이어서, 제 1마스크패턴(210)을 마스크로 제 1다결정실리콘층(204)과 절연층(206)과 HSG(208)을 제거하여 층간절연층(202)을 노출시킨다.Subsequently, the interlayer insulating layer 202 is exposed by removing the first polysilicon layer 204, the insulating layer 206, and the HSG 208 using the first mask pattern 210 as a mask.
도 2C 와 같이, 제 1마스크패턴(210)을 제거한다.As shown in FIG. 2C, the first mask pattern 210 is removed.
그리고 층간절연층(202)상에 HSG(208)를 덮도록 제 2다결정실리콘층을 형성한 후, 에치백하여 잔류된 제 1다결정실리콘층(204) 및 절연층(206)의 측면에 측벽(212)을 형성한다.After the second polysilicon layer is formed on the interlayer insulating layer 202 to cover the HSG 208, the sidewalls of the first polycrystalline silicon layer 204 and the insulating layer 206 remaining after being etched back are formed. 212).
이 때, HSG(208)은 제 2다결정실리콘층을 에치백하는 과정에서 함꼐 제거가 된다.At this time, the HSG 208 is removed together in the process of etching back the second polycrystalline silicon layer.
다음에, 층간절연층(202) 상에 측벽(212)을 포함한 절연층(206)을 덮도록 질화층(213)을 적층한다. 여기에서, 질화층(213)은 측벽(212)을 보호하여 하부의 층간절연층(202)이 노출되는 것을 보호하는 버퍼층 역할을 하며, 증착되는 질화층의 두께는 100 ∼ 500 Å 정도가 적당하다.Next, the nitride layer 213 is laminated on the interlayer insulating layer 202 so as to cover the insulating layer 206 including the sidewalls 212. Here, the nitride layer 213 serves as a buffer layer to protect the side wall 212 to protect the lower interlayer insulating layer 202 is exposed, the thickness of the deposited nitride layer is suitable to about 100 ~ 500 Å .
이어서, 질화층(202) 상에 포토레지스트를 도포한 후, 노광 및 현상하여 측벽(212) 및 측벽(212) 및 측벽 사이의 질화층은 덮고, 절연층(206)과 대응되는 부위는 노출시키는 제 2마스크패턴(214)을 형성한다.Subsequently, after photoresist is applied on the nitride layer 202, the photoresist is exposed and developed to cover the sidewalls 212 and the nitride layer between the sidewalls 212 and the sidewalls, and to expose portions corresponding to the insulating layer 206. The second mask pattern 214 is formed.
다음에, 건식식각 및 습식식각 방법으로 제 2마스크패턴(214)을 마스크로 질화층 및 잔류된 절연층(206)을 제거하여 잔류된 제 1다결정실리콘층(204) 및 측벽(212)의 일부위를 노출시킨다.Next, a part of the first polycrystalline silicon layer 204 and the sidewall 212 remaining by removing the nitride layer and the remaining insulating layer 206 using the second mask pattern 214 as a mask by dry etching and wet etching methods. Expose the stomach.
이 때, 제 2마스크패턴(214) 형성 시에 발생되는 스컴은 상기 건식식각 시에 함께 제거되며, 또한, 건식식각 방법만으로는 접속구(H2)에 채우진 절연층(208)이 모두 제거가 되지 않기 때문에 이 부위의 절연층을 제거하기 위해, 종래기술과 마찬가지로, 별도로 습식액인 HF 또는 BOE 용액 등을 이용하여 습식식각 공정을 거친다.At this time, the scum generated at the time of forming the second mask pattern 214 is removed together during the dry etching, and since only the dry etching method does not remove all of the insulating layer 208 filled in the connector H2. In order to remove the insulating layer at this site, a wet etching process is performed separately using HF or BOE solution, which is a wet liquid, as in the prior art.
상기에서, 질화층(213)은 측벽(212) 및 측벽 사이를 애워싸서 HF 또는 BOE 용액이 층간절연층(202)으로 침투되지 않도록 보호한다. 따라서, 절연층(206) 식각 시, 이 절연층(206)과 동일물질인 층간절연층(202)이 노출될 우려가 없다.In the above, the nitride layer 213 surrounds the side wall 212 and the side wall to protect the HF or BOE solution from penetrating into the interlayer insulating layer 202. Accordingly, when the insulating layer 206 is etched, the interlayer insulating layer 202, which is the same material as the insulating layer 206, may not be exposed.
도 2d 와 같이, 제 2마스크패턴(214)을 제거한 후, 측벽(212) 및 측벽 사이에 잔류된 질화층(213)을 제거하여서 잔류된 제 1다결정실리콘층(212) 및 측벽(212)으로 이루어진 스토리지전극(216)을 노출시킨다.As shown in FIG. 2D, after removing the second mask pattern 214, the nitride layer 213 remaining between the sidewall 212 and the sidewalls is removed to the remaining first polysilicon layer 212 and the sidewall 212. Exposed storage electrode 216 is exposed.
도 2e 와 같이, 층간절연층(202)상에 스토리지전극(216)이 형성된 부위를 덮도록 유전층(218)을 패터닝한 후, 층간절연층(202) 상에 유전층(218)을 덮도록 제 3다결정실리콘층을 증착하여 플레이트전극(120)을 형성한다.As shown in FIG. 2E, after the dielectric layer 218 is patterned to cover a portion where the storage electrode 216 is formed on the interlayer insulating layer 202, the third dielectric layer 218 is covered on the interlayer insulating layer 202. The polysilicon layer is deposited to form the plate electrode 120.
상술한 바와 같이, 본 발명에서는 적층구조의 캐패시터에서 스토리지전극으로 사용될 다결정실리콘층 및 측벽 내부에 형성된 절연층 제거 시, 측벽 측면에 상기 절연층과 다른 식각선택성을 갖는 물질을 적층하여 상기 측벽을 보호함으로써, 습식액이 마스크패턴과 상기 다결정실리콘층 사이에 틈새에 침투되어 하부의 층간절연층이 노출되는 것을 방지할 수 있다. 따라서, 비트라인과 캐패시터의 플레이트전극이 쇼트되는 것을 방지가능한 잇점이 있다.As described above, in the present invention, when the polysilicon layer to be used as the storage electrode and the insulating layer formed inside the sidewall are removed, the sidewall is protected by stacking a material having an etching selectivity different from that of the insulating layer. As a result, the wet liquid can be prevented from penetrating into the gap between the mask pattern and the polysilicon layer to expose the lower interlayer insulating layer. Therefore, there is an advantage in that the bit electrodes and the plate electrodes of the capacitors can be prevented from shorting.
Claims (5)
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