KR19990025164A - Electrostatic thermal bonding method of semiconductor substrate - Google Patents
Electrostatic thermal bonding method of semiconductor substrate Download PDFInfo
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- KR19990025164A KR19990025164A KR1019970046678A KR19970046678A KR19990025164A KR 19990025164 A KR19990025164 A KR 19990025164A KR 1019970046678 A KR1019970046678 A KR 1019970046678A KR 19970046678 A KR19970046678 A KR 19970046678A KR 19990025164 A KR19990025164 A KR 19990025164A
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- semiconductor substrate
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- oxide
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- 239000000758 substrate Substances 0.000 title claims abstract description 81
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000000203 mixture Substances 0.000 claims abstract description 30
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 17
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 17
- 238000004140 cleaning Methods 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 15
- 230000008021 deposition Effects 0.000 claims abstract description 12
- 238000005566 electron beam evaporation Methods 0.000 claims abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 239000011521 glass Substances 0.000 claims description 12
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims description 9
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 4
- 239000000395 magnesium oxide Substances 0.000 claims description 4
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 claims description 2
- ODINCKMPIJJUCX-UHFFFAOYSA-N Calcium oxide Chemical compound [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 claims description 2
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 claims description 2
- XUCJHNOBJLKZNU-UHFFFAOYSA-M dilithium;hydroxide Chemical group [Li+].[Li+].[OH-] XUCJHNOBJLKZNU-UHFFFAOYSA-M 0.000 claims description 2
- FZFYOUJTOSBFPQ-UHFFFAOYSA-M dipotassium;hydroxide Chemical compound [OH-].[K+].[K+] FZFYOUJTOSBFPQ-UHFFFAOYSA-M 0.000 claims description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 239000010409 thin film Substances 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000001934 delay Effects 0.000 abstract 1
- 238000010894 electron beam technology Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- 238000009461 vacuum packaging Methods 0.000 description 2
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 1
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910001416 lithium ion Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Photovoltaic Devices (AREA)
Abstract
본 발명은 반도체 기판의 정전 열 접합방법에 관한 것으로, 종래 반도체 기판의 정전 열 접합방법은 높은 온도와 높은 전압이 요구되어 제조비용이 증가할 뿐만 아니라 접합 강도가 낮고, 기판에 코닝 #7740유리를 스퍼터를 사용하여 증착함으로써, 기판에 손상을 줄 뿐만 아니라 공정시간도 지연되는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 반도체 기판을 세척하는 제 1세척단계와; 세척된 반도체 기판에 실리콘 산화물과 금속 산화물을 혼합한 혼합물을 증착하는 증착단계와; 상기 혼합물이 증착된 반도체 기판을 세척하는 제 2세척단계와; 상기 혼합물이 증착된 반도체 기판과 일반 반도체 기판에 열과 전압을 인가하여 접합시키는 접합단계로 이루어져 전자선 증착법으로 금속 산화물과 실리콘 산화물의 혼합물을 반도체 기판 위에 증착하여 두 반도체 기판의 접합시 중간층으로 이용함으로써, 공정시간을 단축하고, 낮은 온도 및 전압에서 공정하여 제조비용을 절감하며, 소자의 응용시 적당한 강한 접합강도를 얻을 수 있는 효과가 있다.The present invention relates to an electrostatic thermal bonding method for a semiconductor substrate. In the conventional electrostatic thermal bonding method for a semiconductor substrate, a high temperature and a high voltage are required, resulting in an increase in manufacturing cost and a low junction strength. Deposition by using a sputter not only damages the substrate but also delays the process time. SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, A deposition step of depositing a mixture of silicon oxide and metal oxide on the cleaned semiconductor substrate; A second cleaning step of cleaning the semiconductor substrate on which the mixture is deposited; And a bonding step of applying heat and voltage to the semiconductor substrate on which the mixture is deposited and the general semiconductor substrate to bond the metal oxide and the silicon oxide onto the semiconductor substrate by electron beam evaporation, The process time is shortened, the process is performed at a low temperature and a voltage to reduce the manufacturing cost, and a strong bonding strength suitable for application of the device can be obtained.
Description
본 발명은 반도체 기판의 정전 열 접합방법에 관한 것으로, 특히 실리콘 기판과 실리콘 기판의 접합시 또는 유리 기판과 실리콘 기판의 접합시 접합할 양 기판간에 실리콘 및 금속산화물을 중간층으로 사용하여 정전 열 접합을 실시하는데 있어, 저전압, 저온에서도 강한 접합이 이루어지도록 한 반도체 기판의 정전 열 접합방법에 관한 것이다.The present invention relates to an electrostatic thermal bonding method for a semiconductor substrate, and more particularly, to an electrostatic thermal bonding method using silicon and a metal oxide as an intermediate layer between a silicon substrate and a silicon substrate or between a glass substrate and a silicon substrate, The present invention relates to an electrostatic thermal bonding method for a semiconductor substrate in which strong bonding is performed even at a low voltage and a low temperature.
일반적으로, 전계 방출 표시소자(field emission display 이하, FED)는 두 개의 기판을 특별한 프릿을 사용해서 진공실장을 하고 있으며, 이러한 프릿을 진공 실장을 이용할 부분에 놓고, 기판을 450~600℃의 온도에서 가열한다. FED의 특성이 효과적으로 나타나기 위해서는 10-6Torr이상의 고진공이 요구되나, 이러한 프릿은 고온에서 사용되어 소자의 동작 수명을 단축시키고, 진공도 또한 떨어뜨리는 문제점이 있었다. 이러한 문제점을 해결하기 위한 방편으로, 최근 정전 열 접합방법이 시도되고 있으나 소자의 유지에 충분한 접합강도를 얻는 것이 용이하지 않은 것이 문제점으로 대두되고 있다.In general, a field emission display (FED) is a vacuum packaging method using two substrates with a special frit. The frit is placed in a vacuum packaging area, and the substrate is heated to a temperature of 450 to 600 ° C Lt; / RTI > In order to obtain the characteristics of the FED effectively, a high vacuum of 10 -6 Torr or more is required. However, such a frit is used at a high temperature, shortening the operating life of the device and lowering the degree of vacuum. Recently, electrostatic thermal bonding methods have been attempted as means for solving these problems, but it has become a problem that it is not easy to obtain a sufficient bonding strength to hold the device.
종래 애노딕 접합(anodic bonding) 또는 필드-어시스티드 접합(field-assisted bonding)이라고 불리는 정전 열 접합방법은 1969년 피. 알. 말로이(P. R. MALLOY)사의 다니엘 아이 포머란츠(DANIEL I. FORMARANTZ)에 의해 300~600℃의 온도와 200~2000V의 전압을 실리콘 기판과 유리 기판에 인가하여 두 기판을 접합시킴으로써 최초로 세상에 알려지게 되었다. 이러한 기술은 직접 접합방법과는 달리 낮은 온도에서 친수화를 위한 화학 약품의 처리가 없이도 접합이 가능하다는 이유로 압력센서, 태양전지, 마이크로 머시닝, 실리콘 온 인슐레이터(SOI) 등 여러 분야에서 응용되고 있다.An electrostatic thermal bonding method, conventionally referred to as anodic bonding or field-assisted bonding, egg. Was first known to the world by applying a temperature of 300 to 600 DEG C and a voltage of 200 to 2000 V to a silicon substrate and a glass substrate by DANIEL I. FORMARANTZ of PR MALLOY Co., . Unlike the direct bonding method, these techniques are applied to various fields such as pressure sensors, solar cells, micromachining, and silicon on insulator (SOI) because bonding can be performed without chemical treatment for hydrophilization at low temperatures.
이와 같은 반도체 기판의 정전 열 접합방법은 두 기판사이에 중간층으로 코닝 #7740이라는 유리박막을 사용하고, 두 기판에 높은 전압과 처리 온도의 열을 인가하여 두 기판 사이의 정전력을 이용하여 영구적인 접합을 실현하였다.In the electrostatic thermal bonding method of the semiconductor substrate, a glass thin film of Corning # 7740 is used as an intermediate layer between two substrates, and a high voltage and a heat of a processing temperature are applied to the two substrates, Junction.
이때 코닝 #7740은 주로 나트륨이온인 알카리이온을 이동시켜 접합이 가능하게 하였다.At this time, Corning # 7740 made possible the bonding by moving the alkali ion mainly as the sodium ion.
그러나, 상기한 바와 같이 종래 반도체 기판의 정전 열 접합방법은 높은 온도와 높은 전압이 요구되어 제조비용이 증가할 뿐만 아니라 접합 강도가 낮고, 기판에 코닝 #7740유리를 스퍼터를 사용하여 증착함으로써, 기판에 손상을 줄 뿐만 아니라 공정시간도 지연되는 문제점이 있었다.However, as described above, the electrostatic thermal bonding method of the conventional semiconductor substrate requires a high temperature and a high voltage to increase the manufacturing cost, and the bonding strength is low. By depositing Corning # 7740 glass on the substrate using a sputtering method, And the process time is also delayed.
이와 같은 문제점을 감안한 본 발명은 전자선 증착기를 이용하여 낮은 온도 및 전압하에서도 접합에 요구되는 이온의 이동이 가능한 물질을 중간층으로 사용함으로써 공정시간을 단축하고, 제조비용을 낮추며, 접합 강도를 증가시키는 반도체 기판의 정전 열 접합방법을 제공함에 그 목적이 있다.According to the present invention, there is provided a method of manufacturing a semiconductor device, which uses an electron beam evaporator as a middle layer capable of moving an ion required for bonding even under low temperature and voltage, thereby shortening a process time, lowering a manufacturing cost, And an object of the present invention is to provide a method of electrostatic thermal bonding of a semiconductor substrate.
도1은 본 발명의 방법을 수행하기 위하여 실리콘 기판과 실리콘 산화물 및 금속산화물의 혼합물이 증착된 실리콘 기판을 실장한 상태를 나타낸 구성설명도.BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a structural explanatory view showing a silicon substrate on which a silicon substrate and a mixture of silicon oxide and metal oxide are deposited in order to carry out the method of the present invention. FIG.
도2는 본 발명의 방법을 수행하기 위하여 ITO코팅 유리 기판과 실리콘 산화물 및 금속산화물의 혼합물이 증착된 실리콘 기판을 정전열 접합장치에 실장한 구조도.FIG. 2 is a structural view of a silicon substrate on which an ITO-coated glass substrate and a mixture of silicon oxide and metal oxide are deposited in order to carry out the method of the present invention. FIG.
도3은 도2의 방법에 의해 접합된 ITO코팅 유리 기판과 실리콘 산화물 및 금속산화물의 혼합물이 증착된 실리콘 기판의 단면 주사 전자현미경 사진.3 is a cross-sectional scanning electron micrograph of a silicon substrate deposited with a mixture of an ITO-coated glass substrate and a silicon oxide and a metal oxide bonded by the method of FIG.
***도면의 주요 부분에 대한 부호의 설명***DESCRIPTION OF THE REFERENCE SYMBOLS
1:전원공급 및 기록부 2:온도조절부1: Power supply and recording unit 2: Temperature control unit
3:가열부3:
상기와 같은 목적은 반도체 기판을 세척하는 제 1세척단계와; 세척된 반도체 기판에 실리콘 산화물과 금속 산화물을 혼합한 혼합물을 증착하는 증착단계와; 상기 혼합물이 증착된 반도체 기판을 세척하는 제 2세척단계와; 상기 혼합물이 증착된 반도체 기판과 일반 반도체 기판에 열과 전압을 인가하여 접합시키는 접합단계로 구성하여 금속이온이 낮은 전압 하에서 이동도가 우수함을 이용하여 정전력을 발생시키고, 전자선 증착법을 이용하여 공정시간을 단축시킴으로써 달성되는 것으로 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above and other objects can be accomplished by the provision of a cleaning method comprising: a first cleaning step of cleaning a semiconductor substrate; A deposition step of depositing a mixture of silicon oxide and metal oxide on the cleaned semiconductor substrate; A second cleaning step of cleaning the semiconductor substrate on which the mixture is deposited; And a bonding step of applying heat and voltage to the semiconductor substrate and the general semiconductor substrate on which the mixture is deposited to generate electrostatic force using metal ions having excellent mobility under a low voltage, The present invention will now be described in detail with reference to the accompanying drawings.
본 발명은 반도체 기판을 세척하는 제 1세척단계와; 세척된 반도체 기판에 실리콘 산화물과 금속 산화물을 혼합한 혼합물을 증착하는 증착단계와; 상기 혼합물이 증착된 반도체 기판을 세척하는 제 2세척단계와; 상기 혼합물이 증착된 반도체 기판과 일반 반도체 기판에 열과 전압을 인가하여 접합시키는 접합단계로 이루어 진다.The present invention relates to a semiconductor device comprising: a first cleaning step of cleaning a semiconductor substrate; A deposition step of depositing a mixture of silicon oxide and metal oxide on the cleaned semiconductor substrate; A second cleaning step of cleaning the semiconductor substrate on which the mixture is deposited; And a bonding step of applying heat and voltage to the semiconductor substrate on which the mixture is deposited and the general semiconductor substrate.
이하, 상기와 같이 구성된 본 발명을 좀 더 상세히 설명한다.Hereinafter, the present invention will be described in more detail.
먼저, 반도체 기판을 아세톤, 메탄올 및 탈 이온수(D.I. WATER)로 세척한 후에 전자선 증착기에 세팅한다.First, the semiconductor substrate is washed with acetone, methanol and deionized water (D.I. WATER), and then set in an electron beam evaporator.
그 다음, 전자선 증착기의 증착 소스 물질로 실리콘 산화물과 금속 산화물을 혼합하여 사용한다. 이때 금속 산화물의 혼합비는 실리콘 산화물의 0.1~10WT%를 사용하며, 금속 산화물은 리튬 옥사이드(Li2O), 베릴륨 옥사이드(BeO), 보론 옥사이드(B2O3), 마그네슘 옥사이드(MgO), 알루미늄 옥사이드(Al2O3), 칼륨 옥사이드(K2O), 칼슘 옥사이드(CaO)중 하나를 사용한다. 이와 같이 실리콘 산화물과 금속 산화물의 혼합물을 상기 세척된 반도체 기판의 상부에 증착한다. 이때, 증착 분위기는 130~300℃의 기판온도와 2.0×10-5Torr의 진공 하에서 증착하며, 증착속도는 1초에 1~100씩 증착하여 종래의 0.5보다 증가시켰다. 증착 높이는 0.5~3
그 다음, 상기 혼합물이 증착된 반도체 기판을 아세톤, 메탄올, 탈 이온수에 세척한다.Then, the semiconductor substrate on which the mixture is deposited is washed with acetone, methanol, and deionized water.
그 다음, 상기 혼합물이 증착된 반도체 기판과 순수한 반도체 기판을 정전 열 접합장치에 실장하고, 10~500℃의 기판온도에서 10~400V의 전압을 5~60분간 인가하여 정전 열 접합을 실시하게 된다.Then, the semiconductor substrate on which the mixture is deposited and the pure semiconductor substrate are mounted in an electrothermal bonding apparatus, and a voltage of 10 to 400 V is applied for 5 to 60 minutes at a substrate temperature of 10 to 500 ° C to perform electrostatic thermal bonding .
이때, 도1과 도2는 정전 열 접합장치의 구조도로서, 이에 도시한 바와 같이 각각은 정전 열 접합을 실시할 반도체 기판에 전원을 인가하고, 기록하는 전원공급 및 기록부(1)와; 온도조절부(2)의 제어에 따라 상기 정전 열 접합을 실시할 반도체 기판을 가열하는 가열부(3)로 구성되며, 실리콘 기판과 상기 혼합물이 증착된 실리콘 기판을 접합시킬 때는 각 실리콘기판에 전원을 인가하며, ITO(INDIUM TIN OXIDE)가 증착된 유리기판과 혼합물이 증착된 실리콘 기판을 접합시킬 경우 실리콘 기판에 전원의 양극을 접속하고, 유리기판에 전원의 음극을 접속하여 전압을 인가한다.1 and 2 illustrate a structure of an electrostatic thermal bonding apparatus. As shown in FIG. 1 and FIG. 2, a power supply and write unit 1 for applying and recording power to a semiconductor substrate to be electrostatically bonded is provided. And a heating unit (3) for heating the semiconductor substrate to be subjected to the electrostatic thermal bonding under the control of the temperature control unit (2). When joining the silicon substrate and the silicon substrate on which the mixture is deposited, When a glass substrate on which ITO (INDIUM TIN OXIDE) is deposited and a silicon substrate on which a mixture is deposited are bonded, a positive electrode of the power source is connected to the silicon substrate, and a negative electrode of the power source is connected to the glass substrate.
또한, 도3은 본 발명에 의해 접합된 ITO코팅 유리와 실리콘 산화물과 금속 산화물의 혼합물이 증착된 실리콘기판의 단면 주사 전자 현미경 사진으로써, 이에 도시한 바와 같이 강한 접합력을 갖도록 접합됨을 알 수 있다.3 is a cross-sectional scanning electron micrograph of a silicon substrate on which ITO-coated glass and a mixture of silicon oxide and metal oxide are bonded according to the present invention. As shown in FIG. 3, the silicon substrate is bonded so as to have a strong bonding force.
이와 같은 접합의 근거는 리튬이온의 경우 원자량이 다른 이온에 비해 매우 작아 낮은 전압을 인가하여도 이동에 필요한 운동에너지를 얻을 수 있기 때문이다.The reason for such a junction is that the lithium ion has a much smaller atomic weight than other ions, so that even if a low voltage is applied, kinetic energy necessary for movement can be obtained.
상기한 바와 같이 본 발명은 전자선 증착법으로 금속 산화물과 실리콘 산화물의 혼합물을 반도체 기판 위에 증착하여 두 반도체 기판의 접합시 중간층으로 이용함으로써, 공정시간을 단축하고, 낮은 온도 및 전압에서 공정하여 제조비용을 절감하며, 소자의 응용시 적당한 강한 접합강도를 얻을 수 있는 효과가 있다.As described above, according to the present invention, a mixture of a metal oxide and a silicon oxide is deposited on a semiconductor substrate by an electron beam deposition method and used as an intermediate layer at the time of bonding the two semiconductor substrates, thereby shortening the processing time, And a strong bonding strength suitable for application of the device can be obtained.
Claims (15)
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