KR19990024970A - Manufacturing Method of Compound Semiconductor Device - Google Patents

Manufacturing Method of Compound Semiconductor Device Download PDF

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KR19990024970A
KR19990024970A KR1019970046375A KR19970046375A KR19990024970A KR 19990024970 A KR19990024970 A KR 19990024970A KR 1019970046375 A KR1019970046375 A KR 1019970046375A KR 19970046375 A KR19970046375 A KR 19970046375A KR 19990024970 A KR19990024970 A KR 19990024970A
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layer
gate
semiconductor device
compound semiconductor
ohmic
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KR1019970046375A
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KR100248399B1 (en
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박병선
최현태
박철순
윤형섭
이진희
편광의
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정선종
한국전자통신연구원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]
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    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]

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Abstract

본 발명은 화합물 반도체 소자의 제작방법에 관한 것으로서, 건식식각방법으로 게이트 리쎄스한 경우 발생하는 게이트전극과 오믹층과의 접촉을 방지함으로 인해 게이트와 소스 또는 게이트와 드레인간의 누설전류를 감소시켜서 소자의 전기적 특성을 향상시킨다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a compound semiconductor device, and by reducing the leakage current between the gate and the source or the gate and the drain by preventing contact between the gate electrode and the ohmic layer generated when the gate is recessed by a dry etching method. To improve the electrical properties of.

본 발명에서는 게이트 리쎄스시 쇼트키층의 손상을 방지하기 위한 에치-스탑 에치텍셜(etch-stop epitaxial)층의 성장방법, 건식식각에 의한 게이트 리쎄스와 선택적 습식식각에 의한 게이트 리쎄스의 이단계 게이트 리쎄스 방법과 ECR에 의해 성장한 산화막과 질화막의 이중절연막을 사용하여 소자를 보호하는 방법으로 구성함으로써, 게이트 리쎄스시 쇼트키층의 손상을 방지할 수 있고, GaAs의 오믹층과 T-게이트전극이 직접 접촉하지 않기 때문에 화합물 반도체 소자의 전기적 특성을 개선할 수 있으며, Ni/Ge/Ni/Ag/Au 오믹금속층을 채택하여 오믹 금속의 표면을 매끄럽게 하여 소자의 초미세(submicron)급 미세 게이트 패턴형성을 용이하게 할 수 있는 효과를 가진다.In the present invention, a method of growing an etch-stop epitaxial layer to prevent damage of the Schottky layer during gate recess, a gate recess by dry etching, and a two-step gate recess of gate recess by selective wet etching By protecting the device by using the double layer of oxide film and nitride film grown by the Cess method and ECR, damage of the Schottky layer can be prevented during gate recess, and the ohmic layer of GaAs and the T-gate electrode are in direct contact with each other. It is possible to improve the electrical characteristics of the compound semiconductor device, and to adopt the Ni / Ge / Ni / Ag / Au ohmic metal layer to smooth the surface of the ohmic metal to facilitate the formation of submicron fine gate patterns of the device. Has the effect of making it possible.

Description

화합물 반도체 소자의 제작방법Manufacturing Method of Compound Semiconductor Device

본 발명은 전계효과형 화합물 반도체 소자 제작 기술중 게이트의 누설 전류특성을 개선하기 위한 게이트 리쎄스 방법과 게이트전극 제작방법에 관한 것이다.The present invention relates to a gate recess method and a gate electrode fabrication method for improving leakage current characteristics of a gate in a field effect compound semiconductor device fabrication technology.

종래의 건식식각 게이트 리쎄스 방법을 채택한 전계효과형 화합물 반도체 소자의 제작방법은, 게이트리쎄스할 때 쇼트키층을 손상시키고 포토레지스트와 오믹층의 식각 프로파일이 수직형태로 되어 게이트 금속전극을 증착한 후 리프트오프하면 게이트 전극과 오믹층이 서로 접촉되어 게이트 전극과 소스 또는 드레인 전극 사이에 누설전류 경로가 발생함으로써 화합물 반도체 소자의 전기적 특성이 열화되는 문제가 발생한다.In the conventional method of fabricating a field effect compound semiconductor device employing the dry etching gate recess method, when the gate recess is applied, the Schottky layer is damaged and the etching profile of the photoresist and the ohmic layer is vertical to deposit the gate metal electrode. After the lift-off, the gate electrode and the ohmic layer are in contact with each other to generate a leakage current path between the gate electrode and the source or drain electrode, thereby deteriorating electrical characteristics of the compound semiconductor device.

도 1a에서 1e는 종래의 전계효과형 화합물 반도체 소자의 제작공정도로서, 종래에 사용한 갈륨비소 고전자 이동도 트랜지스터(HEMT), 금속-반도체 전계효과 트랜지스터(MESFET) 등과 같은 전계효과형 화합물 반도체 소자의 제조방법을 간단히 나타내었다.1A to 1E are diagrams illustrating fabrication processes of a conventional field effect compound semiconductor device, and the field effect compound semiconductor device such as a gallium arsenide high electron mobility transistor (HEMT) and a metal-semiconductor field effect transistor (MESFET). The preparation method is shown briefly.

도 1a는 반절연 갈륨비소 기판(1), 버퍼층(2), 서브 채널(3), 채널층(4), 스페이서층(5), 쇼트키층(6), N형 GaAs 오믹층(7), 소오스 전극 및 드레인 전극의 오믹전극을 형성하기 위한 감광막의 패턴(8)으로 이루어져 있다.1A shows a semi-insulating gallium arsenide substrate 1, a buffer layer 2, a subchannel 3, a channel layer 4, a spacer layer 5, a Schottky layer 6, an N-type GaAs ohmic layer 7, It consists of the pattern 8 of the photosensitive film for forming the ohmic electrode of a source electrode and a drain electrode.

상기와 같이 감광막 패턴(8)을 형성한 다음 열저항 가열 진공 증착기로 합금형태로 된 AuGe 금속을 1000∼2000A두께 그리고 Ni 금속을 400∼100A두께로 비교적 두껍게 증착한 다음에 Au 금속을 차례로 증착하여 AuGe/Ni/Au로 구성된 어믹금속층(9)을 상기 도 1b에 나타내었다.After forming the photoresist layer pattern 8 as described above, AuGe metal in the alloy form was deposited to a thickness of 1000 to 2000 A and Ni metal to 400 to 100 A in thickness using a heat resistance heating vacuum evaporator, and then Au metal was sequentially deposited. An amorphous metal layer 9 composed of AuGe / Ni / Au is shown in FIG. 1B.

오믹 금속층(9)을 증착한 다음에 상기 도 2c와 같이 lift-off 방법으로 상기 감광막 패턴(8)을 제거하여 소오스 전극과 드레인 전극(9)을 형성한 후, 약 430℃ 정도의 온도에서 20초 정도 열처리를 수행한다.After depositing the ohmic metal layer 9, the photoresist pattern 8 is removed by a lift-off method to form a source electrode and a drain electrode 9 as shown in FIG. 2C, and then, at a temperature of about 430 ° C. The heat treatment is performed for about a second.

그 후 도 1d와 같이 전계효과형 화합물 반도체 소자의 T형 게이트를 만들기 위한 PMMA/P(MMA-MAA) 감광막 패턴(10)을 형성하고, 건식식각방법으로 게이트 리쎄스 한다.Thereafter, as shown in FIG. 1D, a PMMA / P (MMA-MAA) photosensitive film pattern 10 for forming a T-type gate of the field effect compound semiconductor device is formed, and the gate is recessed by a dry etching method.

이어서 도 1e와 같이 Ti/Pt/Au로 구성된 게이트 금속전극(11)을 증착하고 lift-off 방법으로 상기 감광막 패턴(10)을 제거하면 미세한 T형 게이트를 갖는 HEMT과 MESFET 등의 전계효과형 화합물 반도체 소자가 완성된다.Subsequently, as shown in FIG. 1E, when the gate metal electrode 11 formed of Ti / Pt / Au is deposited and the photoresist pattern 10 is removed by a lift-off method, a field effect compound such as HEMT and MESFET having a fine T-type gate is formed. The semiconductor element is completed.

상기와 같은 방법으로 게이트 리쎄스하고, 게이트전극을 제작하였을 경우에는 화합물 반도체의 쇼트키층을 손상시키고, 포토레지스트와 오믹층의 식각 프로파일이 수직형태로 되어 게이트 금속전극을 증착한 후 리프트오프하면 HEMT 소자의 T형 게이트 전극(11)과 N형 GaAs 오믹층(7)이 서로 접촉되어 게이트전극과 소스 또는 드레인 전극사이에 생긴 누설전류 경로 때문에 화합물 반도체 소자의 전기적 특성이 열화되는 문제가 발생한다.When the gate is recessed and the gate electrode is manufactured in the same manner as above, the Schottky layer of the compound semiconductor is damaged, the etch profile of the photoresist and the ohmic layer becomes vertical, and the gate metal electrode is deposited and then lifted off. The T-type gate electrode 11 and the N-type GaAs ohmic layer 7 of the device are in contact with each other, resulting in a problem of deterioration of the electrical characteristics of the compound semiconductor device due to a leakage current path generated between the gate electrode and the source or drain electrode.

상기 문제를 해결하기 위해 본 발명은, 고전자 이동도 트랜지스터(HEMT), 금속-반도체 전계효과 트핸지스터(MESFET) 등의 전계효과형 화합물 반도체 소자의 게이트 누설전류특성을 개선하기 위한 게이트 리쎄스 방법과 게이트전극 제작방법을 제공하는 것을 목적으로 한다.In order to solve the above problems, the present invention provides a gate recess method for improving gate leakage current characteristics of a field effect compound semiconductor device such as a high electron mobility transistor (HEMT) and a metal-semiconductor field effect transistor (MESFET). And to provide a gate electrode manufacturing method.

도 1a에서 1e는 종래의 전계효과형 화합물 반도체 소자의 제작공정도,1a to 1e is a manufacturing process diagram of a conventional field effect compound semiconductor device,

도 2a에서 2h는 본 발명이 적용되는 전계효과형 화합뮬 반도체 소자의 제작공정도.2a to 2h is a manufacturing process diagram of the field effect compound mule semiconductor device to which the present invention is applied.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

1,101 : 반절연 갈륨비소 기판 2,102 : 버퍼층1,101: semi-insulating gallium arsenide substrate 2,102: buffer layer

3,103 : 서브 채널 4,104 : 채널층3,103: subchannel 4,104: channel layer

5,105 : 스페이서층 6,106 : 쇼트키층5,105: spacer layer 6,106: Schottky layer

7 : N형 갈륨비소오믹층 8 : 오믹전극 포토레지스트 패턴7: N-type gallium arsenide layer 8: Ohmic electrode photoresist pattern

9 : HEMT소자의 오믹 금속전극 10 : T형 게이트 패턴9: ohmic metal electrode of HEMT device 10: T-type gate pattern

11 : HEMT소자의 T형 게이트 전극 107 : 에치스탑(etch-stop)층11: T-type gate electrode of HEMT device 107: etch-stop layer

108 : N형 갈륨비소오믹층108: N-type gallium arsenic layer

109 : 오믹전극 포토레지스트 패턴 110 : HEMT소자의 오믹 금속전극109: ohmic electrode photoresist pattern 110: ohmic metal electrode of the HEMT element

111 : T형 게이트 패턴111: T-type gate pattern

112 : 게이트 리쎄스된 N형 갈륨비소오믹층112: gated N-type gallium arsenide layer

113 : 식각된 에치스탑층 114 : 게이트 금속113: etched etch stop layer 114: gate metal

115 : T형 게이트 전극 116 : HEMT소자의 보호막115: T-type gate electrode 116: protective film of the HEMT element

상기 목적을 달성하기 위해 본 발명은, 반절연 갈룸비소 기판에 버퍼층, 서브채널, 채널층, 스페이서층, 쇼트키층, 에치스탑층, N형 갈륨비소오믹층, HEMT소자의 오믹 금속전극을 차례로 성장하는 공정과, 상기 오믹 금속전극층상에 전자선 진공층착기를 사용하여 일정 두께로 구성된 오믹금속층을 증착하고 일정 온도에서 열처리를 하여 소오스와 드레인의 오믹전극을 형성하는 공정과, 소오스와 드레인 오믹전극 형성 후 전계효과형 화합물 반도체 소자의 게이트를 형성하기 위해 감광막 패턴을 형성하는 공정과, 상기 감광막 패턴 아래 빈 공간을 갖는 식각단면을 형성하는 제 4 공정과, 식각단면 형성 후 일정비율의 혼합용액을 사용하여 에치스탑층을 제거한 후 게이트 금속전극을 증착하는 공정과, 리프트오프 방법으로 상기 감광막 패턴을 제거하여 T형 게이트를 갖는 HEMT과 MESFET의 전계효과형 화합물 반도체 소자를 제작하는 공정과, 화합물 반도체 소자를 보호하기 위해 ECR 방식으로 상온에서 산화막과 질화막을 증착하는 제 7 공정으로 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention, a buffer layer, a subchannel, a channel layer, a spacer layer, a Schottky layer, an etch stop layer, an N-type gallium arsenic layer, and an ohmic metal electrode of an HEMT device are sequentially grown on a semi-insulating gallum arsenide substrate. And depositing an ohmic metal layer having a predetermined thickness on the ohmic metal electrode layer by using an electron beam vacuum layer bonder and performing heat treatment at a predetermined temperature to form an ohmic electrode of a source and a drain, and forming a source and a drain ohmic electrode. Using a process of forming a photoresist pattern to form a gate of the field effect compound semiconductor device, a fourth process of forming an etch cross section having an empty space under the photoresist pattern, and using a mixed solution having a predetermined ratio after forming the etch cross section Removing the etch stop layer and depositing a gate metal electrode; and removing the photoresist pattern by a lift-off method. And a seventh step of depositing an oxide film and a nitride film at room temperature by an ECR method to protect the compound semiconductor device, and to manufacture a field effect compound semiconductor device of a HEMT and a MESFET having a T-type gate.

이하 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a에서 2h는 본 발명이 적용되는 전계효과형 화합뮬 반도체 소자의 제작공정도로서, 반도체 기판을 습식식각하여 활성영역을 정의한 다음 오믹전극을 형성하기 위한 포토레지스터 패턴을 나타낸 것이다.2A to 2H are manufacturing process diagrams of the field effect compound mule semiconductor device to which the present invention is applied, and show a photoresist pattern for forming an ohmic electrode after defining an active region by wet etching a semiconductor substrate.

도 2a는 반절연 갈륨비소 기판(101), 버퍼층(102), 서브 채널(103), 채널층(104), 스페이서층(105), 쇼트키층(106), InxAlAs1-x(x=0.8∼1) 에치-스탑(etch-stop)층(107), N형 GaAs 오믹층(108), 오믹전극용 포토 레지스트 패턴(109)으로 이루어져 있다.2A shows a semi-insulating gallium arsenide substrate 101, a buffer layer 102, a sub-channel 103, a channel layer 104, a spacer layer 105, a Schottky layer 106, InxAlAs 1-x (x = 0.8 to 1) An etch-stop layer 107, an N-type GaAs ohmic layer 108, and a photoresist pattern 109 for an ohmic electrode.

이어서 도 2c에서 보는 바와 같이 전자선 진공증착기를 사용하여 Ni를 70A∼100A두께, Ge를 300∼500A두께, Ni을 400∼600A두께, Ag을 100∼200A두께, Au를 1000∼1500A두께로 각각 증착하여 리프트-오프 후 Ni/Ge/Ag/Au로 구성된 오믹 금속층을 증착하고, 처음에는 340∼360℃의 저온에서 급속열처리하고 다시 390∼420℃의 고온에서 급속열처리하여 소오스와 드레인의 오믹전극(110)을 제작한다.Subsequently, as shown in FIG. 2C, Ni is deposited to 70A to 100A thickness, Ge to 300 to 500A thickness, Ni to 400 to 600A thickness, Ag to 100 to 200A thickness, and Au to 1000 to 1500A thickness, respectively. After the lift-off, the ohmic metal layer composed of Ni / Ge / Ag / Au was deposited, and rapidly heat-treated at a low temperature of 340 to 360 ° C. and then rapidly heat-treated at a high temperature of 390 to 420 ° C. 110).

그 후 도 2d와 같이 전계효과형 화합물 반도체 소자의 T형 게이트를 형성하기 위한 PMMA/P(MMA-MAA) 감광막 패턴(111)을 형성한다.Thereafter, as shown in FIG. 2D, a PMMA / P (MMA-MAA) photosensitive film pattern 111 for forming a T-type gate of the field effect compound semiconductor device is formed.

상기 도 2d는 본 발명에 의한 게이트 리쎄스방법을 나타낸 것이다.2D illustrates a gate recess method according to the present invention.

먼저 SF6와 BCl3의 혼합가스를 사용하는 ECR(Electrom cyclotron resonance) 건식식각 방식으로 게이트 리쎄스하여 오믹층(108)을 선택적으로 제거한 다음에 citric acid와 H2O를 3:1로 배합하여 다시 GaAs 오믹층(108)을 선택적으로 식각하여 도 2e에서 처럼 PMMA/P(MMA-MAA) 감광막 패턴(111) 아래에 빈 공간을 갖는 식각단면(112)과 (113)를 만든다.First, the ohmic layer 108 is selectively removed by gate-resisting by using an ECR (Electrom cyclotron resonance) dry etching method using a mixture of SF 6 and BCl 3 , and then mixing citric acid and H 2 O at 3: 1. The GaAs ohmic layer 108 is selectively etched again to form etching sections 112 and 113 having an empty space under the PMMA / P (MMA-MAA) photoresist pattern 111 as shown in FIG. 2E.

이때 수직방향으로의 식각은 InxAlAs1-x(x-0.8∼1) 층에 의해 에치-스탑(etch-stop)되어 쇼트키층(106)은 손상을 받지 않게 된다.At this time, the etching in the vertical direction is etch-stop by the In x AlAs 1-x (x-0.8 to 1) layer so that the Schottky layer 106 is not damaged.

이어서 도 2f와 같이 HCl과 H2O의 1 대 10 비율의 혼합용액을 사용하여 InxAlAs1-x(x=0.8∼1)으로 구성된 에치-스탑층을 제거한 후 Ti/Pt/Au 게이트 금속전극(114)을 증착한다.Subsequently, as shown in FIG. 2F, an etch-stop layer composed of In x AlAs 1-x (x = 0.8 to 1) was removed using a mixed solution of HCl and H 2 O in a ratio of 1 to 10, and then the Ti / Pt / Au gate metal was removed. Electrode 114 is deposited.

다음에 도 2g에서 보는 바와 같이 리프트-스탑 방법으로 상기 감광막 패턴(111)을 제거하여 미세한 T형 게이트를 갖는 HEMT과 MESFET 등의 전계효과형 화합물 반도체 소자를 제작한다.Next, as shown in FIG. 2G, the photoresist pattern 111 is removed by a lift-stop method to fabricate a field effect compound semiconductor device such as HEMT and MESFET having a fine T-type gate.

마지막으로 도 2h에서 처럼 화합물 반도체 소자를 보호하기 위하여 ECR 방식으로 상온에서 산화막과 질화막을 증착한다.Finally, in order to protect the compound semiconductor device as shown in FIG. 2H, an oxide film and a nitride film are deposited at room temperature by an ECR method.

종래의 방법에 비해서 SF6와 BCl3의 혼합가스를 사용하는 ECR 건식식각방법으로 선택적으로 GaAs 오믹층을 게이트 리쎄스하고 다시 citric acid와 H2O를 3.5 : 1로 배합한 용액으로 GaAs 오믹층을 선택적으로 습식식각하는 이단계 게이트 리쎄스방법을 사용하여 T-게이트패턴 밑에 빈 공간이 만들어져 GaAs의 오믹층과 T-게이트전극이 직접 접촉하지 않기 때문에 화합물 반도체 소자의 전기적 특성을 개선할 수 있다.Compared to the conventional method, the GaAs ohmic layer was prepared by gate-resisting the GaAs ohmic layer selectively by ECR dry etching method using a mixed gas of SF 6 and BCl 3 and mixing citric acid and H 2 O at 3.5: 1. By using the two-step gate recess method of selectively wet etching, an empty space is formed under the T-gate pattern, so that the ohmic layer of GaAs and the T-gate electrode do not directly contact, thereby improving the electrical characteristics of the compound semiconductor device. .

또한 Ni/Ge/Ni/Ag/Au 오믹금속층을 채택하여 화합물 반도체 소자의 오믹접촉층을 개선할 수 있고, 오믹 금속의 표면을 매끄럽게 하여 소자의 submicron급 게이트 패턴형성을 용이하게 할 수 있다.In addition, by adopting the Ni / Ge / Ni / Ag / Au ohmic metal layer, the ohmic contact layer of the compound semiconductor device can be improved, and the surface of the ohmic metal can be smoothed to facilitate the formation of a submicron gate pattern of the device.

상술한 바와 같이 본 발명에 의한 전계효과형 소자를 제작하는 방법은, 종래의 방법에 비해 InxAlAs1-x(x=0.8∼1)으로 구성된 에치-스탑(etch-stop)층을 갖는 반도체 기판을 사용함으로써, 게이트 리쎄스시 쇼트키층의 손상을 방지할 수 있고, SF6와 BCl3의 혼합가스를 사용하는 ECR 건식식각방법으로 선택적으로 GaAS 오믹층을 게이트 리쎄스하고 다시 citric acid와 H2O를 3:1로 배합한 용액으로 GaAs 오믹층을 선택적으로 습식식각하는 이단계 게이트 리쎄스방법을 사용하여 GaAs의 오믹층과 T-게이트 전극이 직접 접촉하지 않기 때문에 화합물 반도체 소자의 전기적 특성을 개선할 수 있다.As described above, the method of manufacturing the field effect device according to the present invention is a semiconductor having an etch-stop layer composed of In x AlAs 1-x (x = 0.8 to 1) , compared to the conventional method. By using the substrate, the damage of the Schottky layer can be prevented during the gate recess, and the ECR dry etching method using the mixed gas of SF 6 and BCl 3 selectively gates the GaAS ohmic layer and again, citric acid and H 2. The OA layer and the T-gate electrode do not come into direct contact with the GaAs ohmic layer by using a two-step gate recess method that selectively wets the GaAs ohmic layer with a 3: 1 solution. It can be improved.

또한 Ni/Ge/Ni/Ag/Au 오믹금속층을 채택하여 오믹 금속의 표면을 매끄럽게하여 소자의 submicron급 미세 게이트 패턴 형성을 용이하게 할 수 있는 효과가 있다.In addition, the Ni / Ge / Ni / Ag / Au ohmic metal layer is adopted to smooth the surface of the ohmic metal, thereby facilitating the formation of a submicron-class fine gate pattern of the device.

Claims (8)

전계효과형 화합물 반도체 소자의 게이트 누설전류특성을 개선하기 위한 제작방법에 있어서,In the manufacturing method for improving the gate leakage current characteristics of the field effect compound semiconductor device, 반절연 갈룸비소 기판에 버퍼층, 서브채널, 채널층, 스페이서층, 쇼트키층, 식각정지층, N형 갈륨비소오믹층, HEMT소자의 오믹 금속전극을 차례로 성장하는 제 1 공정과;A first step of sequentially growing a buffer layer, a subchannel, a channel layer, a spacer layer, a Schottky layer, an etch stop layer, an N-type gallium arsenic layer, and an ohmic metal electrode of an HEMT element on a semi-insulating gallum arsenide substrate; 상기 오믹 금속전극층상에 전자선 진공층착기를 사용하여 일정 두께로 구성된 오믹금속층을 증착하고 일정 온도에서 열처리를 하여 소오스와 드레인의 오믹전극을 형성하는 제 2 공정과;A second step of depositing an ohmic metal layer having a predetermined thickness on the ohmic metal electrode layer by using an electron beam vacuum layer bonder and performing heat treatment at a predetermined temperature to form an ohmic electrode of a source and a drain; 소오스와 드레인 오믹전극 형성 후 전계효과형 화합물 반도체 소자의 게이트를 형성하기 위해 감광막 패턴을 형성하는 제 3 공정과;Forming a photoresist pattern to form a gate of the field effect compound semiconductor device after the source and drain ohmic electrodes are formed; 상기 감광막 패턴 아래 빈 공간을 갖는 식각단면을 형성하는 제 4 공정과;A fourth step of forming an etch cross section having an empty space under the photosensitive film pattern; 식각단면 형성 후 일정비율의 혼합용액을 사용하여 식각정지층을 제거한 후 게이트 금속전극을 증착하는 제 5 공정과;A fifth step of removing the etch stop layer by using a mixed solution having a predetermined ratio after forming the etch cross section and then depositing a gate metal electrode; 리프트오프 방법으로 상기 감광막 패턴을 제거하여 T형 게이트를 갖는 전계효과형 화합물 반도체 소자(HEMT과 MESFET)의 오믹접촉전극을 제작하는 제 6 공정과;A sixth step of fabricating an ohmic contact electrode of a field effect compound semiconductor device (HEMT and MESFET) having a T-type gate by removing the photoresist pattern by a lift-off method; 화합물 반도체 소자를 보호하기 위해 ECR 방식으로 상온에서 산화막과 질화막을 증착하는 제 7 공정을 포함하여 구성된 것을 특징으로 하는 화합물 반도체 소자의 제작방법.And a seventh step of depositing an oxide film and a nitride film at room temperature by an ECR method to protect the compound semiconductor device. 제 1 항에 있어서, 상기 제 1 공정은The method of claim 1, wherein the first process 상기 각 층을 차례로 성장하여 전계효과형 화합물 반도체 소자 및 고전자이동도 트렌지스터 반도체 기판을 형성하는 것을 특징으로 하는 화합물 반도체 소자의 제작방법.And growing each of the layers in sequence to form a field effect compound semiconductor device and a high electron mobility transistor semiconductor substrate. 제 1 항에 있어서, 상기 제 2 공정은The method of claim 1, wherein the second process 전자선 진공증착기를 사용하여 각각의 금속을 일정두께로 증착하여 리프트오프하여 각각의 금속으로 구성된 오믹금속층을 형성하고,Using an electron beam vacuum evaporator to deposit each metal to a certain thickness to lift off to form an ohmic metal layer composed of each metal, 오믹금속층 형성 후 다시 소정의 온도에서 열처리하여 전계효과형 화합물 반도체 소자의 오믹접촉전극을 형성하는 것을 특징으로 하는 화합물 반도체 소자의 제작방법.And forming an ohmic contact electrode of the field effect compound semiconductor device by heat-treating again at a predetermined temperature after forming the ohmic metal layer. 제 1 항에 있어서, 상기 제 3 공정은The method of claim 1, wherein the third process SF6와 BCl3의 혼합가스를 사용하는 ECR 건식식각방법으로반도체 기판의 갈륨비소층을 선택적으로 게이트 리쎄스하고,ECR dry etching method using a mixed gas of SF 6 and BCl 3 to selectively gate recess the gallium arsenide layer of the semiconductor substrate, 게이트 리쎄스 후 다시 구연산(citric acid)과 H2O를 일정 비율로 배합한 용액을 사용하여 이단계 게이트 리쎄스 방법으로 갈륨비소 오믹층을 선택적으로 습식식각하는 것을 특징으로 하는 화합물 반도체 소자의 제작방법.Fabrication of a compound semiconductor device, characterized in that the gallium arsenide ohmic layer is selectively wet-etched using a solution containing citric acid and H 2 O at a predetermined ratio after the gate recess. Way. 제 1 항에 있어서, 상기 제 4 공정은The method of claim 1, wherein the fourth process 상기 이단계 리쎄스 방법을 사용하여 게이트 패턴 밑에 빈 공간을 형성하고, 리프트오프 방법으로 전계효과형 화합물 반도체 소자의 게이트전극을 형성하는 것을 특징으로 하는 화합물 반도체 소자의 제작방법.And forming an empty space under the gate pattern using the two-step recess method, and forming a gate electrode of the field effect compound semiconductor device by a lift-off method. 제 1 항에 있어서, 상기 제 5 공정은The method of claim 1, wherein the fifth process 상기 이단계 리쎄스방법에서 갈륨비소 오믹층을 선택적으로 InxAlAs1-x을 식각정지층으로 사용하고,In the two-step recess method, a gallium arsenide ohmic layer is selectively used as In x AlAs 1-x as an etch stop layer, HCl과 H2O의 일정비율의 혼합용액을 사용하여 InxAlAs1-x식각정지층을 제거한 후 전계효과형 화합물 반도체 소자의 게이트 전극을 형성하는 것을 특징으로 하는 화합물 반도체 소자의 제작방법.A method of manufacturing a compound semiconductor device, comprising removing the In x AlAs 1-x etch stop layer using a mixed solution of HCl and H 2 O to form a gate electrode of a field effect compound semiconductor device. 제 1 항에 있어서, 상기 제 7 공정은The method of claim 1, wherein the seventh process ECR 방식으로 상온에서 산화막과 질화막을 증착한 후 게이트 전극 부근에 생긴 빈 공간을 이중 절연막으로 채움으로써 화합물 반도체 소자를 보호하는 것을 특징을 하는 화합물 반도체 소자의 제작방법.A method of fabricating a compound semiconductor device, comprising depositing an oxide film and a nitride film at room temperature by an ECR method and then protecting the compound semiconductor device by filling an empty space near the gate electrode with a double insulating film. 제 1 항에 있어서,The method of claim 1, 상기 제 1,2,3,4,5,6,7 공정을 사용하여 전계효과형 트랜지스터(MESFET), 고전자이동도 트랜지스터(HEMT) 및 이종접합형 트랜지스터(HBT)의 화합물 반도체 소자를 제작하는 것을 특징으로 하는 화합물 반도체 소자의 제작방법.A compound semiconductor device of a field effect transistor (MESFET), a high electron mobility transistor (HEMT) and a heterojunction transistor (HBT) is manufactured using the first, second, third, fourth, fifth, sixth and seventh processes. Method for producing a compound semiconductor device, characterized in that.
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KR100479266B1 (en) * 2002-11-26 2005-03-28 한국전자통신연구원 Semiconductor device having T-gate electrode and method of manufacturing the same
KR100681842B1 (en) * 2005-12-06 2007-02-12 재단법인서울대학교산학협력재단 T-type gate electrode and method for fabricating the same

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KR101104251B1 (en) 2008-11-24 2012-01-11 한국전자통신연구원 Method of fabrricating semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100479266B1 (en) * 2002-11-26 2005-03-28 한국전자통신연구원 Semiconductor device having T-gate electrode and method of manufacturing the same
KR100681842B1 (en) * 2005-12-06 2007-02-12 재단법인서울대학교산학협력재단 T-type gate electrode and method for fabricating the same

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