KR19980051967A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
- Publication number
- KR19980051967A KR19980051967A KR1019960070894A KR19960070894A KR19980051967A KR 19980051967 A KR19980051967 A KR 19980051967A KR 1019960070894 A KR1019960070894 A KR 1019960070894A KR 19960070894 A KR19960070894 A KR 19960070894A KR 19980051967 A KR19980051967 A KR 19980051967A
- Authority
- KR
- South Korea
- Prior art keywords
- nitride film
- film
- semiconductor device
- laminated
- contact hole
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
공정수행을 개선시킨 반도체장치의 제조방법에 관한 것이다.A method for manufacturing a semiconductor device with improved process performance.
본 발명은, 콘택 홀이 가공형성되는 단계를 포함하는 반도체장치의 제조방법에 있어서, 상기 콘택 홀을 포함하는 반도체 기판 상에 화학기상증착장치를 이용하여 질화티타늄막 및 질화텅스텐막을 적층형성시켜 접착력을 향상시키는 단계 및 전기적 연결을 위하여 상기 질화티타늄막 및 질화텅스텐막이 적층형성된 반도체 기판 상에 상기 화학기상증착장치를 이용하여 메탈막을 적층형성시키는 단계를 포함하여 이루어짐을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device including forming a contact hole, wherein a titanium nitride film and a tungsten nitride film are laminated on a semiconductor substrate including the contact hole by using a chemical vapor deposition apparatus. And forming a metal film by using the chemical vapor deposition apparatus on the semiconductor substrate on which the titanium nitride film and the tungsten nitride film are laminated to form an electrical connection.
따라서, 단일 모듈인 화학기상증착장치로 인시튜로 메탈막을 적층함으로 인해 생산성이 극대화되는 효과가 있다.Therefore, there is an effect that the productivity is maximized by stacking the metal film in situ as a chemical vapor deposition apparatus that is a single module.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 보다 상세하게는 메탈막(Metal)을 적층형성시키는 공정을 화학기상증착장치를 이용하여 수행함으로써 공정수행을 개선시킨 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having improved process performance by performing a process of stacking a metal film using a chemical vapor deposition apparatus.
일반적으로, 반도체장치의 제조에서는 소자들간의 상호연결 또는 리드 프레임(Lead Frame)을 통한 외부와 연결 등을 위해서 반도체 기판 상에 메탈막을 적층형성시킨다.In general, in the manufacture of a semiconductor device, a metal film is laminated on a semiconductor substrate for interconnection between devices or external connection through a lead frame.
이러한 메탈막의 적층형성은 주로 스퍼터링(Sputtering)장치를 이용하여 공정을 수행하였으나, 최근의 반도체장치가 고밀도화, 고집적화되어 감에 따라 스퍼터링장치 및 화학기상증착(CVD)장치를 혼용하여 사용하고 있다.Stacking of the metal film is mainly performed by using a sputtering device, but as a semiconductor device is recently densified and highly integrated, a sputtering device and a chemical vapor deposition (CVD) device are used in combination.
도1 (가) 내지 (마)는 종래의 반도체장치의 제조방법을 나타내는 단면도이다.1A to 1E are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
먼저, 도1 (가)는 콘택 홀이 가공형성되어 있는 반도체 기판(10) 상에 산화막(12)이 적층형성되고 그 상부에 스퍼러링으로 소정두께의 티타늄막(14)(Ti) 및 질화티타늄막(TiN)(16)을 적층형성시킨다.First, Fig. 1 (a) shows that an oxide film 12 is laminated on a semiconductor substrate 10 having a contact hole formed thereon, and a titanium film 14 (Ti) and nitride having a predetermined thickness by sputtering thereon. A titanium film (TiN) 16 is laminated.
이러한 티타늄막(14) 및 질화티타늄막(16)의 적층형성은 산화막(12)과 후속공정에서 적층형성되는 메탈막과의 접착력을 향상시키기 위한 것이다.The stacking of the titanium film 14 and the titanium nitride film 16 is to improve the adhesion between the oxide film 12 and the metal film laminated in a subsequent process.
여기서 산화막(12) 상에 적층형성되는 티타늄막(14) 및 질화티타늄막(16)은 콘택 홀 내부에 양호한 스텝 커버리지를 확보하기 위하여 약 1000Å 정도의 두께로 적층형성시킨다.Here, the titanium film 14 and the titanium nitride film 16 laminated on the oxide film 12 are laminated to a thickness of about 1000 mW in order to ensure good step coverage inside the contact hole.
그러면 콘택 홀 내부로 적층형성되는 티타늄막(14) 및 질화티타늄막(16)은 약 100Å의 정도의 두께로 적층형성되는 것이다.Then, the titanium film 14 and the titanium nitride film 16 stacked in the contact hole are formed to have a thickness of about 100 GPa.
이어서 도1 (나)는 화학기상증착을 이용하여 콘택 홀 내부를 포함하는 티타늄막(14) 및 질화티타늄막(16)이 적층형성된 상부에 소정두께의 텅스텐으로 이루어지는 메탈막(18)을 적층형성시키고, 도1 (다)는 산화막(12)이 적층형성된 일정영역을 포함하여 도1 (나)의 A-A선으로 제거하여 콘택 홀 내부에만 메탈막(18)이 존재하도록 한다.Subsequently, FIG. 1B shows a lamination of a metal film 18 made of tungsten having a predetermined thickness on top of the titanium film 14 including the inside of the contact hole and the titanium nitride film 16 formed by lamination using chemical vapor deposition. 1 (C) includes a predetermined region in which the oxide film 12 is stacked to be removed by the AA line of FIG. 1B so that the metal film 18 exists only inside the contact hole.
그리고 도1 (라)는 다시 스퍼터링을 이용하여 소정두께로 티타늄막(14) 및 질화티타늄막(16)을 적층형성시키고, 도1 (마)는 티타늄막(14) 및 질화티타늄막(16)이 적층형성된 상부에 알루미늄으로 이루어지는 메탈막(20)을 적층형성시키는 구성이다.FIG. 1 (d) again forms a titanium film 14 and a titanium nitride film 16 at a predetermined thickness using sputtering, and FIG. 1 (e) shows a titanium film 14 and a titanium nitride film 16. It is a structure which laminates the metal film 20 which consists of aluminum on this laminated upper part.
여기서 종래의 메탈막(18, 20)의 적층형성을 위한 반도체장치의 제조는 반도체장치가 고집적화, 고밀도화되어 가는 추세에 따라 스퍼터링 및 화학기상증착을 혼용하여 수행하였으나, 콘택 홀의 에스펙트 에어리가 계속적으로 커져가는 최근의 추세에는 그 스텝 커버리지를 충분히 확보하지 못하였다.Here, the manufacturing of the semiconductor device for stacking the conventional metal films 18 and 20 has been performed by using a combination of sputtering and chemical vapor deposition in accordance with the trend of high integration and high density of the semiconductor device, but the aspect air of the contact hole is continuously In recent years, the growing trend has not secured enough step coverage.
즉, 물리적인 방법을 이용하는 스퍼터링으로는 최근의 미세화되어가는 콘택 홀 내부로 원하는 스텝 커버리지를 확보하지 못하였기 때문이다.In other words, sputtering using a physical method does not secure desired step coverage into a contact hole that is becoming more recent.
또한 질화티타늄막(16)은 콘택 홀 내부에 적층형성되는 메탈막(18)인 텅스텐의 적층형성시 충분한 장벽역할을 하지 못하여 콘택 저항을 줄이기에는 그 한계가 있었다.In addition, the titanium nitride film 16 did not have a sufficient barrier role in forming a layer of tungsten, which is a metal film 18 laminated in the contact hole, and thus the contact resistance was limited.
그리고 공정수행시 스퍼터링장치에서 화학기상증착장치로 이동하기 때문에 웨이퍼(Wafer)가 공기(Air)와 접촉하여 산화되는 불량이 나타나기도 하였다.In addition, since the process moves from the sputtering apparatus to the chemical vapor deposition apparatus, the wafer is inferior in contact with air and oxidizes.
따라서 종래의 반도체장치의 제조는 상기 전술한 결함 등으로 인해 반도체장치의 제조 수율 및 신뢰성을 확보하지 못하여 생산성이 저하되는 문제점이 있었다.Therefore, the conventional semiconductor device has a problem in that productivity cannot be secured due to failure to secure the production yield and reliability of the semiconductor device due to the defects described above.
본 발명의 목적은, 메탈막을 적층형성하는 공정을 개선시켜 생산성을 극대화시키기 위한 반도체장치의 제조방법을 제공하는 데 있다.An object of the present invention is to provide a method of manufacturing a semiconductor device for maximizing productivity by improving a process of forming a metal film in a lamination.
도1 (가) 내지 (마)는 종래의 반도체장치의 제조방법을 나타내는 단면도이다.1A to 1E are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
도2 (가) 및 (나)는 본 발명에 따른 반도체장치의 제조방법의 실시예를 나타내는 단면도이다.2 (a) and (b) are sectional views showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10, 30 : 반도체 기판 12, 32 : 산화막10, 30: semiconductor substrate 12, 32: oxide film
14 : 티타늄막 16, 34 : 질화티타늄막14 titanium film 16, 34 titanium nitride film
18, 20, 38 : 메탈막 36 : 질화텅스텐막18, 20, 38: metal film 36: tungsten nitride film
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은, 콘택 홀이 가공형성되는 단계를 포함하는 반도체장치의 제조방법에 있어서, 상기 콘택 홀을 포함하는 반도체 기판 상에 화학기상증착장치를 이용하여 질화티타늄막 및 질화텅스텐막을 적층형성시켜 접착력을 향상시키는 단계 및 전기적 연결을 위하여 상기 질화티타늄막 및 질화텅스텐막이 적층형성된 반도체 기판 상에 상기 화학기상증착장치를 이용하여 메탈막을 적층형성시키는 단계를 포함하여 이루어짐을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: forming a contact hole, wherein the chemical vapor deposition apparatus is formed on a semiconductor substrate including the contact hole. Stacking a titanium nitride film and a tungsten nitride film to improve adhesion and stacking a metal film on the semiconductor substrate on which the titanium nitride film and the tungsten nitride film are laminated for electrical connection using the chemical vapor deposition apparatus. Characterized in that comprises a.
그리고 상기 메탈막은 그 재질이 텅스텐으로 이루어지는 것이 바람직하다.The metal film is preferably made of tungsten.
이하, 본 발명의 구체적인 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2 (가) 및 (나)는 본 발명에 따른 반도체장치의 제조방법의 실시예를 나타내는 단면도이다.2 (a) and (b) are sectional views showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.
먼저, 도2 (가)는 콘택 홀이 가공형성된 반도체 기판(30) 상에 산화막(32)이 적층형성되고, 그 상부에 소정의 두께로 질화티타늄막(34) 및 질화텅스텐막(W2N)(36)이 적층형성되는 구성이고, 도2 (나)는 질화티타늄막(34) 및 질화텅스텐막(36)이 적층형성된 상부에 메탈막(38)이 적층형성되는 구성이다.First, in FIG. 2A, an oxide film 32 is stacked on a semiconductor substrate 30 having a contact hole formed thereon, and a titanium nitride film 34 and a tungsten nitride film W 2 N are formed in a predetermined thickness thereon. ) 36 is laminated, and FIG. 2B is a structure in which the metal film 38 is laminated on the titanium nitride film 34 and the tungsten nitride film 36.
이러한 구성으로 이루어지는 본 발명은, 질화티타늄막(34), 질화텅스텐막(36) 및 메탈막(38)을 단일 모듈인 화학기상증착장치를 이용하여 인시튜로 적층형성시킨다.According to the present invention having such a configuration, the titanium nitride film 34, the tungsten nitride film 36, and the metal film 38 are laminated in situ using a chemical vapor deposition apparatus as a single module.
또한 산화막(32)과 메탈막(38)의 접착력 향상을 위해 본 발명의 방법으로 적층형성되는 질화티타늄막(34) 및 질화텅스텐막(36)은 그 두께를 90Å ∼ 110Å 정도로 적층형성할 수 있고, 실시예는 100Å의 두께로 적층형성시킨다.In addition, the titanium nitride film 34 and the tungsten nitride film 36, which are laminated by the method of the present invention to improve the adhesion between the oxide film 32 and the metal film 38, can be laminated to a thickness of about 90 to 110 kW. , Example is laminated to a thickness of 100Å.
그리고 본 발명의 메탈막(38)은 전기적 연결을 수행할 수 있는 것으로써, 그 재질을 텅스텐(W), 알루미늄(Al) 또는 구리(Cu) 등으로 적층형성할 수 있고, 실시예의 메탈막(38)은 텅스텐을 적층형성시킨다.In addition, the metal film 38 of the present invention is capable of electrical connection, and the material may be formed of tungsten (W), aluminum (Al), copper (Cu), or the like. 38) laminates tungsten.
전술한 구성으로 이루어지는 본 발명의 실시예에 대한 작용 및 효과에 대하여 설명한다.The operation and effects of the embodiment of the present invention having the above-described configuration will be described.
먼저, 산화막(32)에 의해 콘택 홀이 형성된 반도체 기판(30) 상에 약 100Å 정도의 두께로 질화티타늄막(34) 및 질화텅스텐막(36)을 적층형성시킨다.First, a titanium nitride film 34 and a tungsten nitride film 36 are laminated on a semiconductor substrate 30 having contact holes formed by an oxide film 32 to a thickness of about 100 GPa.
여기서 질화티타늄막(34) 및 질화텅스텐막(36)의 적층형성은 반도체장치의 전기적 연결을 위하여 후속공정에서 적층형성되는 메탈막(38)이 반도체 기판(30) 상에 적층형성되어 있는 산화막(32)과 양호한 접착력을 유지시키기 위해서이다.Here, the stacking of the titanium nitride film 34 and the tungsten nitride film 36 includes an oxide film in which a metal film 38 stacked in a subsequent process is laminated on the semiconductor substrate 30 for electrical connection of the semiconductor device. 32) and good adhesion.
그리고 콘택 홀의 에스펙트 에어리어 즉, 콘택 홀의 밑변의 단면길이를 깊이로 나눈값이 2.5 ∼ 3 보다 큰 경우에는 물리적인 방법을 이용하는 스퍼터링으로는 콘택 홀의 밑변까지 충분히 원하는 두께로 질화티타늄막(34) 및 질화텅스텐막(36)을 적층형성시키지 못하나, 본 발명은 가스 반응을 이용하는 화학기상증착으로 수행하기 때문에 에스펙트 에어리어가 아주 큰 값을 가지는 콘택 홀에 대해서도 원하는 두께의 질화티타늄막(34) 및 질화텅스텐막(36)을 적층형성시킬 수 있어 스텝 커버리지를 충분히 확보할 수 있다.And when the area of the contact hole, that is, the cross-sectional length of the bottom of the contact hole divided by the depth is larger than 2.5 to 3, the titanium nitride film 34 and the desired thickness sufficiently to the bottom of the contact hole by sputtering using a physical method. Although the tungsten nitride film 36 cannot be laminated, the present invention is performed by chemical vapor deposition using a gas reaction, so that the titanium nitride film 34 and nitride having a desired thickness even for a contact hole having a very large value area. The tungsten film 36 can be stacked to ensure sufficient step coverage.
이렇게 질화티타늄막(34) 및 질화텅스텐막(36)이 적층형성된 상부에 화학기상증착을 이용하여 텅스텐으로 이루어지는 메탈막(38)을 적층형성시키면 된다.In this way, the titanium film 34 and the tungsten nitride film 36 may be laminated on the metal film 38 made of tungsten by chemical vapor deposition.
본 발명은, 질화티타늄막(34), 질화텅스텐막(36) 및 메탈막(38)의 적층형성을 단일 모듈인 화학기상증착장치를 이용하여 인시튜로 수행한다.In the present invention, the stacking of the titanium nitride film 34, the tungsten nitride film 36, and the metal film 38 is performed in situ using a chemical vapor deposition apparatus as a single module.
그래서 공정스텝(Step)을 단축시킬 수 있어 공정소요시간을 줄이고, 또한 단일 모듈에서 공정이 수행되기 때문에 웨이퍼가 공기와 접촉되는 것을 방지할 수 있어 그로 인한 불량이 제거된다.Therefore, the process step can be shortened, so that the process time is reduced, and since the process is performed in a single module, the wafer can be prevented from coming into contact with air, thereby eliminating defects.
또한 가스 반응으로 질화티타늄막(34) 및 질화텅스텐막(36)을 적층형성시킴으로 인해 충분한 스텝 커버리지를 확보할 수 있고, 원하는 두께의 질화티타늄막 (34) 및 질화텅스텐막(36)을 적층형성시킬 수 있어 불필요한 질화티타늄 및 질화텅스텐의 사용이 줄어들기 때문에 고가의 원자재 손실을 방지할 수 있다.In addition, by stacking the titanium nitride film 34 and the tungsten nitride film 36 by gas reaction, sufficient step coverage can be ensured, and the titanium nitride film 34 and the tungsten nitride film 36 having a desired thickness can be laminated. This reduces the use of unnecessary titanium nitride and tungsten nitride, thereby avoiding costly raw material losses.
그리고 본 발명은 가스 반응으로 질화티타늄막(34) 및 질화텅스텐막(36)을 적층형성시키기 때문에 메탈막(38)의 적층형성시 충분한 장벽역할을 수행할 수 있어 콘택저항을 줄일수 있다.In the present invention, since the titanium nitride film 34 and the tungsten nitride film 36 are laminated by the gas reaction, a sufficient barrier role may be performed when the metal film 38 is stacked, thereby reducing contact resistance.
실예로 종래보다 본 발명의 콘택저항이 약 50%로 줄어드는 측청치를 얻을 수 있다.For example, the measured value of the contact resistance of the present invention can be reduced to about 50% compared to the related art.
그래서 본 발명은 공정스텝의 단축 및 단일 모듈에서의 공정수행으로 불량의 원인을 제거할 수 있고, 충분한 스텝 커버리지 확보로 인해 반도체장치 제조수율 증가 및 반도체장치의 신뢰도가 향성되며, 또한 고가의 원자재의 불필요한 손실 등을 방지하여 가격 경쟁력 등을 확보할 수 있다.Therefore, the present invention can eliminate the cause of defects by shortening the process step and performing the process in a single module, increasing the semiconductor device manufacturing yield and improving the reliability of the semiconductor device by ensuring sufficient step coverage, It is possible to secure price competitiveness by preventing unnecessary losses.
따라서, 본 발명에 의하면 단일 모듈에서 인시튜로 메탈막을 적층함으로 인해 생산성이 극대화되는 효과가 있다.Therefore, according to the present invention, the productivity is maximized by laminating metal films in situ in a single module.
이상에서 본 발명은 기재된 구체예에 대해서만 상세히 설명되었지만 본 발명의 기술사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960070894A KR19980051967A (en) | 1996-12-24 | 1996-12-24 | Manufacturing Method of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960070894A KR19980051967A (en) | 1996-12-24 | 1996-12-24 | Manufacturing Method of Semiconductor Device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980051967A true KR19980051967A (en) | 1998-09-25 |
Family
ID=66428802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960070894A KR19980051967A (en) | 1996-12-24 | 1996-12-24 | Manufacturing Method of Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19980051967A (en) |
-
1996
- 1996-12-24 KR KR1019960070894A patent/KR19980051967A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5963827A (en) | Method for producing via contacts in a semiconductor device | |
| US6329284B2 (en) | Manufacturing process of a semiconductor device | |
| KR100390952B1 (en) | Method of manufacturing a capacitor | |
| JP3122845B2 (en) | Method for forming metal wiring of semiconductor device | |
| KR20060072680A (en) | Capacitor for semiconductor device and manufacturing method thereof | |
| US7687392B2 (en) | Semiconductor device having metal wiring and method for fabricating the same | |
| KR19980051967A (en) | Manufacturing Method of Semiconductor Device | |
| KR20040047503A (en) | Method for forming aluminum metal wiring | |
| KR19980051762A (en) | Manufacturing Method of Semiconductor Device | |
| KR100499401B1 (en) | Method for forming metal interconnection layer of semiconductor device | |
| KR950005259B1 (en) | Fabricating method of semiconductor device | |
| KR100464652B1 (en) | Method for forming capacitor of semiconductor device | |
| KR100332122B1 (en) | Method of forming a metal wiring in a semiconductor device | |
| KR100642917B1 (en) | Method of forming a metal line in semiconductor device | |
| KR100691941B1 (en) | Method of manufacturing a capacitor in semiconductor device | |
| KR100268792B1 (en) | Capacitor forming method of semiconductor device | |
| KR20040059853A (en) | Method for manufacturing copper diffusion barrier | |
| KR100480576B1 (en) | Forming method of metal wiring in semiconductor device | |
| KR100283480B1 (en) | Metal wiring for semiconductor devices and its manufacturing method | |
| KR20020044859A (en) | Method of forming metal line in semiconductor device | |
| KR20010011307A (en) | Method for forming metal wire using zirconiumdiboride layer as diffusion barrier | |
| KR20010105885A (en) | Semiconductor fabrication method capable of preventing misalign between bottom electrode and storage node contact and oxidation of diffusion barrier layer | |
| KR100521445B1 (en) | Method for forming the semiconductor device | |
| KR100519375B1 (en) | Capacitor in semiconductor device and method for making the same | |
| KR20010027365A (en) | Method for manufacturing semiconductor device having barrier metal layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |