KR19980036135A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR19980036135A KR19980036135A KR1019960054632A KR19960054632A KR19980036135A KR 19980036135 A KR19980036135 A KR 19980036135A KR 1019960054632 A KR1019960054632 A KR 1019960054632A KR 19960054632 A KR19960054632 A KR 19960054632A KR 19980036135 A KR19980036135 A KR 19980036135A
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- South Korea
- Prior art keywords
- semiconductor device
- gate electrode
- manufacturing
- forming
- substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract description 21
- 238000004519 manufacturing process Methods 0.000 title abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 채널(Channel)의 오프셋(Offset) 길이를 일정하게 유지하도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which the offset length of a channel is kept constant.
이와 같은 본 발명의 반도체 소자의 제조방법은 기판을 준비하는 단계 ; 상기 기판상의 소정영역에 게이트 전극을 형성하는 단계 ; 상기 게이트 전극을 포함한 전면에 게이트 절연막 및 도전층을 형성하는 단계 ; 상기 게이트 전극의 일정영역을 도핑하는 단계 ; 상기 도전층내에 소오스/드레인 불순물 영역을 형성하는 단계를 포함하여 형성함을 특징으로 한다.Such a method of manufacturing a semiconductor device of the present invention comprises the steps of preparing a substrate; Forming a gate electrode in a predetermined region on the substrate; Forming a gate insulating film and a conductive layer on the entire surface including the gate electrode; Doping a predetermined region of the gate electrode; And forming a source / drain impurity region in the conductive layer.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 채널(Channel)의 오프셋(Offset)길이를 일정하게 유지하도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to maintain a constant offset length of a channel.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a - 도 1e는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 1a에 도시된 바와 같이 반도체 기판(11)상에 언더우프트(Undoped) 제 1 폴리 실리콘(12)을 형성하고, 상기 제 1 폴리 실리콘(12)의 전면에 게이트 도핑(Doping) 이온을 주입한다.As shown in FIG. 1A, an undoped first polysilicon 12 is formed on the semiconductor substrate 11, and gate doping ions are implanted into the entire surface of the first polysilicon 12. do.
도 1b에 도시된 바와 같이 상기 게이트 이온이 주입된 제 1 폴리 실리콘(12)상에 제 1 감광막(13)을 도포한 후, 노광 및 현상공정으로 패터닝(Patterning)하고, 상기 패터닝된 제 1감광막(13)을 마스크로 하여 상기 제 1 폴리 실리콘(12)을 선택적으로 제거하여 게이트 전극(12a)을 형성한다.As shown in FIG. 1B, the first photoresist layer 13 is coated on the first polysilicon 12 into which the gate ions are implanted, and then patterned by exposure and development processes, and the patterned first photoresist layer is formed. Using the 13 as a mask, the first polysilicon 12 is selectively removed to form the gate electrode 12a.
도 1c 에 도시된 바와 같이 상기 제 1 감광막(13)을 제거하고, 상기 게이트 전극(12a)을 포함한 전면에 게이트 절연막(14) 및 제 2 폴리 실리콘(15)을 형성한다. 이어, 상기 제 2 폴리 실리콘(15)상에 제 2 감광막(16)을 도포한 후, 노광 및 현상 공정으로 패터닝한다.As illustrated in FIG. 1C, the first photoresist layer 13 is removed, and a gate insulating layer 14 and a second polysilicon 15 are formed on the entire surface including the gate electrode 12a. Subsequently, the second photosensitive film 16 is coated on the second polysilicon 15 and then patterned by an exposure and development process.
도 1d 에 도시된 바와 같이 상기 패터닝된 제 2 감광막(16)을 마스크로 하여 전면에 소오스/드레인 불순물 영역을 형성하기 위하여 불순물 이온을 주입하므로써 상기 제 2 폴리 실리콘(15)내에 소오스 영역(17)과 드레인 영역(18)을 형성한다.As shown in FIG. 1D, a source region 17 is formed in the second polysilicon 15 by implanting impurity ions to form a source / drain impurity region on the entire surface using the patterned second photoresist layer 16 as a mask. And drain region 18 are formed.
도 1e 에 도시된 바와 같이 상기 제 2 감광막(16)을 제거한다.As shown in FIG. 1E, the second photosensitive layer 16 is removed.
그러나 이와 같은 종래의 반도체 소자의 제조방법에 있어서 다음과 같은 문제점이 있다.However, there is the following problem in the conventional method of manufacturing a semiconductor device.
즉, 소오스/드레인 불순물 영역을 형성하기 위하여 이온주입시 마스크의 미쓰얼라인(Misalign)에 의해서 오프셋(On/Off) 길이의 변화가 발생하기 때문에 반도체 소자의 온/오프(On/Off) 특성이 저하된다.In other words, the on / off length of the semiconductor device is changed due to misalignment of the mask during ion implantation in order to form source / drain impurity regions. Degrades.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 마스크의 얼라인에 관계없이 오프셋 길이를 일정하게 유지하도록 한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device to maintain a constant offset length regardless of alignment of a mask.
도 1a - 도 1e는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2a - 도 2d는 본 발명의 반도체 소자의 제조방법을 나타낸 공정단면도2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21 : 반도체 기판22 : 제 1 폴리 실리콘21 semiconductor substrate 22 first polysilicon
23 : 제 1 감광막22a : 게이트 전극23: first photosensitive film 22a: gate electrode
24 : 게이트 절연막25 : 제 2 폴리 실리콘24 gate insulating film 25 second polysilicon
26 : 제 2 감광막27 : 소오스 불순물 영역26 second photosensitive film 27 source impurity region
28 : 드레인 불순물 영역28: drain impurity region
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 기판을 준비하는 단계 ; 상기 기판상의 소정영역에 게이트 전극을 형성하는 단계 ; 상기 게이트 전극을 포함한 전면에 게이트 절연막 및 도전층을 형성하는 단계 ; 상기 게이트 전극의 일정영역을 도핑하는 단계 ; 그리고 상기 도전층내에 소오스/드레인 불순물 영역을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of preparing a substrate; Forming a gate electrode in a predetermined region on the substrate; Forming a gate insulating film and a conductive layer on the entire surface including the gate electrode; Doping a predetermined region of the gate electrode; And forming a source / drain impurity region in the conductive layer.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 2a - 도 2d 는 본 발명의 반도체 소자의 제조방법을 나타낸 공정단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
도 2a에 도시된 바와 같이 반도체 기판(21) 상에 언도우프트 제 1 폴리 실리콘(22)을 형성하고, 상기 제 1 폴리 실리콘(22) 상에 제 1 감광막(23)을 도포한 후, 노광 및 현상공정으로 패터닝(Patterning)한다.As shown in FIG. 2A, an undoped first polysilicon 22 is formed on the semiconductor substrate 21, a first photosensitive film 23 is coated on the first polysilicon 22, and then exposed. And patterning in a developing process.
도 2b에 도시된 바와 같이 상기 패터닝된 제 1 감광막(23)을 마스크로 하여 상기 제 1 폴리 실리콘(22)을 선택적으로 제거하여 게이트 전극(22a)을 형성하고, 상기 제 1 감광막(23)을 제거한다.As shown in FIG. 2B, the first polysilicon 22 is selectively removed using the patterned first photoresist layer 23 as a mask to form a gate electrode 22a, and the first photoresist layer 23 is formed. Remove
이어, 상기 게이트 전극(22a)을 포함한 전면에 게이트 절연막(24) 및 제 2 폴리 실리콘(25)을 형성한다. 그리고 상기 제 2 폴리 실리콘(25) 상에 제 2 감광막(26)을 도포한 후, 노광 및 현상공정으로 패터닝하고, 상기 패터닝된 제 2 감광막(26)을 마스크로 하여 높은 에너지(High Energy)로 불순물을 주입하여 상기 게이트 전극(22a)의 일부영역을 도핑(Doping)한다.Subsequently, a gate insulating film 24 and a second polysilicon 25 are formed on the entire surface including the gate electrode 22a. After coating the second photoresist layer 26 on the second polysilicon 25, the photoresist layer is patterned by an exposure and development process, and the patterned second photoresist layer 26 is used as a mask for high energy. An impurity is implanted to dope a portion of the gate electrode 22a.
도 2c 에 도시된 바와 같이 상기 제 2 감광막(26)을 마스크로 하여 소오스/드레인 불순물 영역을 형성하기 위한 불순물 이온을 주입하여 소오스 영역(27)과 드레인 영역(28)을 형성한다.As shown in FIG. 2C, the source region 27 and the drain region 28 are formed by implanting impurity ions for forming a source / drain impurity region using the second photoresist layer 26 as a mask.
도 2d에 도시된 바와 같이 상기 제 2 감광막(26)을 제거한다.As shown in FIG. 2D, the second photosensitive film 26 is removed.
이상에서 설명한 바와 같이 본 발명의 반도체 소자의 제조방법에 있어서 마스크의 미쓰얼라인(Misalign)에 의해 발생되는 오프셋(Offset) 길이의 변화를 방지하기 때문에 반도체 소자의 동작특성이 변하지 않고, 일정한 온/오프(On/Off) 전류비를 유지하는 효과가 있다.As described above, in the manufacturing method of the semiconductor device of the present invention, since the change in the offset length caused by misalignment of the mask is prevented, the operation characteristics of the semiconductor device do not change, and the constant ON / OFF It has the effect of maintaining the On / Off current ratio.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960054632A KR100236104B1 (en) | 1996-11-16 | 1996-11-16 | Semiconductor device making method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960054632A KR100236104B1 (en) | 1996-11-16 | 1996-11-16 | Semiconductor device making method |
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| Publication Number | Publication Date |
|---|---|
| KR19980036135A true KR19980036135A (en) | 1998-08-05 |
| KR100236104B1 KR100236104B1 (en) | 1999-12-15 |
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| KR1019960054632A KR100236104B1 (en) | 1996-11-16 | 1996-11-16 | Semiconductor device making method |
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| KR101088817B1 (en) * | 2009-06-26 | 2011-12-06 | 주식회사 하이닉스반도체 | Semiconductor device and manufacturing of method the same |
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