KR102040649B1 - Liquid crystal display and method of generating data enable signal - Google Patents

Liquid crystal display and method of generating data enable signal Download PDF

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KR102040649B1
KR102040649B1 KR1020120149846A KR20120149846A KR102040649B1 KR 102040649 B1 KR102040649 B1 KR 102040649B1 KR 1020120149846 A KR1020120149846 A KR 1020120149846A KR 20120149846 A KR20120149846 A KR 20120149846A KR 102040649 B1 KR102040649 B1 KR 102040649B1
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enable signal
data enable
low
liquid crystal
input
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KR1020120149846A
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Korean (ko)
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KR20140080250A (en
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김영호
이태욱
김제학
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엘지디스플레이 주식회사
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

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  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The present invention relates to a liquid crystal display and a method of generating a data enable signal thereof, wherein the timing controller of the liquid crystal display includes the nth row when the n-1th low section of the input data enable signal is larger than the n-2th low section. An internal data enable signal is generated using the result of dividing the -2 low interval by 1 / i. The timing controller generates the internal data enable signal by using the result of dividing the n−1 th low section by 1 / i when the n−1 th low section is equal to or less than the n−2 th low section.

Description

Liquid crystal display and its data enable signal generation method {LIQUID CRYSTAL DISPLAY AND METHOD OF GENERATING DATA ENABLE SIGNAL}

The present invention relates to a liquid crystal display for generating an internal data enable signal having a higher frequency than an input data enable signal, and a method of generating the data enable signal.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal cells of the liquid crystal display display an image by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode.

The data enable signal DE is input to the liquid crystal display. The high period of the data enable signal indicates an input timing of one line data in synchronization with one line data of the input image. One period of the data enable signal is one horizontal period. The timing controller TCON controls the operation timing of the data driver and the gate driver based on the data enable signal DE.

Recently, a liquid crystal display panel has been developed as a panel structure capable of reducing the number of data lines without reducing the number of pixels. Since the LCD has a small number of data lines, the number of output channels of the data driver can be reduced. Since the liquid crystal display panel must supply data to pixels through a relatively small number of data lines, the driving frequency is increased. To this end, the timing controller should generate an internal data enable signal having a high frequency based on the input data enable signal.

The data enable signal DE input to the timing controller may change a low section when an external input interface is changed, a channel is changed, or a 2D mode and a 3D mode are changed. In this case, the internal data enable signal generated by the timing controller is temporarily distorted. When the internal data enable signal is distorted, timing control signals of the data driver and the gate driver may be generated at abnormal timing temporarily, thereby causing the data driver and the gate driver to malfunction.

The present invention provides a liquid crystal display and a method for generating the data enable signal, which can generate an internal data enable signal generated in the timing controller at a normal timing even when the input data enable signal is changed.

A liquid crystal display device according to an embodiment of the present invention comprises: a liquid crystal display panel in which data lines and gate lines intersect and pixels are arranged in a matrix type; A data driver supplying a data voltage to the data lines; A gate driver sequentially supplying gate pulses synchronized with the data voltages to the gate lines; And generating an internal data enable signal having a frequency higher than that of the input data enable signal as a result of dividing the low period of the input data enable signal by 1 / i (i is 2 or 3) and generating the internal data enable signal. And a timing controller controlling the data driver and the gate driver based on the data driver.

The timing controller determines the n-2th low interval when the n−1th low interval (n is a positive integer of 2 or more) of the input data enable signal is greater than the n−2 low duration of the input data enable signal. The internal data enable signal is generated using the result divided by 1 / i.
The timing controller generates the internal data enable signal by using the result of dividing the n−1 th low section by 1 / i when the n−1 th low section is equal to or less than the n−2 th low section.

The method of generating a data enable signal of the liquid crystal display includes: comparing the n−1 low period of the input data enable signal with the n−2 low period of the input data enable signal; And generating the internal data enable signal by using the result of dividing the n-2th low interval by 1 / i when the n−1th low interval is larger than the n−2th low interval.

The liquid crystal display according to the present invention compares the n-2th low section to the n-1th low section of the input data enable signal, and when the n-2th low section is larger than the n-1th low section, the n-2th row An internal data enable signal is generated using the interval. As a result, the liquid crystal display of the present invention can generate the internal data enable signal at a normal timing even if the input data enable signal is changed.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
2 to 4 illustrate structures of various liquid crystal display panels.
5 is a waveform diagram illustrating an example in which an internal data enable signal is abnormally generated.
6 is a flowchart illustrating a method of generating a data enable signal according to an embodiment of the present invention.
7 is a waveform diagram illustrating an example of steps S2 to S4 in FIG. 6.
FIG. 8 is a waveform diagram illustrating an example of steps S5 and S6 of FIG. 6.
9 is a block diagram showing a data enable signal generation circuit in the timing controller of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a data driver 102, and a gate driver 103.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The LCD panel includes pixels arranged in a matrix by a cross structure of the data lines DL and the gate lines GL. Each of the pixels includes liquid crystal cells Clc.

A TFT array is formed on the lower glass substrate of the liquid crystal display panel 100. The TFT array includes liquid crystal cells Clc formed at the intersections of the data lines DL and the gate lines GL, TFTs connected to the pixel electrode 1 of the liquid crystal cells, and a storage capacitor Cst. do. The TFT array may be implemented in various forms as shown in FIGS. 2 to 4. The liquid crystal cells Clc are connected to the TFT and are driven by an electric field between the pixel electrodes 1 and the common electrode 2. A color filter array including a black matrix, a color filter, and the like is formed on the upper glass substrate of the liquid crystal display panel 100. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100 to form an alignment layer for setting a pre-tilt angle of the liquid crystal.

The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate.

The liquid crystal display panel 100 applicable to the present invention may be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 101 supplies the digital video data RGB of the input image input from the host system (HOST) 104 to the data driver 102. The timing controller 101 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, DE, and a clock CLK from the system board 104. The timing controller 101 uses an internal data enable signal DRD / TRD DE based on an input data enable signal DE to control an operation timing of the LCD panel 100 having the structure shown in FIGS. 3 and 4. Create The internal data enable signal DRD / TRD DE includes a DRD data enable signal (hereinafter referred to as “DRD DE”) and a TRD data enable signal (hereinafter referred to as “DRD DE”) as shown in FIGS. 5 to 9 according to the structure of the liquid crystal display panel. TRD DE ").

The timing controller 101 generates a data enable signal DRD / TRD DE suitable for driving the panel structure when the liquid crystal display panel 100 is implemented in a panel structure having a TFT array shown in FIG. 3 or 4. do. In detail, the timing controller 101 may determine that the n−1th low section (n is a positive integer of 2 or more) of the input data enable signal DE is greater than the n−2 low section of the input data enable signal DE. An internal data enable signal DRD / TRD DE is generated by using the result of dividing the n-2 low period by 1 / i (i is 2 or 3). The timing controller 101 enables the internal data using a result of dividing the n-1 low section by 1 / i when the n−1 low section of the input data enable signal DE is less than or equal to the n−2 low section. Generate the signal DRD / TRD DE. If each of the n-1th low period and the nth low period of the input data enable signal DE is greater than the n-2th low period, the timing controller 101 may set the nth low period of the input data enable signal DE. The internal data enable signal DRD / TRD DE is generated using the result of dividing by 1 / i.

The timing controller 101 generates timing control signals for controlling the operation timing of the data driver 102 and the gate driver 103 based on the internal data enable signal DRD / TRD DE and the clock signal. The timing control signals include a gate timing control signal for controlling the operation time of the gate driver 103, and a data timing control signal for controlling the operation timing of the data driver 102 and the vertical polarity of the data voltage. The timing controller 101 is connected to an EEPROM (Electrically Erasable Programmable Read-Only Memory) 105. The EEPROM 105 stores timing information of the timing control signal.

The gate timing control signal includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The gate start pulse GSP controls the operation start timing of the gate drive integrated circuit (IC) constituting the gate driver 103. The gate shift clock GSC is a clock signal commonly input to gate drive ICs to control the shift timing of the gate pulse. The gate output enable signal GOE controls the output timing of the gate drive ICs.

The data timing control signal includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, a source output enable signal SOE, a charge share control signal CS, and the like. The source start pulse SSP controls the data sampling start timing of the source drive ICs constituting the data driver 102. The source sampling clock SSC is a clock signal that controls the sampling timing of data in each of the source drive ICs. The source output enable signal SOE controls the output timing of the data driver 102. If the digital video data to be input to the data driver 102 is transmitted using mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

Each of the source drive ICs of the data driver 102 includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The source drive ICs latch the digital video data RGB under the control of the timing controller 101. Source drive ICs convert the digital video data RGB into analog positive / negative gamma compensation voltages to generate a data voltage and invert the polarity of the data voltage in response to the polarity control signal POL. The source drive ICs output data voltages to the data lines DL in response to the source output enable signal SOE.

The gate drive ICs of the gate driver 103 include a shift register and a level shifter. The gate driver 103 sequentially supplies gate pulses synchronized with the data voltage to the gate lines GL in response to the gate timing control signal.

The host system 104 may be implemented as any one of a television system, a home theater system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), and a phone system. The host system 104 scales the digital video data RGB of the input image according to the resolution of the liquid crystal display panel 100. The host system 14 transmits the timing signals Vsync, Hsync, DE, and MCLK together with the digital video data RGB of the input image to the timing controller 101.

2 to 4 are equivalent circuits showing various examples of the TFT array. 2 to 4 show a part of the TFT array. 2 to 4, D1 to D6 denote data lines, G1 to G6 denote gate lines, and LINE # 1 to LINE # 6 denote line numbers of pixel arrays, respectively.

The TFT array shown in FIG. 2 is a TFT array applied in most liquid crystal display devices. The data lines D1 to D6 and the gate lines G1 to G4 intersect with the TFT array. In this TFT array, each of the red subpixel R, the green subpixel G, and the blue subpixel B are disposed along the column direction. Each of the TFTs includes a pixel electrode of a liquid crystal cell in which data voltages from the data lines D1 to D6 are disposed on the left (or right) side of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G4. To feed. In the TFT array illustrated in FIG. 3, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels G along a row direction (or a line direction) orthogonal to the column direction. . When the resolution of the TFT array shown in FIG. 2 is M × N (M and N are each positive integers of 2 or more), M × 3 data lines and N gate lines are required. In M × 3, 3 is the number of subpixels included in one pixel.

The TFT array shown in FIG. 3 is a TFT array having a structure in which the number of data lines required at the same resolution is reduced by half compared to the TFT array shown in FIG. The driving frequency of this TFT array is twice as high as that of the TFT array shown in FIG. For this reason, the liquid crystal display panel having the TFT array shown in FIG. 3 is also referred to as a double rate driving (DRD) panel. Hereinafter, the DRD panel refers to the liquid crystal display panel shown in FIG. 3. The DRD panel can reduce the number of source drive ICs by half compared to the TFT array shown in FIG. 2. In the TFT array of the DRD panel, each of the red subpixel R, the green subpixel G, and the blue subpixel B is disposed along the column direction. In the TFT array of the DRD panel, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels G along a line direction perpendicular to the column direction. In the TFT array of the DRD panel, the liquid crystal cells adjacent to the left and right share the same data line and continuously charge the data voltage supplied in the time division manner through the data line. The liquid crystal cell and the TFT disposed on the left side of the data lines D1 to D4 are referred to as the first liquid crystal cell and the first TFT (T1), respectively. The structure of the TFT array will be described as a second liquid crystal cell and a second TFT (T2) as follows. The first TFT T1 supplies the data voltage from the data lines D1 to D4 to the pixel electrode of the first liquid crystal cell in response to the gate pulses from the odd gate lines G1, G3, G5, and G7. The gate electrode of the first TFT T1 is connected to the odd gate lines G1, G3, G5, and G7, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the first TFT T1 is connected to the pixel electrode of the first liquid crystal cell. The second TFT T2 supplies the data voltage from the data lines D1 to D4 to the pixel electrode of the second liquid crystal cell in response to the gate pulses from the even gate lines G2, G4, G6, and G8. The gate electrode of the second TFT T2 is connected to the even gate lines G2, G4, G6, and G8, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the second TFT T2 is connected to the pixel electrode of the second liquid crystal cell. The TFT array of the DRD panel requires (M × 3) / 2 data lines and 2N gate lines when the resolution is M × N.

The TFT array shown in FIG. 4 is a TFT array having a structure in which the number of data lines required at the same resolution is reduced by 1/3 compared to the TFT array shown in FIG. The driving frequency of this TFT array is three times higher than that of the TFT array shown in FIG. For this reason, the liquid crystal display panel having the TFT array shown in FIG. 4 may be referred to as a triple rate driving (TRD) panel. Hereinafter, the TRD panel refers to the liquid crystal display panel shown in FIG. 3. In the TFT array of the TRD panel, each of the red subpixel R, the green subpixel G, and the blue subpixel B is disposed along the line direction. One pixel in the TFT array of the TRD panel includes neighboring red subpixels R, green subpixels G, and blue subpixels G along the column direction. In the TFT array of the TRD panel, each of the TFTs transmits the data voltage from the data lines D1 to D6 to the left (or right) of the data lines D1 to D6 in response to the gate pulses from the gate lines G1 to G6. Supply to the pixel electrode of the liquid crystal cell arranged. The TFT array of the TRD panel requires M / 3 data lines and 3N gate lines when the resolution is M × N.

5 is a waveform diagram illustrating an example in which an internal data enable signal is abnormally generated. In FIG. 5, the input DE is a data enable signal input to the timing controller 101, and the DRD DE is a data enable signal required for driving the DRD panel as shown in FIG. 3. The TRD DE is a data enable signal required for driving the TRD panel as shown in FIG. 4. DRD DE and TRD DE are selected according to the structure of the liquid crystal display panel.

Referring to FIG. 5, one line period Ht of the input data enable signal DE may include a high logic section (hereinafter, referred to as a “high section”) that defines one line data section of an input image. It is divided into a high logic section (hereinafter referred to as a "low period") that defines a horizontal blank period without data.

In order to generate the DRD DE, the timing controller 101 first counts the row interval of the input DE every 2 clocks (CLK), measures 1/2 row intervals (a / 2, b / 2), and outputs the result. Temporarily stored in a register built into 101. The timing controller 101 generates the first high intervals 1a and 1e of the DRD DE in synchronization with the rising edge of the input DE, and thereafter, the half-low intervals aa and b / 2 of the input DE stored in the register are generated. As much as the first row interval (1b, 1f) of the DRD DE. The timing controller 101 reads the high section time of the DRD DE stored in the EEPROM 105 and generates first high sections 1a and 1e by that time. Subsequently, the timing controller 101 generates the second low period 1d of the DRD DE by maintaining the low period of the DRD DE signal until the rising edge of the next input DE after the second high period 1c of the DRD DE is generated. .

In order to generate the TRD DE, the timing controller 101 first counts the row section of the input DE every 3 clocks (CLK) to measure the 1/3 row section (a / 3, b / 3) of the input DE and the result. Is stored in a register. The timing controller 101 generates the first high intervals 2a and 2g of the TRD DE in synchronization with the rising edge of the input DE, and then stores the 1/3 low intervals (a / 3 and b / 3) of the input DE stored in the register. The first row sections 2b and 2h of the TRD DE are generated. The timing controller 101 reads the high section time of the TRD DE stored in the EEPROM 105 and generates first high sections 2a and 2g by that time. Subsequently, the timing controller 101 generates the second row of the TRD DE by one third row period (a / 3, b / 3) of the input DE stored in the register after generating the second high periods 2c, 2i of the TRD DE. Generate intervals 2d and 2j. Subsequently, after the third high period 2e of the DRD DE is generated, the timing controller 101 maintains the TRD DE signal in the low period until the rising edge of the next input DE to generate the third low period 2f of the TRD DE. do.

When the row period of the input DE is long as b, the first row period of the DRD DE may be lengthened by b / 2. In this case, the timing controller 101 generates a second high period of the DRD DE subsequent to the first low period of the DRD DE, which is the second row of the DRD DE because the next input DE is input within this second high period. No intervals occur In the case of the TRD DE, the timing controller 101 generates a third high section of the DRD DE subsequent to the second low section of the TRD DE, since the next input DE is input within the third high section, so 3 Low intervals do not occur. Therefore, when the row period of the input DE is changed, DRD DE and TRD DE are generated at abnormal timing. In the method of generating a data enable signal according to the present invention, as shown in FIG. 6, when the row period of the input DE is changed by selecting one of them by comparing the row periods of consecutive input DEs, an abnormal internal data enable signal DRD DE, TRD DE) to prevent occurrence.

6 is a flowchart illustrating a method of generating a data enable signal according to an embodiment of the present invention. The timing controller 101 generates a DRD DE or a TRD DE by the method of generating a data enable signal as shown in FIG. 6. 7 is a waveform diagram illustrating an example of steps S2 to S4 in FIG. 6. FIG. 8 is a waveform diagram illustrating an example of steps S5 and S6 of FIG. 6.

6 to 8, when a data enable signal generation method receives an input DE (S1), the low interval of the input DE is counted for every i clock CLK to measure 1 / i low interval of the input DE. To store the result in a register. Where i is 2 in DRD DE and 3 in TRD DE.

The method of generating a data enable signal compares consecutive row sections of the input DE and selects one of them. (S2) The n-th low section b (n-1) is an n-th low row section (S2). If a (n-2)) is greater than a (n-2) + X plus a predetermined constant value X, the n-2th row section a (n-2) is selected. The n-th low row a (n-2) is input to the timing controller 101 before the n-th low row b (n-1). If the n-th low row b (n-1) is equal to or less than a (n-2) + X, the n-th low row b (n-1) is selected.

The constant value X is a constant value of 0 or more and is selected according to the resolution of the liquid crystal display panel 100, the drive IC specification of the liquid crystal display panel 100, the DRD panel, and the TRD panel. This constant value X is stored in the EEPROM 105.

The data enable signal generation method generates a first high period 1a, 1e of the DRD DE in synchronization with the rising edge of the input DE, and then selects the n-2 low period a (n-2) selected in step S2. The first row periods 1b and 1f of the DRD DE are generated as much as the 1/2 period or the minimum row period HB of the DRD DE. (S3) The minimum row period of the DRD DE is stored in the EEPROM 105. The minimum row period of the DRD DE may be preset to a value greater than 0 and less than or equal to a / 2. Subsequently, the data enable signal generation method maintains the DRD DE signal in the low period until the rising edge of the next input DE after the second high period 1c of the DRD DE, thereby maintaining the second low period (1d, 1h) of the DRD DE. Occurs. 7 shows a method for generating DRD DE when b (n-1)> a (n-2) + X.

In the case of the TRD DE, the data enable signal generation method generates the first high periods 2a and 2g of the TRD DE in synchronization with the rising edge of the input DE in step S3, and then selects the n-2 low period selected in the step S2. The TRD DE first row sections 2b and 2h are generated by the half period of a (n-2)) or the minimum row section HB of the TRD DE. The minimum row period of TRD DE is stored in EEPROM 105. The minimum row section of TRD DE may be preset to a value greater than zero and less than a / 3. Subsequently, the data enable signal generation method generates one-third of the row period a (n-2) or b (n-1) selected in step S2 after generating the second high periods 2c and 2i of the TRD DE. The TRD DE second row periods 2d and 2j are generated by the period. Subsequently, in the method of generating a data enable signal, after the third high periods 2e and 2k of the TRD DE are generated, the TRD DE signal is kept low until the rising edge of the next input DE so that the third low period 2f of the TRD DE is maintained. , 2l). 7 shows a method for generating DRD DE when b (n-1)> a (n-2) + X.

If b (n-1) is less than or equal to a (n-2) + X in step S2, the method of generating a data enable signal is based on the n-1 low period b (n-1) of the input DE in step S3. In step S4, a row period of the DRD / TRD DE is generated.

If a low section larger than a (n-2) + X is continuously input from the input DE, the input DE is normally long. Therefore, the method of generating a data enable signal compares consecutive row sections in the input DE and selects the most recently input row section when row sections larger than a (n-2) + X are continuously input (S5).

In the example of FIG. 8, the n−1 and nth row sections b (n−1) and b (n) continuously input after the n−2th row section a (n-2) in the input DE ) Is greater than a (n-2) + X. In this case, the data enable signal generation method selects the n th row period b (n) most recently input.

In the method of generating a data enable signal, after generating the first high section 1i of the DRD DE in synchronization with the rising edge of the input DE, 1 / n of the nth low section b (n) selected in step S5 as shown in FIG. 8. The DRD DE first low period 1j is generated for two periods (S6). Then, the data enable signal generation method generates the DRD DE before the rising edge of the next input DE after generating the second high period 1k of the DRD DE. The signal maintains the low section to generate the second low section 11 of the DRD DE.

In the case of the TRD DE, the data enable signal generation method generates a first high section 2m of the TRD DE in synchronization with the rising edge of the input DE in step S3, and then selects the nth low section selected in step S5 as shown in FIG. The TRD DE first row period 2n is generated for one third of the period b (n). Subsequently, after the second high period 2o of the TRD DE is generated, the data enable signal generating method generates the TRD DE second low period (1/3) of the nth low period b (n) selected in step S5. 2p). Subsequently, the data enable signal generation method generates a third low period 2r of the TRD DE by maintaining the low period of the TRD DE signal after the third high period 2q until the rising edge of the next input DE.

9 is a block diagram illustrating a data enable signal generation circuit in the timing controller 101 of the present invention.

Referring to FIG. 9, the timing controller 101 includes first and second counters 91 and 92, a comparator 93, a selector 94, an internal data enable signal generator 95, and a timing control signal. Generation section 96 and the like.

The first counter 91 counts the n-th low row period of the input DE every i clock CLK, stores the count value in a register, and supplies the count value to the comparator 93. The first counter 91 resets the count value on the rising edge of the next input DE. Subsequently, the first counter 91 counts the nth low period of the input DE every i clock CLK, stores the count value in a register, and supplies the count value to the comparator 93.

The second counter 92 counts the n−1 th low section of the input DE every i clock CLK, stores the count value in a register, and supplies the count value to the comparator 93. The second counter 92 resets the count value on the rising edge of the next input DE. i is 2 in DRD DE and 3 in TRD DE. Subsequently, the second counter 92 counts the n + 1 low periods of the input DE every i clock CLK, stores the count value in a register, and supplies the count value to the comparator 93.

The comparator 93 compares the count values input from the first and second counters 91 and 92 so that the n-th low interval b (n-1) is the n-2th low interval a (n -2)), a predetermined signal value X is greater than a (n-2) + X plus a selection signal as the first logic value. The comparator 93 generates the selection signal as the first logic value when the nth row period b (n) is larger than a (n-2) + X. On the other hand, the comparator 93 removes the selection signal when the n−1th row section b (n−1) or the nth row section b (n) is less than or equal to a (n−2) + X. Occurs as 2 logical values. The first logic value may be high logic or 1 and the second logic value may be high logic or 0.

The selector 94 selects any one of the outputs of the first and second counters 91 and 92 in response to the selection signal from the comparator 93 and supplies it to the internal data enable signal generator 95. . If the selection signal is the first logic value, the count value of the n-th low section a (n-2) output from the first counter 91 is selected. On the other hand, if the selection signal is the second logic value, the count value of the n-th low interval b (n-1) output from the second counter 92 is selected. When the selection signal is input two or more times as the first logic value, the count value of the nth low period b (n) output from the second counter 92 is selected.

The internal data enable signal generator 95 generates a DRD DE or a TRD DE as shown in FIGS. 7 and 8 based on the row interval count value input through the selector 94. The timing control signal generator 96 counts the DRD DE or TRD DE input from the internal data enable signal generator 95 as a clock CLK and compares the count value with waveform information stored in the EEPROM 105. A gate timing control signal and a data timing control signal are generated.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

91, 92: counter 93: comparison unit
94: selector 95: internal data enable signal generator
96 timing control signal generator 100 liquid crystal display panel
101: timing controller 102: data driver
103: gate driver

Claims (8)

A liquid crystal display panel in which data lines and gate lines intersect and pixels are arranged in a matrix type;
A data driver supplying a data voltage to the data lines;
A gate driver sequentially supplying gate pulses synchronized with the data voltages to the gate lines; And
As a result of dividing the low period of the input data enable signal by 1 / i (i is 2 or 3), an internal data enable signal having a higher frequency than the input data enable signal is generated, and based on the internal data enable signal. A timing controller configured to control the data driver and the gate driver;
The timing controller,
If the n-1th low section of the input data enable signal (n is a positive integer of 2 or more) is larger than the n-2th low section of the input data enable signal, the n-2th low section is set to 1 / i. Generate the internal data enable signal using the divided result;
And the internal data enable signal is generated using the result of dividing the n-1 low section by 1 / i when the n−1 low section is equal to or less than the n−2 low section. . delete The method of claim 1,
The timing controller,
The internal data enable signal is generated by using the result of dividing the nth low section by 1 / i when each of the n-1th low section and the nth low section is larger than the n-2th low section. A liquid crystal display device. The method of claim 3, wherein
The timing controller
A first counter for counting the n-th low interval and the n-th low interval every i clock, and storing the count value in a register and outputting the count value;
A second counter for counting the n-th low interval and the n + 1th low interval every i clock, and storing the count value in the register and outputting the count value;
Comparing the count values input from the first and second counters, if the n−1 low period is greater than the n−2 low period, a selection signal is generated as a first logic value and the n−1 low period A comparator for generating the selection signal as a second logic value when the number is equal to or less than the n−2 low periods;
If the selection signal is a first logic value, a count value of the n-2 low intervals output from the first counter is selected; and if the selection signal is a second logic value, the n-th output from the second counter is selected. A selection unit for selecting a count value of one row period;
An internal data enable signal generator configured to generate the internal data enable signal based on a count value input from the selector; And
And a timing control signal generator for generating a timing control signal for controlling operation timing of the data driver and the gate driver based on the internal data enable signal. The method of claim 4, wherein
The comparison unit generates the selection signal as a first logic value when the nth row period is greater than the n−1th row period,
And the selector selects the count value of the nth row section when the selection signal is continuously input two or more times as the first logic value. A liquid crystal display panel in which data lines and gate lines intersect and pixels are arranged in a matrix type, a data driver supplying a data voltage to the data lines, and a gate pulse synchronized with the data voltages sequentially to the gate lines. A gate driver for supplying; And generating an internal data enable signal having a frequency higher than that of the input data enable signal as a result of dividing the low period of the input data enable signal by 1 / i (i is 2 or 3) and generating the internal data enable signal. In the data enable signal generation method of the liquid crystal display device including a timing controller for controlling the data driver and the gate driver based on,
Comparing the n−1th low section of the input data enable signal with n being a positive integer of 2 or more;
Generating the internal data enable signal by using the result of dividing the n-2th low interval by 1 / i when the n−1th low interval is larger than the n−2th low interval; And
Generating the internal data enable signal by using the result of dividing the n-1 low section by 1 / i when the n−1 low section is equal to or less than the n−2 low section. A method of generating a data enable signal of a liquid crystal display device. delete The method of claim 6,
Generating the internal data enable signal by using the result of dividing the nth low section by 1 / i when each of the n-1th low section and the nth low section is greater than the n-2th low section; And a data enable signal generation method of the liquid crystal display device.
KR1020120149846A 2012-12-20 2012-12-20 Liquid crystal display and method of generating data enable signal KR102040649B1 (en)

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