KR101964153B1 - Implementation of SiC Semiconductor Devices On SiC Insulation or Semi-insulation Substrate And Manufacturing Methods of The Same - Google Patents
Implementation of SiC Semiconductor Devices On SiC Insulation or Semi-insulation Substrate And Manufacturing Methods of The Same Download PDFInfo
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- KR101964153B1 KR101964153B1 KR1020140113006A KR20140113006A KR101964153B1 KR 101964153 B1 KR101964153 B1 KR 101964153B1 KR 1020140113006 A KR1020140113006 A KR 1020140113006A KR 20140113006 A KR20140113006 A KR 20140113006A KR 101964153 B1 KR101964153 B1 KR 101964153B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 127
- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 238000009413 insulation Methods 0.000 title description 3
- 238000005468 ion implantation Methods 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000002019 doping agent Substances 0.000 claims description 27
- 239000013078 crystal Substances 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 230000005669 field effect Effects 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910044991 metal oxide Inorganic materials 0.000 description 10
- 150000004706 metal oxides Chemical class 0.000 description 10
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000005094 computer simulation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a SiC semiconductor device having a high withstand voltage characteristic and a manufacturing method thereof. The SiC semiconductor device of the present invention includes an insulating or semi-insulating SiC substrate; A plurality of semiconductor regions formed in the SiC substrate; And electrodes formed on the SiC substrate and electrically connecting the plurality of doped regions. The SiC device according to the present invention forms a high-concentration semiconductor region on an insulating or semi-insulating SiC substrate. Exhibits high withstand voltage characteristics, and can be realized through an ion implantation process.
Description
The present invention relates to a SiC semiconductor device and a manufacturing method thereof, and more particularly to a SiC semiconductor device having a high withstand voltage characteristic and a manufacturing method thereof.
Silicon carbide (SiC) -based semiconductors (SiC), which exhibit superior characteristics over conventional silicon (Si) devices, can meet high power and switching characteristics due to their excellent properties such as high breakdown voltage, Devices are attracting attention.
A high voltage silicon carbide horizontal metal oxide semiconductor field effect transistor (LMOSFET) is formed by forming a silicon carbide epilayer on a silicon carbide (SiC) substrate and forming a necessary region through ion implantation . Such a typical LMOSFET fabrication process has a disadvantage in that an expensive epitaxial layer forming step must be separately performed and a leakage current to the substrate is large when a P-epi layer is formed on an N- substrate.
On the other hand, since a low-concentration epitaxial layer is used to obtain a high breakdown voltage even in a commonly used silicon-based high-voltage horizontal device, the current controllability is low due to high on- There is a problem that the area of a device becomes large when a 600V device used for a car is manufactured with a silicon base.
An object of the present invention is to provide a SiC-based semiconductor device having high breakdown voltage characteristics.
It is another object of the present invention to provide a method of manufacturing a SiC semiconductor device in an insulating or semi-insulating substrate.
It is another object of the present invention to provide a SiC semiconductor device having a high withstand voltage characteristic without the epitaxial layer of the present invention.
It is another object of the present invention to provide a method of manufacturing a SiC semiconductor device having a high withstand voltage characteristic by an ion implantation process.
An SiC semiconductor device according to an aspect of the present invention includes: an insulating or semi-insulating SiC substrate; A plurality of semiconductor regions formed in the SiC substrate; And electrodes formed on the SiC substrate and electrically connecting the plurality of doped regions. In this case, the SiC substrate preferably has an electric resistance of 10 5 Ω-cm or more, or 10 5 to 10 7 Ω-cm.
In addition, it is preferable that the SiC substrate is a single SiC single crystal body and does not include an epitaxial layer inside or on the substrate surface.
In the present invention, the plurality of semiconductor regions include a source region, a base region, a current passage region, and a drain region, and the plurality of semiconductor regions are a transverse metal oxide field effect transistor arranged substantially parallel to the SiC substrate surface .
In the present invention, the base region extends to the lower end of the source region between the source region and the current passage region to form a junction with the source region.
In the present invention, the junction depth of the current passage region is preferably larger or larger than the junction depth of the source region, and is preferably smaller than the junction depth of the base region.
According to another aspect of the invention, a source region, a drain region, a base region and a plurality of the semiconductor region and the electric resistance, including a
At this time, among the plurality of semiconductor regions, the current passage region forms a junction surface with the resistance region. The junction depth of the current passage region is equal to or greater than the junction depth of the source region, and the junction region of the base region and the junction region of the base region are connected to each other, Less than depth.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: providing an insulating or semi-insulating SiC substrate; Implanting a dopant into the SiC substrate to form a plurality of semiconductor regions; And forming an electrode for electrically connecting the plurality of doped regions on the SiC substrate.
In this case, the plurality of semiconductor regions may include a source region, a base region, a drain region, and a current path region, and the forming the plurality of semiconductor regions may include forming a base region by implanting a dopant of the second conductivity type ; Implanting a dopant of a first conductivity type to form a current path region; Implanting a dopant of a first conductivity type into the base region to form a source region; And implanting a dopant of the first conductivity type to form a drain region.
At this time, the source region and the drain region may be formed by one ion implantation process.
According to an embodiment of the present invention, the ion implantation depth of the current passage region is preferably 100 to 300 nm. In addition, the ion implantation depth of the source region is preferably 100 to 300 nm, and the ion implantation depth of the base region is preferably 200 to 1000 nm.
At this time, it is preferable that the dopant concentration in the current passage region is 10 15 to 10 17 / cm 3 and the dopant concentration in the base region is 10 16 to 10 18 / cm 3 .
According to one aspect of the present invention, a SiC element is formed by forming a high-concentration semiconductor region on an insulating or semi-insulating SiC substrate. It is possible to exhibit high withstand voltage characteristics. Further, since the breakdown voltage characteristics of the SiC semiconductor device of the present invention depend mainly on the length of the current passage region, the breakdown voltage characteristics can be controlled according to the length of the current passage region.
According to another aspect of the present invention, there is no need to perform a process of forming an epitaxial layer on a SiC substrate. Accordingly, it is possible to form a necessary semiconductor region only by an ion implantation process, It is possible.
Further, according to another aspect of the present invention, it is possible to realize a device with a very small size in order to maintain the same withstand voltage as that of the silicon-based device. For example, in the SiC semiconductor device according to the present invention, the length of the current path region can be realized at 1/10 of the level to maintain the same withstand voltage as that of the silicon semiconductor device, and the concentration of the current path region can be increased 10 times or more , The on-resistance can be lowered to 1/100 level compared with the silicon-based device.
1 is a cross-sectional view of a metal oxide field-effect transistor according to an embodiment of the present invention.
2 is a graph illustrating a simulation result of the breakdown voltage characteristics of a horizontal metal oxide semiconductor field effect transistor according to an embodiment of the present invention.
FIG. 3 is a graph illustrating a simulation result of the breakdown voltage characteristics according to the concentration and the length of the current doping region of a horizontal metal oxide semiconductor field effect transistor according to an embodiment of the present invention.
FIGS. 4 to 11 are schematic views illustrating steps of manufacturing a metal oxide field-effect transistor according to an embodiment of the present invention.
The present invention uses an insulating or semi-insulating substrate as the SiC substrate. The insulating or semi-insulating substrate has an electrical resistance of 10 5 Ω-cm or more. More specifically, the insulating substrate in the present invention means a substrate having a resistance of 10 7 Ω-cm or more. And the semi-insulating substrate has a resistance in the range of 10 5 to 10 7 Ω-cm. The resistance of the substrate can be controlled by controlling the content of impurities during SiC single crystal growth. Pure SiC single crystals, which typically contain unintended impurities, can be used as the SiC substrate of the present invention. Of course, in the present invention, it is needless to say that the insulating or semi-insulating substrate satisfies the above-mentioned resistance condition, but may include an intended impurity.
The SiC semiconductor device of the present invention comprises a plurality of semiconductor regions formed in the SiC substrate by ion implantation. In other words, the present invention does not implement a semiconductor region using a conventional epitaxial layer.
Generally, when a horizontal semiconductor device is fabricated using silicon, an epilayer length of 60 μm or more and an epilayer thickness of about 20 μm are required to obtain a breakdown voltage of about 600 V. However, when a SiC substrate is used, a breakdown voltage of 600 V or more can be obtained with only an epilayer length of 5 탆 and an epilayer thickness of 1 탆. Therefore, the SiC semiconductor device can realize the same withstand voltage characteristic even with a size of 1/10 as compared with the silicon semiconductor device. In addition, the SiC device can realize a doping concentration of 10 times or more. Therefore, the on-resistance can be lowered roughly to about 100 times that of the silicon semiconductor device.
Figure 1 illustrates, by way of example, a SiC semiconductor device implemented in accordance with an embodiment of the present invention.
The device of FIG. 1 illustrates a metal oxide semiconductor field effect transistor (MOSFET) 100. However, it will be understood by those skilled in the art that there is no difficulty in implementing a semiconductor device such as CMOS or the like according to the technical idea disclosed in the present invention.
The device of FIG. 1 has a plurality of semiconductor regions and a
In this embodiment, the SiC substrate may be a semi-insulating substrate having an electric resistance of 10 5 to 10 7 Ω-cm or an insulating substrate having a thickness of 10 7 Ω-cm. Thus, the electrical resistance of the
In the present invention, the plurality of semiconductor regions are formed in the SiC substrate. That is, the SiC substrate may be composed of a single single crystal body. Preferably, the SiC substrate can be implemented as a SiC single crystal wafer and does not require a separate material layer, such as an epitaxial layer, for the formation of the semiconductor region.
FET structure, the semiconductor regions include a
In the present invention, the
In the present invention, the
The magnitude of the withstand voltage that the FET device can withstand typically depends on the length (L CPL ) and the thickness of the
Therefore, in the SiC device of the present invention, the influence of the thickness of the current passage region on the breakdown voltage characteristics is reduced to negligible level. Therefore, the magnitude of the withstand voltage mainly depends on the length (L CPL ) of the
Thus, the thickness of the
According to an embodiment of the present invention, the junction depth of the
As shown, the
A
A
A
Hereinafter, the operation of the SiC LMOSFET of the present invention will be described. When a positive voltage equal to or greater than a predetermined value is applied to the
The SiC LMOSFET of the present invention has the following advantages. First, in the present invention, the current passage region may have a low thickness. Therefore, the ion implantation depth is limited to the vicinity of the SiC substrate surface. The SiC LMOSFET of the present invention exhibits a high breakdown voltage characteristic despite the thickness of the low current passing region, and the magnitude of the breakdown voltage depends entirely on the length of the current passing region. The current path region can be easily formed by ion implantation, and high concentration doping is facilitated. According to the present invention, as compared with a silicon-based device, it is possible to maintain the same withstand voltage even with a length of 1/10 and to increase the concentration of the current flowing region by more than ten times, It is possible to lower the on-resistance to 100 levels.
FIG. 2 is a computer simulation of the withstand voltage characteristics of a horizontal metal oxide semiconductor field effect transistor as shown in FIG. 1 using a semi-insulating substrate having an electrical resistance of 10 7 ? -Cm according to an embodiment of the present invention .
For the computer simulation, Silvaco's TCAD tool was used. The doping concentration and junction depth of each region used in computer simulation are as follows.
- P-base concentration and junction depth: 3 × 10 17 / cm 3 , 0.7 μm
- N + source / drain concentration and junction depth: 3 x 10 20 / cm 3 , 0.2 um
- Concentration and junction depth in current path region: 1 × 10 15 / cm 3 ~ 1 × 10 17 / cm 3 , 0.2 μm
- current passage area length: 5 to 20um in increments of 5um
Referring to FIG. 2, the breakdown voltage characteristic of the SiC device changes according to the length of the current passage region. The SiC device, which is computationally simulated, shows a high withstand voltage characteristic of about 100 V per 1 mu m. Considering the fact that a silicon semiconductor-based horizontal metal oxide semiconductor field effect transistor requires a length of about 10 占 퐉 in order to obtain an insulation withstand voltage of 100V, the MOSFET of the present invention has a breakdown voltage of 10 times or more Lt; / RTI >
FIG. 3 is a graph showing a simulation result of the breakdown voltage characteristics according to the concentration and the length of the current doping region of the SiC LMOSFET according to an embodiment of the present invention.
FIG. 3 shows a simulation result of the breakdown voltage characteristics of the Si LMOSFET for comparison with the embodiment of the present invention. The Si LMOSFET has an epilayer thickness of 5 μm and an epilayer length of 20 μm. The doping concentration and junction depth of each region are as follows.
- P-base concentration and junction depth: 3 × 10 17 / cm 3 , 2.5 μm
- N + source / drain concentration and junction depth: 1 x 10 20 / cm 3 , 1.0 um
As shown in FIG. 3, the Si LMOSFET exhibits a higher withstand voltage characteristic of the SiC LMOSFET despite the thickness of the epitaxial layer being very thick.
In the case of the SiC LMOSFET, the thickness of the current passage region is 0.2 탆 and the length is 20 탆, the withstand voltage of 1,700 V is obtained when the concentration of the current passage region is 2 10 16 / cm 2 , while in the case of the Si LMOSFET, Only the internal pressure change of about 200 V is shown. In particular, when the concentration is 2 × 10 16 / cm 2 , which is the same as that of the SiC LMOSFET, the breakdown voltage characteristic is about 40V.
Hereinafter, a method of manufacturing a SiC LMOSFET according to an embodiment of the present invention will be described with reference to the drawings.
Referring to FIG. 4, a first ion implantation mask M1 is formed to open a predetermined region of the
Next, as shown in FIG. 5, a second ion implantation mask M2 opening a predetermined portion of the
Similarly, as shown in Fig. 6, a source region and a drain region are formed by an ion implantation process (e, f). That is, a third ion implantation mask M3 is formed and N or P ions of the first conductivity type are implanted. At this time, the dopant concentration and the ion implantation depth are preferably in the range of 10 18 to 10 21 / cm 3 and 100 nm to 300 nm, respectively.
Additionally, in the present invention, a step of doping a part of the base region at a high concentration may be added. This
As described above, heat treatment is performed at a high temperature for electrical activation of ions implanted in the ion implantation processes. The heat treatment temperature and time can be appropriately selected. Illustratively, a heat treatment within the range of 10 minutes to 1 hour at a temperature of 1600 to 1800 占 폚 can be performed.
The ion implantation process described above exemplifies one embodiment of the present invention. It will be apparent to those skilled in the art that the sequence of each ion implantation process and the ion implantation conditions can be easily changed.
Next, an
Next, an etch mask M5 is formed on the
After the etching mask M5 is removed, a conductive metal layer filling the opening is formed. As shown in FIG. 10, the conductive metal layer is patterned to form the
A
Then, as shown in FIG. 11 (n), a
100
112
122 high
132
150
160
170
190 passivation layer
M1, M2, M3, M4, M5 Mask
Claims (27)
A plurality of semiconductor regions and a resistance region formed in the single crystal SiC substrate; And
And electrodes formed on the monocrystalline SiC substrate for electrically connecting the plurality of semiconductor regions,
Wherein the plurality of semiconductor regions include a source region, a base region, a current path region, and a drain region,
The dopant concentration of the source region is 10 18 to 10 21 / cm 3 ,
The dopant concentration of the base region is 10 16 to 10 18 / cm 3 ,
The dopant concentration in the current passage region is 10 15 / cm 3 to 10 17 / cm 3 ,
Wherein the resistance region has an electrical resistance of 10 5 Ω-cm or more.
Wherein the monocrystalline SiC substrate has an electrical resistance of 10 5 to 10 7 Ω-cm.
Wherein the plurality of semiconductor regions are arranged substantially parallel to the surface of the SiC substrate.
And the base region extends to the lower end of the source region between the source region and the current path region to form a junction with the source region.
And the junction depth of the current passage region is equal to or larger than the junction depth of the source region.
And the junction depth of the current passage region is smaller than the junction depth of the base region.
Wherein one side of the source region is doped with a dopant of a conductivity type different from that of the source region and further comprises a doping region having a higher concentration than the base region.
And an oxide film and a gate formed on the oxide film on the base region.
Wherein the semiconductor element is a MOSFET or a CMOS.
Wherein the current path region forms a junction surface with the resistance region.
Implanting a dopant into the single crystal SiC substrate to form a plurality of semiconductor regions and a resistance region; And
Forming an electrode for electrically connecting the plurality of semiconductor regions on the single crystal SiC substrate,
Wherein the plurality of semiconductor regions include a source region, a base region, a current path region, and a drain region,
The dopant concentration of the source region is 10 18 to 10 21 / cm 3 ,
The dopant concentration of the base region is 10 16 to 10 18 / cm 3 ,
The dopant concentration in the current passage region is 10 15 / cm 3 to 10 17 / cm 3 ,
Wherein the resistance region has an electrical resistance of 10 5 Ω-cm or more.
Wherein forming the plurality of semiconductor regions comprises:
Implanting a dopant of a second conductivity type to form a base region;
Implanting a dopant of a first conductivity type to form a current path region;
Implanting a dopant of a first conductivity type into the base region to form a source region; And
And implanting a dopant of a first conductivity type to form a drain region.
Wherein the source region and the drain region are formed by one ion implantation process.
Wherein the ion implantation depth of the current passage region is 100 to 300 nm.
Wherein the ion implantation depth of the base region is 200 to 1000 nm.
Wherein the ion implantation depth of the source region is 100 to 300 nm.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020140113006A KR101964153B1 (en) | 2014-08-28 | 2014-08-28 | Implementation of SiC Semiconductor Devices On SiC Insulation or Semi-insulation Substrate And Manufacturing Methods of The Same |
| PCT/KR2014/012875 WO2016032069A1 (en) | 2014-08-28 | 2014-12-26 | Sic semiconductor element implemented on insulating or semi-insulating sic substrate and method for manufacturing same |
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| KR1020140113006A KR101964153B1 (en) | 2014-08-28 | 2014-08-28 | Implementation of SiC Semiconductor Devices On SiC Insulation or Semi-insulation Substrate And Manufacturing Methods of The Same |
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| KR101964153B1 true KR101964153B1 (en) | 2019-04-03 |
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| KR102381395B1 (en) * | 2017-09-18 | 2022-04-01 | 한국전기연구원 | Implementation of SiC Semiconductor Devices On 6H-SiC Insulation or Semi-insulation Substrate And Manufacturing Methods of The Same |
| CN108417623B (en) * | 2018-05-11 | 2021-02-02 | 安徽工业大学 | IGBT (insulated Gate Bipolar transistor) containing semi-insulating region and preparation method thereof |
| CN108417624B (en) * | 2018-05-11 | 2021-02-02 | 安徽工业大学 | IGBT for improving short circuit robustness and preparation method thereof |
| KR20230093791A (en) * | 2021-12-20 | 2023-06-27 | 한국전기연구원 | Implementation of SiC Semiconductor Devices On SiC Insulation or Semi-insulation Substrate And Manufacturing Methods of The Same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020070412A1 (en) * | 1999-03-31 | 2002-06-13 | Heinz Mitlehner | Integrated semiconductor device having a lateral power element |
| JP2004253427A (en) * | 2003-02-18 | 2004-09-09 | Matsushita Electric Ind Co Ltd | Silicon carbide semiconductor element |
| US20100276703A1 (en) * | 2007-03-16 | 2010-11-04 | Nissan Motor Co., Ltd. | Silicon carbide semiconductor device |
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| KR19980054472U (en) * | 1996-12-31 | 1998-10-07 | 박병재 | Shock absorber mounting structure |
| JP5995435B2 (en) * | 2011-08-02 | 2016-09-21 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020070412A1 (en) * | 1999-03-31 | 2002-06-13 | Heinz Mitlehner | Integrated semiconductor device having a lateral power element |
| JP2004253427A (en) * | 2003-02-18 | 2004-09-09 | Matsushita Electric Ind Co Ltd | Silicon carbide semiconductor element |
| US20100276703A1 (en) * | 2007-03-16 | 2010-11-04 | Nissan Motor Co., Ltd. | Silicon carbide semiconductor device |
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