KR101897641B1 - Method for manufacturing power module package and the power module package using the same - Google Patents

Method for manufacturing power module package and the power module package using the same Download PDF

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Publication number
KR101897641B1
KR101897641B1 KR1020160160690A KR20160160690A KR101897641B1 KR 101897641 B1 KR101897641 B1 KR 101897641B1 KR 1020160160690 A KR1020160160690 A KR 1020160160690A KR 20160160690 A KR20160160690 A KR 20160160690A KR 101897641 B1 KR101897641 B1 KR 101897641B1
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South Korea
Prior art keywords
power module
module package
ceramic layer
chip
layer
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KR1020160160690A
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Korean (ko)
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KR20180060791A (en
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조한신
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현대오트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3164—Partial encapsulation or coating the coating being a foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The present invention provides a method of manufacturing a ceramic substrate, comprising: preparing a substrate having a ceramic layer and a metal circuit pattern formed on a lower surface of the ceramic layer; Forming an inner space by removing at least a portion of the ceramic layer to mount chips and spacers; Mounting chips and spacers in the internal space; Performing wire bonding to electrically connect the chip and the metal circuit pattern; Bonding a lead frame to a signal terminal and a terminal terminal of the substrate, respectively; Molding the inner space between the chip and the ceramic layer to surround the outer circumferential surface of the substrate; Forming a metal layer on the spacer and the molding part; And forming a protective layer on the metal layer, and a power module package implemented using the method.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a power module package and a power module package using the same,

The present invention relates to a method of manufacturing a power module package and a power module package using the same, and more particularly, to a method of manufacturing a power module package with improved cooling performance and a power module package using the same.

The power module is applied to the inverter (HEV, EV, PHEV, etc.) for eco-friendly automobiles. It simplifies the internal structure of the module and improves the performance of the module through a robust structure.

Recently, in order to improve the performance of the power module, a two-sided cooling module was constructed using two ceramic insulating substrates, and the upper and lower parts were electrically connected by using a metal pattern facing the chip and a metal block formed in the middle. Have been studied extensively for structures filled with epoxy molding compound (EMC).

However, when such a structure is subjected to a warpage thermal shock test while performing a high temperature soldering process using two asymmetric ceramic insulating substrates, the stress can concentrate on the chip while being heated at a high temperature and a low temperature, thereby shortening the life. The epoxy molding compound which is a material to be filled between the two sheets of insulating substrates may have a high thermal resistance because the thermal conductivity is not very good. In addition, the epoxy molding compound has a property of absorbing moisture well, which can induce peeling by moisture absorption in a high temperature and high humidity test. As a result, when the epoxy molding compound is filled in the entire module, there is a possibility that the thermal shrinkage test may peel off the interface from the periphery of the chip due to internal shrinkage expansion of the module.

It is an object of the present invention to provide a method of manufacturing a power module package capable of improving thermal performance and reducing the weight and size of the module and a power module package using the same. . However, these problems are exemplary and do not limit the scope of the present invention.

According to one aspect of the present invention, a method of manufacturing a power module package is provided. The method includes the steps of: preparing a ceramic layer and a substrate on which a metal circuit pattern is formed on the lower surface of the ceramic layer; Forming an inner space by removing at least a portion of the ceramic layer to mount chips and spacers; Mounting chips and spacers in the internal space; Performing wire bonding to electrically connect the chip and the metal circuit pattern; Bonding a lead frame to a signal terminal and a terminal terminal of the substrate, respectively; Molding the inner space between the chip and the ceramic layer to surround the outer circumferential surface of the substrate; Forming a metal layer on the spacer and the molding part; And forming a protective layer on the metal layer.

In the method of manufacturing the power module package, the molding may be performed by using an epoxy molding compound (EMC), the epoxy molding compound flows into the plurality of holes of the area where the chip is mounted, .

In the method of manufacturing the power module package, the step of forming the metal layer may include forming the metal layer on the spacer and the molding part using a sputtering method or an electrolytic plating method.

In the method of manufacturing the power module package, an inner space between the spacer and the ceramic layer may be filled with a non-conductive epoxy in the vicinity of the area where the spacer is mounted.

According to another aspect of the present invention, a power module package is provided. Wherein the power module package includes a ceramic layer at least a portion of which is removed to form an inner space, and a metal circuit pattern formed on a lower surface of the ceramic layer; A chip surrounded by the ceramic layer and mounted on the metal circuit pattern; A spacer formed on the chip; A molding part formed in the inner space between the chip and the ceramic layer or between the spacer and the ceramic layer; And a metal layer formed on the ceramic layer, the molding part, and the spacer.

In the power module package, the chip and the metal circuit pattern may be connected to each other by wire bonding.

In the power module package, a lead frame may be bonded to a signal terminal provided on both sides of the metal circuit pattern and a terminal terminal.

The power module package may include a lower surface of the metal circuit pattern and a protection layer formed on the upper surface of the metal layer to insulate the metal circuit pattern from the metal layer.

In the power module package, the protective layer may include a polyimide series material.

In the power module package, the ceramic layer may include any one of materials of aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), and alumina (Al 2 O 3 ).

In the power module package, the metal circuit pattern and the metal layer may include copper (Cu) or aluminum (Al) -based materials.

In the power module package, a plurality of holes may be formed on an upper surface of the substrate so that the chip and the spacer may be mounted.

According to one embodiment of the present invention as described above, a power module package can be implemented using a method of manufacturing a power module package that improves thermal performance, reduces the weight and size of the module, is inexpensive, have. Of course, the scope of the present invention is not limited by these effects.

1 is a cross-sectional view of a power module package implemented by a method of manufacturing a power module package according to an embodiment of the present invention.
2 to 8 are top views schematically showing a method of manufacturing a power module package according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, Is provided to fully inform the user. Also, for convenience of explanation, the components may be exaggerated or reduced in size.

1 is a cross-sectional view of a power module package implemented by a method of manufacturing a power module package according to an embodiment of the present invention.

Referring to FIG. 1, a power module package 1000 according to an embodiment of the present invention includes a ceramic layer 110, which is at least partially removed to form an inner space, and a metal circuit pattern 120 A chip 200 surrounded by the ceramic layer 110 and mounted on the metal circuit pattern 120; a spacer 300 formed on the chip 200; a chip 200; The molding part 500 formed in the inner space between the ceramic layer 110 or the spacer 300 and the ceramic layer 110 and the upper surface of the ceramic layer 110 and the upper surface of the molding part 500 and on the spacer 300 And a metal layer 600 formed thereon.

The substrate 100 of the power module package 1000 according to an embodiment of the present invention may include a ceramic layer 110 and a metal circuit pattern 120. The ceramic circuit board 110 may include any one of aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), and alumina (Al 2 O 3 ) Or an aluminum (Al) -based material. A plurality of holes (not shown) may be provided on the upper surface of the substrate 100 so that the chips 200 and the spacers 300 can be mounted.

The substrate 100 may be a DBC (Direct Bonder Copper) substrate. For example, the DBC substrate is formed by depositing copper on a ceramic PCB substrate. The DBC substrate is formed by etching at least a part of the ceramic layer of the DBC substrate to form an internal space, and the chip 200 and the spacer 300 are formed in the internal space. Can be mounted. The DBC substrate may have a plurality of holes at positions where the chips 200 and the spacers 300 are mounted. The heat dissipation characteristics can be further improved through the plurality of holes and the bonding strength between the substrate 100 and the chip 200 or between the substrate 100 and the spacer 300 can be further improved by the plurality of holes .

In the power module package 1000 according to an embodiment of the present invention, the chip 200 and the metal circuit pattern 120 may be electrically connected to each other by wire bonding. The lead frame 400 may be bonded to a signal terminal (not shown) and a terminal terminal (not shown) provided on both sides of the metal circuit pattern 120, respectively.

The metal layer 600 may include the same material as the metal circuit pattern 120, that is, a material of copper (Cu) or aluminum (Al). The metal circuit pattern 120 and the metal layer 600 may include a lower surface of the metal circuit pattern 120 and a protective layer 700 formed on the upper surface of the metal layer 600 to insulate the metal circuit pattern 120 from the outside. The protective layer 700 may include a polyimide series material. Here, the protective layer formed on the lower surface of the metal circuit pattern 120 can be understood as a first protective layer 710, and the protective layer formed on the upper surface of the metal layer 600 can be understood as a second protective layer 720 .

The method of manufacturing the power module package of the present invention will be described in detail below with reference to FIGS. 2 to 8.

2 to 8 are top views schematically showing a method of manufacturing a power module package according to an embodiment of the present invention. FIG. 2 (a) is a schematic top view of a substrate according to an embodiment of the present invention, and FIG. 2 (b) is a view schematically showing a bottom surface of a substrate according to an embodiment of the present invention. to be.

1, 2, and 3, a substrate 100 may be prepared. The substrate 100 may include any one of materials of aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), and alumina (Al 2 O 3 ), for example. 2A and 2B, at least a part of the substrate 100 is removed to form a ceramic layer 110 which forms an inner space and a metal circuit pattern 120 ). The first passivation layer 710 may be insulated and coated on the lower surface of the metal circuit pattern 120. The metal circuit pattern 120 may include a signal terminal 122 and a terminal terminal 124 so as to exchange signals with the outside.

The chip 200 and the spacer 300 may be mounted on the inner space. At this time, a plurality of holes (not shown) may be provided on the upper surface of the substrate 100 so that the chips 200 and the spacers 300 can be mounted. The plurality of holes may be formed by removing at least a portion of the ceramic layer 110, and may form an inner space surrounded by the ceramic layer 110.

The upper surface of the metal circuit pattern 120 formed on the lower surface of the ceramic layer 110 is exposed so that the chip 200 and the spacer 300 can be mounted by removing at least a part of the ceramic layer 110, The inner space formed of the circuit pattern 120 and the ceramic layer 110 can be formed. Here, as a method of removing the ceramic layer 110, for example, a method such as etching or patterning can be used, and these methods are already known, and a detailed description thereof will be omitted.

On the other hand, when the metal circuit pattern 120 is formed of a lead frame, the ceramic layer 110 may be formed on the metal circuit pattern 120, and the ceramic layer 110 may be removed as described above. Alternatively, a part of the upper surface of the metal circuit pattern 120 may be exposed from the step of forming the ceramic layer 110 on the metal circuit pattern 120. And the order of processes may vary depending on the type, size, and shape of the substrate.

Further, the chip 200 and the spacer 300 can be mounted in the internal space. In this case, the chip 200 and the spacer 300 may be formed by a vacuum soldering method. The vacuum soldering method is a well known technique, and a detailed description thereof will be omitted.

The first solder preform 130 may be formed on the lower surface of the inner space of the substrate 100 and the chip 200 may be positioned on the first solder preform 130 to perform soldering. The spacer 300 may be formed on the first solder preform 130 such as the chip 200. The second solder preform 140 may be formed on the top surface of the chip 200 and the second solder preform 140 , And soldering can be performed.

1 and 4, after the chip 200 and the spacer 300 are mounted, the metal circuit pattern 120 formed on the lower surface of the substrate 100 and the chip 200 are electrically Respectively. If the metal circuit pattern 120 formed on the lower surface of the substrate 100 is exposed upward as the ceramic layer 110 is removed, the chip 200 is electrically connected to a portion of the upper surface of the metal circuit pattern 120, 150 may be bonded and electrically connected. On the other hand, if the metal circuit pattern 120 is not exposed upward, the chip 200 may be wire-bonded to the signal terminal 122 and electrically connected to each other.

Thereafter, a nonconductive epoxy is used in the vicinity of the area where the chip 200 and the spacer 300 are mounted, so that the internal space between the chip 200 and the ceramic layer 110 or between the spacer 300 and the ceramic layer 110 It can be filled with a dispenser in the inner space of the container.

1, 5, and 6, the lead frame 400 may be bonded to the signal terminal 122 and the terminal terminal 124, respectively. The method of bonding the lead frame 400 is similar to the method of mounting the chip 200 and the spacer 300 by using a solder preform (not shown) in the signal terminal 122 and a signal lead frame The terminal lead frame 420 can be bonded to the terminal terminal 124 by using a solder preform (not shown).

Thereafter, an epoxy molding compound (EMC) is used to flow into a plurality of holes of the region where the chip 200 is mounted to mold the inside of the substrate 100, and a space between the chip 200 and the ceramic layer 110 A space between the spacer 300 and the ceramic layer 110 may be embedded to form the molding part 500. Since the molding part 500 is formed not only by filling the space of the chip 200 and the spacer 300, but also surrounding the periphery of the substrate 100, the bonding property with the substrate can be improved .

Particularly, since the epoxy molding compound filled in the substrate 100 performs only a gap fill function, it is possible to minimize the problem caused by contamination that may occur in the module assembly process, and in the thermal shock test, 100 may serve as a core to reduce thermal deformation and enhance reliability.

Referring to FIGS. 1, 7 and 8, a metal layer 600 may be formed on the upper surface of the spacer 300 and the molding part 500. The metal layer 600 may be formed by a sputtering method or an electrolytic plating method. Here, since the sputtering method or the electrolytic plating method is a well-known technique, a detailed description thereof will be omitted.

For example, the first metal layer 610 and the second metal layer 620 may be formed by a sputtering method using a mask. At this time, the first metal layer 610 and the second metal layer 620 are formed to be insulated from each other and can operate as a power module. For example, in order to improve the bonding strength between the metal layer 600 and the substrate 100 and between the electrodes in the structure below, the metal layer 600 may be deposited by a sputtering method, or the metal layer 600 may be formed thickly using an electrolytic plating method.

The second passivation layer 720 may be formed on the metal layer 600 for the same purpose as the first passivation layer 710 formed on the lower surface of the substrate 100. [ The second protective layer 720 is formed not only to protect the metal layer 600 but also over the entire surface of the molding part 500, the first metal layer 610 and the second metal layer 620, ). ≪ / RTI >

In order to understand the advantageous effects of the manufacturing method of the power module package according to the technical idea of the present invention, a comparative example of the present invention will be described.

The power module package according to the comparative example of the present invention may include a structure in which a double-sided cooling module is formed using two insulating substrates and an interior thereof is filled with an epoxy molding compound. In this case, when the soldering process is performed at a high temperature, the stress is concentrated on the chip while moving between the high temperature state and the low temperature state, thereby shortening the life time. In addition, the thermal conductivity is not very good, and if the entire interior of the module is filled with the epoxy molding compound, the interface may peel off around the chip due to internal shrinkage expansion.

In the present invention, one insulating substrate is used to replace a part of the epoxy molding compound in the power module package according to the comparative example with a ceramic material having excellent thermal conductivity, and an insulating coating material The present invention can provide a power module package capable of improving thermal performance (reducing thermal resistance), reducing thermal deformation and improving reliability, and minimizing interfacial peeling of a mold, and a manufacturing method thereof.

In addition, since a double-sided cooling module can be implemented with a single ceramic substrate, the thickness of the module can be reduced, the weight of the module can be reduced, the manufacturing cost can be reduced, and the thermal conductivity can be improved by about 80 to 150 times By forming the inside of the module by using the material, it is possible to improve the thermal performance and provide a highly effective power module package.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: substrate
110: Ceramic layer
120: metal circuit pattern
122: Signal terminal
124: Terminal terminal
130: first solder preform
140: second solder preform
150: wire
200: chip
300: Spacer
400: Lead frame
410: Signal lead frame
420: Terminal lead frame
500: molding part
600: metal layer
610: First metal layer
620: second metal layer
700: protective layer
710: first protective layer
720: second protective layer
1000: Power module package

Claims (12)

Preparing a substrate including a ceramic layer and a metal circuit pattern formed on a lower surface of the ceramic layer;
Forming an inner space by etching and removing at least a portion of the ceramic layer to mount the chip and the spacer;
Mounting chips and spacers in the internal space;
Performing wire bonding to electrically connect the chip and the metal circuit pattern;
Bonding a lead frame to a signal terminal and a terminal terminal of the substrate, respectively;
Molding the inner space between the chip and the ceramic layer to surround the outer circumferential surface of the substrate;
Forming a metal layer on the spacer and the molding part; And
Forming a protective layer on the metal layer;
/ RTI >
A method of manufacturing a power module package. The method according to claim 1,
Wherein the molding comprises:
Using an epoxy molding compound (EMC), wherein the epoxy molding compound flows into a plurality of holes of the region where the chip is mounted to mold the inside of the substrate.
A method of manufacturing a power module package. The method according to claim 1,
Wherein forming the metal layer includes forming the metal layer on the spacer and the molding portion using a sputtering method or an electrolytic plating method.
A method of manufacturing a power module package. The method according to claim 1,
And filling the internal space between the spacer and the ceramic layer using a nonconductive epoxy in the vicinity of the region where the spacer is mounted.
A method of manufacturing a power module package. A ceramic layer forming an inner space formed by removing at least a part of the ceramic layer and a substrate having a metal circuit pattern formed on a lower surface of the ceramic layer;
A chip surrounded by the ceramic layer and mounted on the metal circuit pattern;
A spacer formed on the chip;
A molding part for filling the space between the chip and the ceramic layer or between the spacer and the ceramic layer by filling the internal space with a nonconductive epoxy; And
A metal layer formed on the ceramic layer, the molding part, and the spacer;
/ RTI >
Power module package. 6. The method of claim 5,
Wherein the chip and the metal circuit pattern are connected to each other by wire bonding,
Power module package. 6. The method of claim 5,
A signal terminal provided on both sides of the metal circuit pattern and a lead frame bonded to the terminal terminal,
Power module package. 6. The method of claim 5,
And a protective layer formed on the lower surface of the metal circuit pattern and the upper surface of the metal layer to insulate the metal circuit pattern from the metal layer.
Power module package. 9. The method of claim 8,
Wherein the protective layer comprises a polyimide series material,
Power module package. 6. The method of claim 5,
Wherein the ceramic layer comprises any one of aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), and alumina (Al 2 O 3 )
Power module package. 6. The method of claim 5,
Wherein the metal circuit pattern and the metal layer are made of copper (Cu) or aluminum (Al)
Power module package. 6. The method of claim 5,
Wherein a plurality of holes are provided on an upper surface of the substrate so that the chip and the spacer can be mounted,
Power module package.
KR1020160160690A 2016-11-29 2016-11-29 Method for manufacturing power module package and the power module package using the same KR101897641B1 (en)

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KR102163662B1 (en) * 2018-12-05 2020-10-08 현대오트론 주식회사 Dual side cooling power module and manufacturing method of the same
KR102264132B1 (en) * 2019-06-14 2021-06-11 제엠제코(주) Semiconductor package

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JP2004303900A (en) * 2003-03-31 2004-10-28 Denso Corp Semiconductor device
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