KR101816895B1 - Management serial bus for chassis type communication equipment - Google Patents

Abstract

A management serial bus interface device for a chassis type communication device is provided. A management serial bus interface device for a chassis type communication device according to an embodiment of the present invention includes a plurality of serial buses connected in a 1: 1 manner by a slot in which the plurality of functional units are mounted and a serial bus composed of four lines, interface; A control unit for controlling the plurality of serial bus interfaces to communicate with each of the plurality of functional units according to a bit counter of a predetermined clock cycle; And a register for storing a memory map of 8 bits to be referred to by the control unit for communication with the plurality of functional units, wherein the control unit and the plurality of functional units perform 1: N serial communication.

Description

[0001] The present invention relates to a management serial bus for a chassis-

The present invention relates to a management serial bus for a chassis-type communication device, and more particularly, to a management serial bus for a chassis-type communication device capable of providing 1: N serial communication between a control unit of a communication device and a plurality of functional units Bus.

Generally, a communication system having a chassis-type shelf uses a local bus to control an external memory-type device in a CPU. At this time, the local bus includes a chip select signal (CS), a read / write enable signal R / W, an address signal ADDR, and a data signal DTAT.

On the other hand, an Inter-Integrated Circuit (I2C) interface is used for communication between a microprocessor and a low-speed peripheral device. It is a synchronous serial communication bus that shares a data line between the microprocessor and the peripheral device. Here, one bus can connect up to 127 devices, and a transmission speed of 1 Mbps is possible.

This I2C interface has the advantage of a simple communication protocol, and most of the MCUs have an I2C communication controller. Here, the I2C bus is composed of a serial clock (SCL) and a serial data (SDA) which are bi-directional open drain lines and operates in a master-slave manner. Here, SCL is a clock line for communication synchronization, and SDA is a data line.

For example, the master outputs a clock for synchronization with the SCL, and the slave outputs or receives data via the SDA according to the clock output to the SCL. At this time, since the SDA transmits and receives data by only one line, it is possible to perform half duplex communication.

Particularly, since the conventional serial communication buses communicate with each other over a single line between the CPU and its related devices, a large number of lines are required. In addition, when an error occurs on the bus, However, there is a problem in that it is impossible to control and operate the entire apparatus sharing the bus because communication is impossible.

KR 1993-0016892 A

In order to solve the problems of the related art as described above, one embodiment of the present invention provides a management serial bus for a chassis-type communication device capable of stably maintaining other units except for a defective unit when an error occurs in a data bus I want to.

According to an aspect of the present invention, there is provided an interface device provided in a control unit of a communication device mounted on a chassis-type shelf for communicating with a plurality of functional units using a serial bus . Wherein the interface device comprises: a plurality of serial bus interfaces connected in a 1: 1 manner by a slot in which the plurality of functional units are mounted and a serial bus composed of four lines; A control unit for controlling each of the plurality of functional units and the plurality of serial bus interfaces for communication according to a bit counter of an undetermined clock period; And a register for storing a memory map of 8 bits to be referred to by the control unit for communication with the plurality of functional units, wherein the control unit and the plurality of functional units perform 1: N serial communication.

In one embodiment, the serial bus comprises a synchronous signal, a clock signal, an input data signal, and an output data signal, each of the synchronous signal, the clock signal, the input data signal, Lt; / RTI >

In one embodiment, the output data signal comprises a 2-bit instruction, 4-bit unit ID, 12-bit register address, 1-bit output check, 1-bit 8-bit output data, . ≪ / RTI >

In one embodiment, the input data signal may include a 4-bit unit ID, 8-bit LOS state data, 8-bit EQ state data, 8-bit input data, and 1-bit parity.

In one embodiment, the bit counter has a 32 clock period, and the control unit may set an odd parity value or an even parity value for data corresponding to the bit counter values 1 to 29 The parity can be determined.

In one embodiment, the controller may control to output or receive the parity corresponding to the value of 30 of the bit counter.

In one embodiment, the control unit controls to sequentially output the instruction, the unit ID, and the register address from among the output data signals corresponding to the values of 1 to 20 of the bit counter, , The LOS state data and the EQ state data sequentially.

In one embodiment, the control unit controls the output data to be sequentially output from the output data signals corresponding to the values of the bit counter 22 to 29, and controls the input data signal to sequentially receive the input data signal .

In one embodiment, the register may include a unit ID register, a control / instruction register, a LOS status register, and an EQ status register.

In one embodiment, the control / command register comprises an instruction register including 2-bit instruction data and 4-bit unit ID, a higher address register including a 4-bit upper address, a lower address including a lower address of 8 bits A register, an input data register, and an output data register.

The management serial bus for the chassis-type communication equipment according to an embodiment of the present invention substantially comprises 1: 1 serial communication between the control unit and the functional unit, so that when a bus error occurs, Since it does not affect other units, the reliability of the communication operation can be improved.

In addition, since the present invention performs serial communication through only four serial bus lines and pins per slot, it is possible to use a smaller number of pins than the number of signal pins used in the local bus, It can be reduced and the mass productivity can be improved.

1 is a block diagram of a serial bus interface device according to an embodiment of the present invention.
2 is a block diagram showing a detailed configuration of the control unit of Fig.
3 is a timing chart for explaining serial communication in a serial bus interface apparatus according to an embodiment of the present invention.
Fig. 4 is a diagram showing a detailed configuration of the register of Fig. 2. Fig.
5 is a diagram showing a configuration of the unit ID register of FIG.
Figs. 6 to 11 are diagrams showing the configuration of the control / command register of Fig.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains. The present invention may be embodied in many different forms and is not limited to the embodiments described herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

1 and 2, a serial bus interface apparatus 100 according to an embodiment of the present invention includes a controller 112, a register 114, and a plurality of serial bus interfaces 116-1 to 116-12. .

The serial bus interface device 100 is provided in the control unit 110 of the communication equipment and is connected to the serial buses S1 to S112 between the control unit 110 and the plurality of functional units 120-1 to 120-12 of the communication equipment. To S12).

Here, the communication device may be a chassis-type shelf, and the control unit 110 and the plurality of functional units 120-1 to 120-12 may be mounted in slots of the chassis-type shelf. At this time, the functional units 120-1 to 120-12 may be a memory-type device or a line card for communication. These functional units 120-1 to 120-12 may be composed of 12 units.

Each of the control unit 110 and the plurality of function units 120-1 to 120-12 is connected to the four serial buses S1 to S12 so that the control unit 110 and the plurality of function units 120-1 to 120-12 perform 1: N serial communication.

That is, the control unit 110 can perform 1: 1 serial communication with each of the functional units 120-1 to 120-12 via the respective serial buses S1 to S12. For example, the control unit 110 performs serial communication with the functional unit # 1 120-1 via the serial bus S1 and serial communication with the functional unit # 2 120-2 via the serial bus S2. can do. In this manner, the control unit 110 can perform serial communication with the functional unit # 12 (120-12) via the serial bus S12.

At this time, each of the serial buses S1 to S12 may be composed of a synchronization (SYNC) signal, a clock (SCLK) signal, an input data (SDIN) signal and an output data (SDOUT) signal. That is, the serial buses S1 to S12 may be formed of four lines of physical connection lines. Thus, the serial buses S1 to S12 can transmit and receive the four signals through each of the four lines.

With this arrangement, even when an error occurs on a specific bus, the functional unit except the bus and the functional unit connected thereto can operate normally without being affected by the error.

The control unit 112 controls the serial communication according to a bit counter (not shown) of a predetermined clock cycle. Here, the bit counter may have, for example, 32 clock cycles. That is, the control unit 112 controls the plurality of serial bus interfaces 116-1 to 116-12 so that the control unit 110 can perform serial communication with each of the plurality of functional units 120-1 to 120-12 .

Although not shown in the figure, the controller 112 can control the serial communication according to the timing according to the bit counter (not shown) according to the clock generated by the clock generator.

At this time, the clock generator may generate a clock of, for example, 16.384 MHz. The bit counter may be provided in the control unit 112 or may be provided outside the control unit 112. These bit counters can be sequentially counted from 0 to 31 in a cycle corresponding to the clock of the clock generator.

Referring to FIG. 3, the controller 112 can control the serial communication by a bit counter counted according to the period of the clock (SCLK). That is, the control unit 112 can generate a synchronization (SYNC) signal at a time when the bit counter has a value of 0 to control the serial communication in one period. As described above, the synchronous (SYNC) signal is generated at 32 clock cycles and is for synchronizing the synchronization between the functional units 120-1 to 120-12 in the serial communication. Such a synchronization signal may be generated, for example, at 512 kHz.

In addition, the controller 112 may control output of the output data (SDOUT) signal or input of the input data (SDIN) signal for one cycle in which the value of the bit counter is 0 to 31.

At this time, the output data (SDOUT) signal includes a 2-bit command [1: 0], a 4-bit unit ID UID [3: 0], a 12-bit register address A [11: 0] Output check (T / A), 8-bit output data WD [7: 0] of 1 bit, and parity of 1 bit.

In other words, the controller 112 sets the command RW [1: 0], the unit ID UID [3: 0] and the register address A [11: 0] in the output data (SDOUT) Can be sequentially output.

Here, the command indicates whether data is input or output. When the functional units 120-1 to 120-12 are memory-type devices, they can indicate read and write.

The unit ID is for identifying the target unit, and is for discriminating any one of the functional units 120-1 to 120-12 that are in 1: 1 communication with the control unit 110. [

The register address is for the control unit 112 to refer to the register 114 as described later. That is, this register address is for mutual reference as the control unit 110 and each functional unit 120-1 to 120-12 have the same memory map.

At this time, between the instruction RW [1: 0] and the unit ID UID [3: 0] corresponding to the 3-4 value of the bit counter can be configured to correspond to the frame of the input data SDIN.

Also, the control unit 112 may control to output an output check (T / A) corresponding to the value of the bit counter 21. Here, the output check (T / A) is for distinguishing whether or not to output.

In addition, the control unit 112 can control to sequentially output the output data WD [7: 0] among the output data (SDOUT) signals corresponding to the values of the bit counters 22 to 29. Here, the output data WD [7: 0] is data to be output to the functional units 120-1 to 120-12 through the slot, and may be, for example, write data.

On the other hand, the input data SDIN signal includes unit ID UID [3: 0] of 4 bits, LOS state data LOS [7: 0] of 8 bits, EQ state data EQ [7: 0] of 8 bits, Input data RD [7: 0] of 1, and parity of 1 bit.

In other words, the control unit 112 determines unit ID UID [3: 0], LOS state data LOS [7: 0] and EQ state data EQ [7: 0] in the input data : 0] can be sequentially received.

Here, LOS (loss of signal) status data represents the electrical state of the subscriber port received signal in each of the functional units 120-1 to 120-12, and Equation of Module (EQ) 1 to 120-12) indicating the physical insertion state of the module for the subscriber port.

The control unit 112 is also configured such that the interval between the EQ state data EQ [7: 0] and the input data RD [7: 0] corresponding to the value of the bit counter corresponds to the frame of the output data SDOUT .

Also, the control unit 112 can control the input data RW [7: 0] to be sequentially received from the input data SDIN signal corresponding to the values of the bit counters 22 to 29. Here, the input data RW [7: 0] is data input from each of the functional units 120-1 to 120-12 through the slot and may be, for example, read data.

At this time, the controller 112 may determine the parity according to an odd parity value or an even parity value for the data corresponding to the value of the bit counter. In addition, the controller 112 may control to receive the determined parity corresponding to the value of 30 of the bit counter.

In addition, the controller 112 may configure a margin bit for synchronization corresponding to the value of 31 of the bit counter. That is, the bit corresponding to the value 31 of the bit counter may be configured as a spare.

In this way, the control unit 112 can control to form a signal frame as shown in FIG. 3 for serial communication between the control unit 110 and each of the functional units 120-1 to 120-12.

In this specification, bit frames have been described with reference to 32 clock cycles, but the configuration of bit frames such as register addresses and data can be changed according to the change of the clock. For example, the register address or the number of bits of data can be adjusted.

The register 114 stores a memory map of 8 bits which is referred to by the control unit 112 for communication with the plurality of functional units 120-1 to 120-12. These memory maps are also stored in the functional units 120-1 to 120-12 and can be cross-referenced.

This register 114 may include a unit ID register, a control / command register, a LOS status register, and an EQ status register.

4, the memory map of the register 114 includes a serial bus version register at the register address 0x00h, a unit ID register at the register addresses 0x01h to 0x0E, a control / instruction register at the register addresses 0x18h to 0x1D, LOS status register at register address 0x20h ~ 0x2Dh, and EQ status register at register address 0x30h ~ 0x3d. Here, a reserve register may be included between the unit ID register and the control / command register, between the control / command register and the LOS status register, and between the LOS status register and the EQ status register.

At this time, as shown in FIG. 5, the unit ID register is made up of the lower bits D [3: 0] and corresponding unit IDs, and the upper bits D [7: 4] are reserved.

In addition, the control / command register may include a control register, an instruction register, an upper address register, a lower address register, an input data register, and an output data register, as shown in Figs.

6, the control register includes 1-bit setting data D [7] and 4-bit slot ID SID [3: 0], while D [6: 4] .

Here, the most significant bit D [7] may be used for the SET / DONE setting. At this time, if the set value is "1 ", the operation of the corresponding slot is started, and if the operation is ended, the set value can be automatically cleared.

The slot ID is for identifying a slot in which each functional unit 120-1 to 120-12 is mounted.

As shown in FIG. 7, the instruction register includes 2-bit instruction data RW [1: 0] and 4-bit unit ID UID [3: 0], while D [5: 4] .

As shown in Fig. 8, the upper address register includes a 4-bit upper address A [11: 8], and the upper bit D [7: 4] can be configured as a spare. In addition, as shown in Fig. 9, the lower address register may include a lower address A [7: 0] of 8 bits.

Here, since the register address is composed of 12 bits, it can not be represented by one register of 8 bits, and therefore, it can be composed of two registers.

As shown in Fig. 10, the input data register may include 8-bit input data WD [7: 0]. Further, as shown in Fig. 11, the output data register may include 8-bit output data RD [7: 0].

Since the memory map thus configured is shared by the control unit 110 and the functional units 120-1 to 120-12, the control unit 110 substantially transfers only the register addresses, so that the functional units 120- 1 to 120-12) can recognize the contents.

Referring again to FIG. 2, the plurality of serial bus interfaces 116-1 to 116-12 are connected in a 1: 1 manner through a slot in which a plurality of functional units 120-1 to 120-12 are mounted and four lines .

That is, the serial bus interface # 1 116-1 performs serial communication with the functional unit # 1 120-1 via the serial bus S1, the serial bus interface # 2 116-2 connects with the serial bus S2, 2 to the functional unit # 2 120-2. In this manner, the serial bus interface # 12 (116-12) can perform serial communication with the functional unit # 12 (120-12) via the serial bus S12.

In this way, each of the serial bus interfaces 116-1 to 116-12 performs 1: 1 serial communication with the plurality of functional units 120-1 to 120-12 under the control of the control unit 112, N serial communication between the functional unit 110 and the plurality of functional units 120-1 to 120-12.

With this configuration, serial communication is possible through only four serial bus lines and pins per slot, so that fewer pins can be used than the number of signal pins used in the local bus.

For example, when the local bus address of the local bus is 24 bits and the data 16 bits are used, the number of pins required by the master CPU is (address + data + control) x (even / odd) control = (24 + 16 + 3) to be. On the other hand, the number of pins of the serial bus according to the embodiment of the present invention is (serial bus pin) x number of slots = 4 x 12 = 48.

As described above, the embodiment of the present invention uses fewer number of pins than the conventional one, so that it is possible to reduce the number of components such as buffers and to improve the mass productivity.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100: Serial bus interface device
110: control unit 112:
114: Register
116-1 to 116-12: Serial bus interface
120-1 to 120-12: Functional unit

Claims (10)

1. An interface device provided in a control unit of a communication device mounted on a chassis-type shelf for communicating with a plurality of functional units using a serial bus,
A plurality of serial bus interfaces connected in a 1: 1 manner by a slot in which the plurality of functional units are mounted and a serial bus composed of four lines;
A control unit for controlling the plurality of serial bus interfaces to communicate with each of the plurality of functional units according to a bit counter of a predetermined clock cycle;
And a register for storing a memory map composed of 8 bits to be referred to by the control unit for communication with the plurality of functional units,
Wherein the control unit and the plurality of functional units perform 1: N serial communication,
The serial bus includes a synchronous signal, a clock signal, an input data signal, and an output data signal, and transmits and receives the synchronous signal, the clock signal, the input data signal, and the output data signal through each of the four lines,
The output data signal includes a slave type communication device including a 2-bit command, a 4-bit unit ID, a 12-bit register address, a 1-bit output check, 8-bit output data, and 1-bit parity A serial bus interface device for management purposes. delete delete The method according to claim 1,
Wherein the input data signal is a serial bus for management for a sash type communication device including a 4-bit unit ID, 8-bit LOS status data, 8-bit EQ status data, Interface device. 5. The method of claim 4,
The bit counter has a 32 clock period,
Wherein the control unit determines the parity according to an odd parity value or an even parity value for data corresponding to the value of the bit counter from 1 to 29, Bus interface device. 6. The method of claim 5,
Wherein the control unit controls to output or receive the parity corresponding to the value of the bit counter (30). The method according to claim 6,
Wherein the control unit controls to sequentially output the instruction, the unit ID, and the register address out of the output data signals corresponding to the value of 1 to 20 of the bit counter, and outputs the unit ID, the LOS state data And controlling the EQ state data to be sequentially received. 8. The method of claim 7,
The control unit controls the output data to be sequentially output from the output data signals corresponding to the values of the bit counter 22 to 29 and sequentially controls the input data to be input from the input data signals A serial bus interface device for management purposes. 9. The method of claim 8,
Wherein the register comprises a unit ID register, a control / command register, a LOS status register, and an EQ status register. 10. The method of claim 9,
The control / instruction register includes an instruction register including 2-bit instruction data and 4-bit unit ID, an upper address register including a 4-bit upper address, a lower address register including an 8-bit lower address, , And an output data register for a chassis-type communications device.

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