KR101811108B1 - Using Insulator-metal transition electronic neuron High density neuromorphic system and High density neuromorphic system curcuit - Google Patents

Using Insulator-metal transition electronic neuron High density neuromorphic system and High density neuromorphic system curcuit Download PDF

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KR101811108B1
KR101811108B1 KR1020150179836A KR20150179836A KR101811108B1 KR 101811108 B1 KR101811108 B1 KR 101811108B1 KR 1020150179836 A KR1020150179836 A KR 1020150179836A KR 20150179836 A KR20150179836 A KR 20150179836A KR 101811108 B1 KR101811108 B1 KR 101811108B1
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synapse
resistance
neuron
layer
metal oxide
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KR20170071766A (en
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황현상
차의준
문기봉
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포항공과대학교 산학협력단
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • H01L27/11507—

Abstract

A highly integrated neurocompick system including a neuron element using an insulator-conductor transition phenomenon, and a highly integrated novel lamp circuit. And a neuron element electrically connected to one side of the synapse element, the neuron element exhibiting electrical vibration, wherein the neuron element includes a metal oxide layer having nonconductor-conductor transition characteristics . Therefore, according to the present invention, it is possible to implement a highly integrated novel Lomographic system by applying an IMT element to a neuron element and using a nanoscale synapse element having an analog resistance change characteristic. Furthermore, it can be applied to the artificial brain by providing a neuromorphic system in which the accuracy of pattern recognition is increased through the coupling of the oscillator neuron element and the synapse element having the analog resistance change characteristic.

Description

[0001] The present invention relates to a highly integrated neurocompic system including a neuron element using an insulator-conductor transition phenomenon and a highly integrated novel neurocomputic system and a high density neuromorphic system curcuit,

The present invention relates to a neuromotor system and a neurometric circuit, and more particularly to a highly integrated neuromotor system including a neuron element using a non-conductor-conductor transition phenomenon and a highly integrated neuromotor circuit.

The neuromotor system mimicking the human brain structure is an alternative to the von Neumann type of computing system, that is, an alternative to overcome the variability, low output, and the failure prevention ability.

These neuromotor systems consist of an input layer, synaptic elements and neurons, which perform similar functions to the synapses of the human brain, enabling the learning and cognitive functions of the neuromorphic system. Accordingly, a resistance random access memory (RRAM) among various conventional synaptic devices has recently been attracting attention due to advantages such as simple structure, low power consumption, high integration and fast switching speed.

Conventionally, an insulator-metal transition (IMT) oscillator using a monocrystalline VO 2 layer has been used as a neuron element. However, a low IMT temperature and a high growth rate of a monocrystalline VO 2 layer There is a problem that back end of line (BEOL) compatibility is difficult due to temperature.

In addition, conventionally, there is a problem that it is difficult to highly integrate a neuron device fabrication technique using a complementary metal-oxide semiconductor (CMOS) process.

Korean Patent Publication No. 10-2013-0149988

SUMMARY OF THE INVENTION It is an object of the present invention to provide a neuromorphic system in which accuracy of high integration and pattern recognition is improved through coupling of an oscillator neuron element and a synapse element having analog resistance change characteristics.

According to an aspect of the present invention, there is provided a highly integrated novel Lompick system including a neuron element using an insulator-conductor transition phenomenon. Wherein the highly integrated novel Lomocopic system comprises a nanoscale synapse element including a resistance variable layer and a neuron element electrically coupled to one side of the synapse element and exhibiting electrical oscillation, And a metal oxide layer having transition properties.

The oscillation period of the neuron element can be formed by a resistance value varying according to a voltage applied to the synapse element.

The neuron element may include a substrate, a first electrode located on the substrate, a metal oxide layer located on the first electrode, and a second electrode located on the metal oxide layer.

The metal oxide layer may include NbO 2 , VO 2 , Ti 3 O 5 , Ti 2 O 3, or SmNiO 3 .

The first electrode may include TiN, W, Mo, Pt, Ru, TaN, Ir, RuO 2, IrO 2 , or Al.

The second electrode may include TiN, W, Mo, Pt, Ru, TaN, Ir, RuO 2, IrO 2 , or Al.

The synapse device may include a substrate, a lower electrode layer disposed on the substrate, a resistance variable layer disposed on the lower electrode layer, and an upper electrode layer disposed on the resistance variable layer.

The resistance variable layer may comprise PCMO.

The PCMO may be in a polycrystalline state.

According to another aspect of the present invention, there is provided a highly integrated novel lamp circuit including a neuron element using an insulator-conductor transition phenomenon. Wherein the highly integrated novel Lomic circuit comprises: an input for receiving patterned information; a synapse part connected to the input part for receiving the received patterned information in a synapse form, the synapse part including a resistance-variable layer; And a neuron unit for receiving and outputting electric vibration of an output signal or classifying input pattern information, and the neuron unit may include a neuron element including a metal oxide layer having nonconductor-conductor transition characteristics.

The synapse portion may be a synapse element including a substrate, a lower electrode layer located on the substrate, a resistance variable layer located on the lower electrode layer, and an upper electrode layer located on the resistance variable layer.

The resistance variable layer may comprise PCMO.

The synapse part may be receiving the patterned information at a positive synapse and a negative synapse.

The positive synapse and the negative synapse may be such that the resistance decreases with the application of the set pulse and the resistance increases with the application of the reset pulse.

The neuron unit includes a capacitor for performing a charge / discharge operation in accordance with an output of the synapse unit, and a neuron connected in parallel to the capacitor for generating an electrical vibration through charge / discharge operation, Device.

The neuron element may include a substrate, a first electrode located on the substrate, a metal oxide layer located on the first electrode, and a second electrode located on the metal oxide layer.

The metal oxide layer may include NbO 2 , VO 2 , Ti 3 O 5 , Ti 2 O 3, or SmNiO 3 .

According to the present invention, it is possible to implement a highly integrated novel Lomographic system by applying an IMT element to a neuron element and using a nanoscale synapse element having an analog resistance change characteristic.

Furthermore, it can be applied to the artificial brain by providing a neuromorphic system in which the accuracy of pattern recognition is increased through the coupling of the oscillator neuron element and the synapse element having the analog resistance change characteristic.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view showing a structure of a neuron device according to Production Example 1 of the present invention.
2 is a cross-sectional view illustrating the structure of a synapse device according to a second embodiment of the present invention.
3 is a schematic diagram illustrating an operation of a highly integrated novel Lomic circuit according to an embodiment of the present invention.
Fig. 4 is a graph showing the oscillation tendency for each pixel in the description of the blue frame portion in Fig. 3. Fig.
Fig. 5 is a diagram for explaining the red frame portion of Fig. 3, which is a mapping comparing a case where a ReRAM synapse element is used and a case where a synapse element including PCMO is used.
FIG. 6 shows a case where a synapse device and a neuron device according to the present invention are connected in series.
7 is a graph showing oscillation cycles when a synapse device and a neuron device according to the present invention are connected in series.
FIG. 8 shows the oscillation window of a neuron device including NbO 2 layers according to various cell sizes.
9 is a table comparing electrical characteristics of a conventional synapse element and a neuron element, and a synapse element and a neuron element according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. Rather, the intention is not to limit the invention to the particular forms disclosed, but rather, the invention includes all modifications, equivalents and substitutions that are consistent with the spirit of the invention as defined by the claims.

It will be appreciated that when an element such as a layer, region or substrate is referred to as being present on another element "on," it may be directly on the other element or there may be an intermediate element in between .

Although the terms first, second, etc. may be used to describe various elements, components, regions, layers and / or regions, such elements, components, regions, layers and / And should not be limited by these terms.

1 is a cross-sectional view illustrating a structure of a neuron device according to an embodiment of the present invention.

Referring to FIG. 1, a neuron device according to an embodiment of the present invention includes a substrate, a first electrode 100 positioned on the substrate, a metal oxide layer 110 located on the first electrode 100, And a second electrode 120 disposed on the metal oxide layer 110. The metal oxide layer 110 may have non-conductor-conductor transition characteristics.

More specifically, the substrate may be a silicon substrate or a silicon on insulator (SOI) substrate. An interlayer insulating layer (not shown) may be interposed between the substrate and the first electrode 100. Such a substrate may be omitted in some cases.

Then, the first electrode 100 may be formed on the substrate. The first electrode 100 may be formed using a physical vapor deposition (PVD) method such as sputtering, pulsed laser deposition (PLD), thermal evaporation, electron-beam evaporation, Deposition, Molecular Beam Epitaxy (MBE), or Chemical Vapor Deposition (CVD).

The first electrode 100 may include TiN, W, Mo, Pt, Ru, TaN, Ir, RuO 2, IrO 2 , or Al. For example, the first electrode 100 may include TiN. When the TiN is used for the first electrode 100, the thermal effect may be higher than the case where other electrode materials are used.

Then, the metal oxide layer 110 may be formed on the first electrode 100 described above. The metal oxide layer 110 may have a nonconductor-conductor transition (IMT) characteristic since the metal moves along the oxygen vacancies and becomes charged. The metal oxide layer 110 may be grown at room temperature. This can effectively induce IMT even at a low driving voltage and can lower the device manufacturing process temperature, so that the post-process compatibility can be facilitated.

The metal oxide layer 110 has a high resistance such as an insulator when a voltage lower than a threshold voltage is applied, but a low resistance such as a metal when a voltage higher than the threshold voltage is applied. Since the metal oxide layer 110 having the nonconductor-conductor transition (IMT) characteristic can flow a current without a semiconductor layer, when used for a neuron device, the size of the device can be reduced, It can be possible.

The metal oxide layer 110 may be formed by physical vapor deposition (PVD) such as sputtering, pulsed laser deposition (PLD), thermal evaporation, electron-beam evaporation, Deposition, Molecular Beam Epitaxy (MBE), or Chemical Vapor Deposition (CVD). For example, the deposition of the metal oxide layer 110 may be performed in an Ar / O 2 atmosphere.

The metal oxide layer 110 may include, but is not limited to, NbO 2 , VO 2 , Ti 3 O 5 , Ti 2 O 3, or SmNiO 3 . For example, the metal oxide layer 110 may include NbO 2 .

Next, a second electrode 120 may be formed on the metal oxide layer 110. The metal oxide layer 110 may be formed by physical vapor deposition (PVD) such as sputtering, pulsed laser deposition (PLD), thermal evaporation, electron-beam evaporation, Deposition, Molecular Beam Epitaxy (MBE), or Chemical Vapor Deposition (CVD).

The second electrode 120 may include TiN, W, Mo, Pt, Ru, TaN, Ir, RuO 2, IrO 2 , or Al. For example, the second electrode 120 may include W.

The neuron element formed may have a design rule of 1 nm to 10 nm.

≪ Preparation Example 1 &

NbO 2 Layer  Including neuron device fabrication

A TiN layer is formed on the Si substrate by sputtering. Then, a 15 nm thick NbO 2 layer was sputtered on the TiN layer and deposited in an Ar / O 2 atmosphere. Then, a W layer was deposited by DC sputtering on the NbO 2 layer.

2 is a cross-sectional view illustrating a structure of a synapse device according to an embodiment of the present invention.

Referring to FIG. 2, a synapse device according to an embodiment of the present invention includes a substrate 200, a lower electrode layer 210 located on the substrate 200, a resistance variable layer 220 disposed on the lower electrode layer 210, (220) and an upper electrode layer (230) located on the resistance-variable layer (220).

More specifically, the substrate 200 may be any material that can serve as a support substrate. For example, such a substrate 200 may be a silicon substrate. On the other hand, the substrate 200 may be omitted depending on circumstances.

The lower electrode layer 210 may be formed on the substrate 200. The lower electrode layer 210 may be formed by sputtering, RF sputtering, RF magnetron sputtering, pulsed laser deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy deposition. The lower electrode layer 210 may comprise TiN, W, Mo, Pt, Ru, TaN, Ir, RuO 2, IrO 2 , or Al.

For example, the lower electrode layer 210 may include Pt.

Then, the resistance-variable layer 220 may be formed on the lower electrode layer 210. For example, the resistance-variable layer 220 may include PCMO. PCMO means Pr 0.7 Ca 0.3 MnO 3 . The PCMO may be in a polycrystalline state.

The resistance variable layer 220 may be formed on the lower electrode layer 210 by sputtering, RF sputtering, RF magnetron sputtering, pulsed laser deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or molecular beam epitaxy As shown in FIG.

The resistance-variable layer 220 may exhibit switching uniformity, storage and resistance retention characteristics in a multi-level state according to the same pulse in a synapse device.

Then, the upper electrode layer 230 may be formed on the resistance-variable layer 220. The upper electrode layer 230 may be formed on the resistance variable layer 220 by sputtering, RF sputtering, RF magnetron sputtering, pulsed laser deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or molecular beam epitaxy deposition As shown in FIG. For example, the upper electrode layer 230 may be made of Pt.

The resistance variable layer 220 and the upper electrode layer 230 may be deposited at room temperature.

≪ Preparation Example 2 &

The PCMO layer  Synaptic device manufacturing included

A Pt layer was formed on an 8-inch Si wafer. Then, a polycrystalline PCMO layer was deposited to a thickness of 70 nm on the Pt layer.

Thereafter, a 10 nm thick Mo layer was formed on the PCMO layer in a room temperature atmosphere, and a 50 nm thick Pt layer was formed on the Mo layer.

3 is a schematic diagram illustrating an operation of a highly integrated novel Lomic circuit according to an embodiment of the present invention.

Referring to FIG. 3, the present invention includes a nanoscale synapse element including a resistance-variable layer, and a neuron element electrically connected to one side of the synapse element and exhibiting electrical vibration, the neuron element having a nonconductor- Lt; RTI ID = 0.0 > a < / RTI > highly integrated < / RTI > The detailed description of the synapse element and the neuron element is the same as that of FIG. 1 and FIG.

More specifically, the highly integrated novel Lomopip system according to the present invention includes an input for receiving patterned information, a weighting unit connected to the input unit, weighted to the received patterned information, And a neuron unit receiving the output of the synapse unit and expressing electric vibration of the output signal or classifying input pattern information, wherein the neuron unit includes a neuron element including a metal oxide layer having nonconductor- A highly integrated neuro-pixel circuit can be realized.

An input vector is applied to the input unit, and the received input vector is transmitted to the synapse unit via a buffer or an inverter.

The synapse portion may be a synapse element that uses PCMO as the resistance-variable layer, and has a characteristic that the resistance varies according to the number of pulses applied. In the synapse device according to Production Example 2 of the present invention, the PCMO is used as the resistance variable layer, and Pt is used as the lower electrode and the upper electrode. For example, a polycrystalline PCMO layer may be deposited to a thickness of 3 nm to 100 nm on the lower electrode layer. For example, the PCMO layer may be deposited to 70 nm.

The synapse portion may receive the patterned information delivered at the input portion at a positive synapse and a negative synapse. The positive synapse and the negative synapse may decrease in resistance with application of the set pulse, and the resistance may increase with the application of the reset pulse.

The neuron part may be electrically connected to the synapse part. The neuron unit includes a capacitor for performing a charge / discharge operation in accordance with an output of the synapse unit, and a neuron unit connected in parallel to the capacitor for generating an electrical vibration through a charge / discharge operation, . ≪ / RTI > The description of the structure of the neuron element is the same as that of Fig.

The neuron element may exhibit oscillation according to the resistance value of the synapse element. For example, when testing a black pixel, when testing a V-voltage, white pixel, apply a -V voltage to pass through the resistive portion of the red border (PCMO layer) Oscillation can lead to results.

That is, when the synapse element including the PCMO has a specific resistance value and the applied voltage is applied sufficiently high, the neuron element may transition from an insulator (high resistance state) to a metal (low resistance state) have. In this case, a large amount of voltage is applied to the synapse element, and the voltage of the neuron element is relatively lowered. Then, the neuron element is changed into a high resistance state. .

Fig. 4 is a graph showing the oscillation tendency for each pixel in the description of the blue frame portion in Fig. 3. Fig.

Referring to FIG. 4, when an irregular number 5 is input, the oscillation tendency for each pixel can be confirmed.

It can be confirmed that the tendency of the oscillation is above the threshold value for the black pixel portion and below the threshold value for the white pixel portion.

Fig. 5 is a diagram for explaining the red frame portion of Fig. 3, which is a mapping comparing a case where a ReRAM synapse element is used and a case where a synapse element including PCMO is used.

Referring to FIG. 5, it can be seen that the synaptic weight of PCMO is lower than that of the conventional ReRAM synapse device when the numbers 1 to 5 are learned. have.

FIG. 6 shows a case where a synapse device and a neuron device according to the present invention are connected in series.

Referring to FIG. 6, the current value when the synapse device according to the present invention and the neuron device are connected in series can be measured. For example, in the case of a neuron element including NbO 2 used at this time, when R on = 1.9 k OMEGA and R off = 15 k OMEGA, the resistance value of the synapse element is in a range of 1.9 kΩ to 15 kΩ, Can be expressed.

7 is a graph showing oscillation cycles when a synapse device and a neuron device according to the present invention are connected in series.

Referring to FIG. 7, it can be seen that, when the synapse device and the neuron device according to the present invention are connected in series, the oscillation cycle of the neuron device gradually increases as the resistance value of the synapse device decreases. This phenomenon can be utilized in a novel Lomographic system, such as a spiking neural network (SNN), by utilizing the oscillation frequency.

FIG. 8 shows the oscillation window of a neuron device including NbO 2 layers according to various cell sizes.

Referring to FIG. 8, when the NbO 2 -based IMT device is used as a neuron device, the oscillation window increases as the cell size decreases. Therefore, such a neuron element including NbO 2 can be promisingly used in terms of scalability.

9 is a table comparing electrical characteristics of a conventional synapse element and a neuron element, and a synapse element and a neuron element according to the present invention.

Referring to FIG. 9, through the coupling of a synapse element including a PCMO and a neuron element including NbO 2 according to an embodiment of the present invention, the plasticity characteristic of the element according to the number of pulses and the resistance- And the like are improved. Accordingly, a novel Lomographic system with improved performance in terms of scalability and power consumption compared to conventional CMOS neurons can be provided.

It should be noted that the embodiments of the present invention disclosed in the present specification and drawings are only illustrative of specific examples for the purpose of understanding and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

100: first electrode 110: metal oxide layer
120: second electrode 200: substrate
210: lower electrode layer 220: resistance variable layer
230: upper electrode layer

Claims (17)

A synapse element which includes a resistance variable layer and whose resistance is changed according to the number of application of the input pulse; And
And a neuron element electrically connected to one side of the synapse element and exhibiting electrical vibration,
The neuron element has non-conductor-to-conductor transition characteristics,
Wherein the resistance is changed to a high resistance state or a low resistance state by a voltage applied from a synapse element to which the resistance is changed to cause the electrical vibration. delete The method according to claim 1,
Wherein the neuron element comprises:
Board;
A first electrode located on the substrate;
A metal oxide layer located on the first electrode; And
And a second electrode located on the metal oxide layer. The method of claim 3,
Wherein the metal oxide layer comprises NbO 2 , VO 2 , Ti 3 O 5 , Ti 2 O 3 or SmNiO 3 . The method of claim 3,
Wherein said first electrode is integrated New our pick system comprises a TiN, W, Mo, Pt, Ru, TaN, Ir, RuO 2, IrO 2 , or Al. The method of claim 3,
The second electrode is integrated New our pick system comprises a TiN, W, Mo, Pt, Ru, TaN, Ir, RuO 2, IrO 2 , or Al. The method according to claim 1,
The synapse device comprises:
Board;
A lower electrode layer disposed on the substrate;
A resistance-variable layer located on the lower electrode layer; And
And an upper electrode layer located on the resistance variable layer. 8. The method of claim 7,
Wherein the resistance variable layer comprises PCMO. ≪ RTI ID = 0.0 > 11. < / RTI > 9. The method of claim 8,
Wherein the PCMO is in a polycrystalline state. An input unit for receiving the patterned information;
A synapse section connected to the input section, receiving a received patterned information in a synapse form, and including a resistance-variable layer; And
And a neuron unit for receiving the output of the synapse unit and expressing electric vibration of the output signal or classifying input pattern information,
Wherein the synapse part receives the patterned information as a positive synapse and a negative synapse, the positive synapse and the negative synapse being reduced in resistance with the application of the set pulse, And has an increasing characteristic,
Wherein the neuron portion includes a metal oxide layer having nonconductor-conductor transition characteristics and is changed to a high resistance state or a low resistance state by a voltage applied from a synapse element in which the resistance is changed, thereby causing the electrical vibration A highly integrated neoplox circuit. 11. The method of claim 10,
The synapse portion includes:
Board;
A lower electrode layer disposed on the substrate;
A resistance-variable layer located on the lower electrode layer; And
And an upper electrode layer positioned on the resistance-variable layer. 12. The method of claim 11,
Characterized in that the resistance variable layer comprises PCMO. delete delete 11. The method of claim 10,
The neuron unit,
A capacitor for performing a charge / discharge operation in accordance with an output of the synapse unit; And
And a neuron element connected in parallel to said capacitor for generating electrical oscillation through charging and discharging operations or for forming an output signal having a particular level. 16. The method of claim 15,
Wherein the neuron element comprises:
Board;
A first electrode located on the substrate;
A metal oxide layer located on the first electrode; And
And a second electrode located on the metal oxide layer. 17. The method of claim 16,
Wherein the metal oxide layer comprises NbO 2 , VO 2 , Ti 3 O 5 , Ti 2 O 3 or SmNiO 3 .

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