KR101743173B1

KR101743173B1 - Communication device between shelves in communication equipment

Info

Publication number: KR101743173B1
Application number: KR1020160006080A
Authority: KR
Inventors: 한명훈
Original assignee: 주식회사 우리넷
Priority date: 2016-01-18
Filing date: 2016-01-18
Publication date: 2017-06-05

Abstract

There is provided a self-communication device of communication equipment. A communication apparatus for communication between communication apparatuses according to an embodiment of the present invention is an apparatus for communicating between a mainframe and a subfolder through a high definition multimedia interface (HDMI) cable, the apparatus being mounted on the mainframe, And receives a control signal from the CPU and data from another external communication device via the CPU of the main shelf and converts the received data into two 32M bit serial data, A first self expanding unit for converting the frame pulse and the two serial data by a Low Voltage Differential Signaling (LVDS) method and transmitting the frame pulse to the sub-shelf through four pairs of lines of the HDMI cable; And receiving control signals and data indicative of states from 15 second line cards of the sub-shelf, converting the received control signals and data into two 32-Mbit serial data, converting them into an LVDS system, To the main shelf through a line of the second self-expanding unit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-communication apparatus for a communication apparatus, and more particularly, to a self-communication apparatus for a communication apparatus capable of performing communication between a main shelf and a sub-shelf using an HDMI cable.

BACKGROUND ART [0002] In recent years, communication devices that perform high-speed switching with the increase in the number of subscribers are emerging. Although these communication apparatuses are manufactured with various functions and capacities according to the hierarchical structure, there are occasions when a plurality of equipments having the same function and capacity are added.

As described above, in order to expand the communication equipment, a sub-shelf is added and used in addition to the main shelf. In this case, a cable or the like is used to perform communication between a plurality of shelves.

At this time, there are about 80 kinds of signals required for self-communication, which is too many signals, so a large number of cables are required. In this case, not only is the cost of management and operation increased, but also the complexity of the cable between the self-cabling becomes inefficient for management and operation, and the possibility of a communication failure due to an operator's mistake such as an incorrect connection of a cable is increasing .

Accordingly, there is a need for a method for simplifying communication between a main shelf and a sub shelf in a communication apparatus.

KR 2007-0065967 A

In order to solve the problems of the related art as described above, one embodiment of the present invention provides a self-communication device capable of simplifying the cable configuration for communication between the self-service devices.

According to an aspect of the present invention, there is provided an apparatus for communicating between a main shelf and a sub shelf via a high definition multimedia interface (HDMI) cable. Wherein the communication device is mounted on the main shelf and receives 32-Mbit clock and frame pulses from the main shelf, and receives data from other external communication equipment through the CPU of the main shelf and control from the CPU And converts the clock, the frame pulse, and the two serial data into a low voltage differential signaling (LVDS) method, and outputs the 32-bit serial data through the four pairs of lines of the HDMI cable to the sub- A first self-expanding unit for self-transmitting; And receiving control signals and data indicative of states from 15 second line cards of the sub-shelf, converting the received control signals and data into two 32-Mbit serial data, converting them into an LVDS system, To the main shelf through a line of the second self-expanding unit.

In one embodiment, each of the first self-expanding unit and the second self-expanding unit includes: a multiplexing unit for multiplexing the data and the control signal into the two serial data; A demultiplexer for demultiplexing the two serial data into the data and the control signal; And a timing controller for controlling bit conversion and timing of the multiplexer unit and the demultiplexer unit.

In one embodiment, the multiplexer unit includes eight first multiplexers for inputting two signals of the data and the control signal and performing 2: 1 multiplexing to convert the signals into 8M bits of serial data; Two second multiplexers for inputting four of the outputs of the first multiplexer and performing a 4: 1 multiplexing on the input to convert the multiplexed data into serial data of 32M bits; And a first memory for temporarily storing each of the outputs of the second multiplexer and transmitting the output of the second multiplexer in the LVDS system in response to the control of the timing controller.

In one embodiment, one of the eight first multiplexers may receive the data and the control signal from any one of the line cards, and the rest may input only the data from the line card.

In one embodiment, the control signal includes a first control signal FAIL indicating whether or not the second line card fails, a second control signal CR indicating whether the second line card is mounted, And a third control signal RST for resetting the line card.

In one embodiment, each of the first control signal to the third control signal may be composed of 16 bits.

In one embodiment, the timing controller may control the timing of inputting the data and the control signal to the first multiplexer in units of 4M bits.

In one embodiment, the timing controller may control the first control signal to the third control signal to be arranged in a predetermined manner among 4M bits.

In one embodiment, the demultiplexer comprises: two first demultiplexers for demultiplexing each of the two serial data received from the counterpart into 4 8M bits of data; A second memory for temporarily storing each of the outputs of the first demultiplexer and outputting under the control of the timing controller; And eight second demultiplexers for 1: 2 demultiplexing each of the outputs of the second memory and converting them into two 4M bit data.

In one embodiment, the HDMI cable includes at least six pairs of lines, wherein four pairs of lines are allocated to the clock, the frame pulse, and the two serial data transmitted from the main shelf to the sub-shelf, Two pairs of lines may be allocated to the two serial data transmitted from the sub-shelf to the main shelf.

The inter-self communication apparatus according to an embodiment of the present invention can communicate a large amount of data while using a small number of signal lines by communicating between the main and sub-housings using an HDMI cable, have.

In addition, since the present invention performs self-communication using a small number of signal lines, it is possible to simplify the cable connected between the selfs, thereby improving the efficiency in management and operation.

1 is a schematic block diagram of a self-contained communication device of a communication device according to an embodiment of the present invention.
2 is a block diagram schematically illustrating a signal flow of a self-communication apparatus of a communication apparatus according to an embodiment of the present invention.
3 is a block diagram showing a detailed configuration of the self-expanding unit of FIG.
4 is a block diagram showing a detailed configuration of the multiplexer unit of FIG.
5 is a diagram showing the structure of an 8M-bit signal constituted by the timing controller of FIG.
FIG. 6 is a diagram showing a structure of a control signal in FIG.
7 is a block diagram showing a detailed configuration of the demultiplexer unit of FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains. The present invention may be embodied in many different forms and is not limited to the embodiments described herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

1 and 2, a self-service communication apparatus 100 according to an exemplary embodiment of the present invention includes a first self-expanding unit 110, a second self-expanding unit 120, and an HDMI cable 130 .

The self-service communication device 100 is for communication between the main shelf 101 and the sub-shelf 102. [ The main shelf 101 is equipped with a CPU 101a, a plurality of first line cards 101b and a first self expanding unit 110. The sub shelf 102 includes a plurality of second line cards 102b, And a second self-expanding unit 120 are mounted.

At this time, the CPU 101a performs control on the function unit or the card mounted on the main shelf 101, and detects and controls the state of each unit or card. The first line card 101b performs a communication function, for example, 15 lines. The CPU 101a communicates with other communication equipment through an external communication network. That is, the CPU 101a can transmit data from the first line card 101b or the second line card to other external communication equipment.

In addition, the second line card 102b performs a communication function, for example, 15 lines.

The main shelf 101 and the sub shelf 102 are for providing expandability of communication equipments. The main shelf 101 and the sub shelf 102 are communication equipments having the same functions.

Although the sub-shelf 102 is shown as being one person in the drawing, the present invention is not limited thereto, and the sub-shelf 102 may be plural. At this time, the main shelf 101 may include a plurality of first self-expanding units 110 for 1: 1 communication between the main shelf 101 and the sub-shelf 102.

The first self-expanding unit 110 transmits the control signal of the CPU 101a to the sub-shelf 102 and receives the data of the second line card 102b from the sub-shelf 102. [

The first self-expanding unit 110 receives the 32-Mbit clock CLK and the frame pulse FP from the clock generating unit (not shown) of the CPU 101a, Lt; RTI ID = 0.0 > CU < / RTI > Here, the clock and frame pulses are for synchronizing the main shelf 101 and the sub shelf 102, and are the reference signals provided from the main shelf 101 to the sub shelf 102. Further, the control signal for each functional unit or card may be a control signal (CU_RST) for resetting the corresponding unit or card.

In addition, the first self-expanding unit 110 receives the respective data TX_DATA from the CPU 101a communicating with other external communication equipment. At this time, the first self-expanding unit 110 may convert the data TX_DATA and the control signal CU into two 32-Mbit serial data.

In addition, the first self-expanding unit 110 generates a low voltage differential signaling (LVDS) signal to transmit a 32-Mbit clock CLK, a frame pulse FP and two serial data TX_DATA and TX_SIG to the sub- ) Method.

2, the first self-expanding unit 110 is connected to the sub-shelf 102 via the four pairs of lines of the HDMI cable 130, such as a clock, a frame pulse, a reset control of a functional unit or a card Signals and data.

The second self expanding unit 120 transmits a control signal and data indicating the state of the second line card 102b to the main shelf 101 in correspondence to the first self expanding unit 110, And data of other external communication equipment through the CPU 101a from the main shelf 101.

The second self expanding unit 120 receives a control signal CU indicating the status of each functional unit or card from the second line card 102b. Here, the control signal for each functional unit or card may be a control signal for detecting a state such as a fail state (FAIL) and a mounting state (CR).

In addition, the second self expanding unit 120 receives the respective data RX_DATA from the plurality of second line cards 102b.

At this time, the second self-expanding unit 120 may convert the data RX_DATA and the control signal CU into two 32-Mbit serial data. Also, the second self-expanding unit 120 can convert the two serial data RX_DATA and RX_SIG into the LVDS scheme for transmission to the main shelf 101.

2, the second self-expanding unit 120 can transmit the monitoring control signal and data to the main shelf 101 through the two pairs of lines of the HDMI cable 130. [

The HDMI cable 130 is for connecting the main shelf 101 and the sub shelf 102. One end of the HDMI cable 130 may be connected to the first connector 101c and the other end thereof may be connected to the second connector 102c. The HDMI cable 130 may be an HDMI (High Definition Multimedia Interface) cable.

Here, the HDMI cable 130 may include at least six pairs of lines. At this time, four pairs of lines are assigned to the clock, frame pulse, and two serial data transmitted from the main shelf 101 to the sub shelf 102, and two pairs of lines are transmitted from the sub shelf 102 to the main shelf 101 Two pairs of lines can be assigned to the serial data.

2, the HDMI cable 130 includes a clock CLK +/-, a frame pulse FP +/-, and two serial data TX_DATA +/-, TX_SIG +/-, It is possible to transmit a signal from the main shelf 101 to the sub shelf 102 through four pairs of lines corresponding to the same four signals.

The HDMI cable 130 also receives signals from the sub-shelf 102 to the main shelf 101 via two pairs of lines corresponding to two signals, such as two serial data (RX_DATA +/-, RX_SIG +/-) Can be transmitted.

As described above, since the signals transmitted between the main shelf 101 and the sub-shelf 102 are converted into the LVDS system and transmitted, a pair (+/- ).

Hereinafter, the first self-expanding unit 110 and the second self-expanding unit 120 will be described in more detail with reference to FIGS. 3 to 7. FIG.

Each of the first self expanding unit 110 and the second self expanding unit 120 may include a timing control unit 112, a multiplexer unit 140 and a demultiplexer unit 150 as shown in FIG. 3 .

The timing control unit 112 can control the bit conversion and timing of the multiplexer unit 140 and the demultiplexer unit 150. [ That is, the timing controller 112 may control multiplexing or demultiplexing of signals to be transmitted in the same format of 32 Mbits for synchronization of signals transmitted through the HDMI cable 130. [

The multiplexer unit 140 receives the control signal CU received from the CPU 101a and the data received from the external communication equipment via the CPU 101a or the data TX_DATA and RX_DATA received from the second line card 102b, Can be multiplexed into two serial data of 32M bits. That is, the multiplexer unit 140 can multiplex a signal transmitted and received for communication between the main shelf 101 and the sub-shelf 102 in accordance with the HDMI cable 130.

The demultiplexer unit 150 may demultiplex the two serial data received from the counterpart to the original signal using the data and control signals. That is, the demultiplexer unit 150 can demultiplex the signals multiplexed by the multiplexer unit 140 of the self-extension units 110 and 120 mounted in the counterparts to the original signals.

Hereinafter, the multiplexer unit 140 and the demultiplexer unit 150 will be described in more detail with reference to FIGS.

As shown in FIG. 4, the multiplexer unit 140 may include a first multiplexer 142, a second multiplexer 144, and a first memory 146.

The first multiplexer 142 can multiplex 2: 1 signals by inputting the two signals of the second line card 102b or the data received from the CPU 101a and the control signal received from the CPU 101a. Here, in the case of the surf shelf 102, the control signal may be a control signal indicating the state of the second line card 102b.

When the first multiplexer 142 is provided with fifteen line cards, the first multiplexer 142 may be composed of eight to generate eight 8-Mbit serial data.

Here, the data received from the second line card 102b or the CPU 101a is 4M-bit data, and the first multiplexer 142 can multiplex such 4M-bit data into 8M-bit serial data.

For example, as shown in FIG. 4, the first multiplexer 142 multiplexes 2-to-1 data of two pieces of data (TX_DATA 1 to TX_DATA 14) received from 15 line cards, Can be converted into serial data.

That is, the first multiplexer 142 converts the two data (TX_DATA 1, TX_DATA 2) into one serial data TX_DT # 1 and outputs the two data TX_DATA 3, TX_DATA 4 to one serial data TX_DT # 2), converts two data (TX_DATA 5, TX_DATA 6) into one serial data (TX_DT # 3), and converts the two data (TX_DATA 7, TX_DATA 8) into one serial data ). &Lt; / RTI >

The first multiplexer 142 converts the two data TX_DATA 9 and TX_DATA 10 into one serial data TX_SI # 1 and outputs the two data TX_DATA 11 and TX_DATA 12 to one serial data TX_SI # 2), and can convert the two data (TX_DATA 13, TX_DATA 14) into one serial data (TX_SI # 3).

At this time, as shown in FIG. 5, the timing controller 112 may perform timing control so that two data (TX_DATA) are input to the first multiplexer 142 in units of 4M bits.

On the other hand, the last first multiplexer 142 receives 2: 1 multiplexing with the data (TX_DATA 15) received from the line card and the control signal received from the CPU or the control signal ETC_DATA indicating the state received from the line card Can be performed.

The control signal ETC_DATA includes a first control signal CU_FAIL indicating whether the second line card 102b fails or not, a second control signal CU_CR indicating whether the second line card 102b is mounted, And a third control signal CU_RST indicating whether the second line card 102b is reset or not.

Each of the first to third control signals may be composed of 16 bits. That is, when the second line card 102b is composed of fifteen lines, a signal of one bit is allocated to each line card and the expansion unit, and it can be constituted by 16 bits.

In addition, this control signal can be reconfigured as a 4Mbit signal since it must be formatted to the same size as the data of the second line card 102b or the CPU 101a (TX_DATA 15). At this time, the timing controller 112 may control to arrange the first to third control signals in a predetermined manner among the 4M bits.

For example, as shown in FIG. 6, each of the first to third control signals may be arranged in a predetermined manner within a 4M-bit frame under the control of the timing control unit 112. [ Here, the first control signal to the third control signal are not limited to the order shown in Fig. 6 within the 4M bit frame, but may be arranged in any order.

At this time, when the multiplexer unit 140 is mounted on the main shelf 101, the control signal ETC_DATA is set to a third control for controlling resetting of each functional unit or card of the sub-shelf 102 in the main shelf 101 Signal CU_RST.

When the multiplexer unit 140 is mounted on the sub-shelf 102, the control signal ETC_DATA includes a first control signal CU_FAIL for monitoring the state of each functional unit or card of the sub-shelf 102, 2 < / RTI > control signal (CU_CR).

The second multiplexer 144 may multiplex 4: 1 with four of the outputs of the first multiplexer 142 as inputs.

The second multiplexer 144 may be composed of 15 line cards and two first multiplexers 142 to generate two 32-Mbit serial data when 8 first multiplexers 142 are provided.

Here, the input data is 8M-bit serial data, and the second multiplexer 144 can multiplex these 4 8M-bit data into 32-Mbit serial data.

For example, as shown in FIG. 4, the second multiplexer 144 multiplexes four data (TX_DT # 1 to TX_DT # 1, TX_SI # 1 to TX_SI # 4) received from the first multiplexer 142 Data can be input and converted into 32-Mbit serial data by 4: 1 multiplexing.

That is, the second multiplexer 144 converts the four pieces of data TX_DT # 1 to TX_DT # 1 into one serial data TX_DATA # 1 and supplies the four pieces of data TX_SI # 1 to TX_SI # It can be converted into serial data (TX_DATA # 2).

At this time, the timing controller 112 can perform timing control so that each of the four data (TX_DT # 1 to TX_DT # 1, TX_SI # 1 to TX_SI # 4) output from the second multiplexer 144 is converted into sequential serial data have.

The first memory 146 temporarily stores each of the outputs of the second multiplexer 144 and can transmit data (LVDS_TX_DATA # 1, LVDS_TX_DATA # 1) in a relative self-manner in the LVDS scheme under the control of the timing controller 112 .

Here, when the 32-Mbit data is transmitted through the HDMI cable 130, the first memory 146 is used as a pair of lines for each signal, and in particular, .

As shown in FIG. 7, the demultiplexer unit 150 may include a first demultiplexer 152, a second memory 154, and a second demultiplexer 156.

The first demultiplexer 152 can 1: 4 demultiplex each of the two serial data (LVDS_RX_DATA # 1, LVDS_RX_DATA # 1) of the LVDS scheme received from the counterpart.

When the first demultiplexer 152 is provided with 15 line cards, the first demultiplexer 152 may be composed of two to generate 8 8-bit data.

Here, the received data is 32M-bit serial data, and the first demultiplexer 152 can demultiplex this one 32M-bit data into 8M-bit data.

4, the first demultiplexer 152 converts one data (LVDS_RX_DATA # 1) into four data (RX_DATA 1 to RX_DATA 4), and one data (LVDS_RX_DATA # 2) Into four pieces of data (RX_SIG 1 to RX_SIG 4).

At this time, the timing controller 112 can perform timing control so that each of the four data (RX_DATA 1 to RX_DATA 4, RX_SIG 1 to RX_SIG 4) output from the first multiplexer 142 is used as parallel data at the subsequent stage.

The first demultiplexer 152 temporarily stores the outputs of the first demultiplexer 152 and outputs the second demultiplexer 152 under the control of the timing controller 112.

The second demultiplexer 156 may demultiplex each of the outputs (RX_DATA 1 to RX_DATA 4, RX_SIG 1 to RX_SIG 4) of the second memory 154 by 1: 2.

The second demultiplexer 156 may include eightteen line cards and eight first demultiplexers 152 to generate sixteen 4M bits of data.

Here, the data (RX_DT # 1 to RX_DT # 8) output from the second memory 154 is 8M-bit data, and the second demultiplexer 156 demultiplexes this 8M-bit data into 4M-bit data Can be converted.

4, the second demultiplexer 156 converts one data (RX_DT # 1) into two data (RX_DT 1 to RX_DT 2), and one data (RX_DT # 2) Converts one data RX_DT # 3 into two data RX_DT 5 to RX_DT 6, converts one data RX_DT # 4 into two data RX_DT 3 to RX_DT 4, (RX_DT 7 to RX_DT 8).

The second demultiplexer 156 converts one piece of data RX_DT # 5 into two pieces of data RX_DT 9 to RX_DT 10 and outputs one piece of data RX_DT # 6 to two pieces of data RX_DT 11 to RX_DT 12 ) And converts one data RX_DT # 7 into two data RX_DT 13 to RX_DT 14 and one data RX_DT # 8 into two data RX_DT 15 to ETC_DATA have.

At this time, the timing controller 112 can perform timing control so that each of the 16 data (RX_DT 1 to RX_DT 15, ECT_DATA) output from the second demultiplexer 156 is used as parallel data at the subsequent stage.

With this configuration, the inter-self communication apparatus 100 according to an embodiment of the present invention communicates between the main and sub-housings using an HDMI cable, thereby enabling a large amount of data communication using a small number of signal lines So that the operation cost can be reduced.

In addition, since a self-communication is performed using a small number of signal lines, a cable connected between the selfs can be simplified, and the efficiency in management and operation can be improved.

The self-service communication apparatus 100 according to the embodiment of the present invention is for communication between the main shelf 101 and the sub-shelf 102.

That is, in the transmitting side self, the inter-self communication apparatus 100 multiplexes 16 signals having a speed of 4M bits to generate 8 signals, and 8 signals are multiplexed with two signals having a 32M bit rate And then transmitted through an HDMI cable.

At this time, in the receiving side shelf, the inter-user communication device 100 demultiplexes signals received by two 32M bits into eight signals of 8M bits, and then demultiplexes the eight signals into 16 signals having a 4M bit rate, And constitute 16 signals originally transmitted.

Here, one of the 16 signals transmitted through the HDMI cable 130 may be a control signal. These control signals may include 16 signals for detecting whether each function or unit fails, 16 signals for detecting the state of mounting (CU_CR), and 16 signals for controlling reset (CU_RST).

By applying such a communication method, it is possible to communicate various signals with a small number of lines. At this time, the multiplexer and the demultiplexer can be implemented using the FPGA.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100: Self-service communication device 101: Main shelf
101a: CPU 101b: first line card
101c: first connector 102: sub-
102b: second line card 102c: second connector
110: first self-expanding unit 112: timing control unit
120: Second self expanding unit 130: HDMI cable
140: multiplexer section 142: first multiplexer
144: second multiplexer 146: first memory
150: Demultiplexer part 152: First demultiplexer
154: second memory 156: second demultiplexer

Claims

An apparatus for communicating between a main shelf and a sub shelf via an HDMI (High Definition Multimedia Interface) cable,
Receives a clock and a frame pulse of 32 Mbits from the CPU of the main shelf and receives data from another external communication apparatus through the CPU of the main shelf and a control signal from the CPU Converts the clock, the frame pulse, and the two serial data into a low voltage differential signaling (LVDS) method, and transmits the serial data to the sub-shelf through four pairs of lines of the HDMI cable A first self-expanding unit; And
And receives control signals and data indicating status from the 15 second line cards of the sub-shelf, converts the received control signals and data into two 32-Mbit serial data, converts them into the LVDS system, And a second self-expanding unit for transmitting the first self-extended self-
Wherein each of the first self-expanding unit and the second self-
A multiplexer section for multiplexing the data and the control signal into the two serial data; a demultiplexer section for demultiplexing the two serial data into the data and the control signal; and a demultiplexer section for demultiplexing the multiplexer section and the demultiplexer section, And a timing controller for controlling the timing controller,
The multiplexer unit,
Eight first multiplexers for performing two-to-one multiplexing on the two signals of the data and the control signal to convert the multiplexed data into serial data of 8M bits;
Two second multiplexers for inputting four of the outputs of the first multiplexer and performing a 4: 1 multiplexing on the input to convert the multiplexed data into serial data of 32M bits; And
And a first memory for temporarily storing each output of the second multiplexer and transmitting the output of the second multiplexer to the counterpart in accordance with the LVDS scheme under the control of the timing controller.

delete

The method according to claim 1,
Wherein one of the eight first multiplexers inputs the data from the one line card and the control signal and the other inputs only the data from the line card.

5. The method of claim 4,
Wherein the control signal includes a first control signal (FAIL) indicating whether the second line card fails or not, a second control signal (CR) indicating whether the second line card is mounted, and a second control signal And a third control signal (RST) for the communication device.

6. The method of claim 5,
Wherein each of the first control signal to the third control signal is composed of 16 bits.

The method according to claim 6,
Wherein the timing controller controls the timing so that the data and the control signal are input to the first multiplexer in units of 4M bits.

8. The method of claim 7,
Wherein the timing control unit controls to arrange the first control signal to the third control signal in a predetermined manner among 4M bits.

The method according to claim 1,
The demultiplexer unit,
Two first demultiplexers for 1: 4 demultiplexing each of the two serial data received from the counterpart and converting the data into four 8-Mbit data;
A second memory for temporarily storing each of the outputs of the first demultiplexer and outputting under the control of the timing controller; And
And eight second demultiplexers for demultiplexing each of the outputs of the second memory into two 4M bit data.

10. The method of claim 9,
Wherein the HDMI cable includes at least six pairs of lines, wherein four pairs of lines are assigned to the clock, the frame pulse, and the two serial data transmitted from the main shelf to the sub-shelf, Wherein two pairs of lines are assigned to the two serial data transmitted by the self.