KR101740284B1 - ADCL(Adiabatic Dynamic CMOS Logic) inverter with enhanced current driving capability - Google Patents

ADCL(Adiabatic Dynamic CMOS Logic) inverter with enhanced current driving capability Download PDF

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KR101740284B1
KR101740284B1 KR1020160027306A KR20160027306A KR101740284B1 KR 101740284 B1 KR101740284 B1 KR 101740284B1 KR 1020160027306 A KR1020160027306 A KR 1020160027306A KR 20160027306 A KR20160027306 A KR 20160027306A KR 101740284 B1 KR101740284 B1 KR 101740284B1
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terminal
adcl
nmos
pmos
bias voltage
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김성권
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서울과학기술대학교 산학협력단
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/354—Astable circuits

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Abstract

The present invention relates to an adiabatic dynamic CMOS logic (ADCL) inverter with an enhanced current driving capability. According to the present invention, the ADCL inverter with an enhanced current driving capability comprises: a first ADCL circuit unit including a first diode wherein an anode terminal thereof is connected to a first AC power input end, a first PMOS wherein a source terminal thereof is connected to a cathode terminal of the first diode and a gate terminal thereof is connected to a first bias voltage input end, a first NMOS wherein a drain terminal thereof is connected to a drain terminal of the first PMOS and a gate terminal thereof is connected to the first bias voltage input end, and a second diode wherein an anode terminal thereof is connected to a source terminal of the first NMOS and a cathode terminal thereof is connected to the first AC power input end; and a second ADCL circuit unit including a third diode wherein an anode terminal thereof is connected to a second AC power input end, a second PMOS wherein a source terminal thereof is connected to a cathode terminal of the third diode and a gate terminal thereof is connected to a second bias voltage input end, a second NMOS wherein a drain terminal thereof is connected to a drain terminal of the second PMOS and a gate terminal thereof is connected to the second bias voltage input end, and a fourth diode wherein an anode terminal thereof is connected to a source terminal of the second NMOS and a cathode terminal thereof is connected to the second AC power input end. According to the present invention, a degree of integration of a chip can be increased to reduce manufacturing costs. A current driving capability is improved by two ADCL circuits to contribute to the improvement of product quality.

Description

[0001] The present invention relates to an ADCL inverter having improved current driving capability,

The present invention relates to an ADCL (Adiabatic Dynamic CMOS Logic) inverter, and more particularly, to a semiconductor integrated circuit which improves chip integration by using no capacitor and operates with one logic gate using two ADCL circuits, To an ADCL inverter which improves the current driving capability, which can reduce the abnormal operation of the logic circuit by improving the current driving capability.

Recently, with the rapid development of biotechnology, microchip and nanochip technology for inserting a chip into a human body are getting much attention. However, when the chip inserted into the body is operated, the chip may suddenly generate heat due to the on / off switching operation of the chip and the energy loss due to the internal resistance of the chip associated therewith. This can cause catastrophic damage to cells of the human body.

In addition, since the chip inserted into the body can not be supplied with power from the outside, once the power is supplied, the operation state of the chip must be continuously maintained without supplying power from the outside. Therefore, low power operation of the circuit is required. ADL (Adiabatic Dynamic CMOS Logic) is an optimized circuit, and various researches and technologies related thereto are being continuously developed. To take advantage of this ADCL, a capacitor is used at the bottom of the circuit. This is to prevent errors in operation and improve the driving capability as a logic gate in the construction of an ADCL-based digital system.

However, in a System on Chip (SoC) design made up of ADCL digital systems, the area of the chip is much larger than that of the CMOS digital system because of the large area of the capacitor. This means that the degree of integration is lowered, leading to an increase in design costs. However, if an ADCL circuit with a capacitor removed is used to cope with this problem, since the digital logic representation instantaneously changes due to the characteristic of using an AC power source, the current driving ability of the circuit is degraded and the operation of the logic circuit is not properly performed.

On the other hand, Japanese Patent Application No. 10-0554826 (Patent Document 1) discloses a "dynamic CMOS logic circuit" for increasing the speed of the gate by reducing the height of the pull down stack in the dynamic logic gate without changing the function of the gate A logic circuit output node connected to a second node of the precharge circuit; and a second logic circuit output node connected to the second node of the precharge circuit, A logic circuit for controlling a logic circuit output node, and a pseudofooter circuit.

However, although the above-described Patent Document 1 can provide a fast dynamic logic gate and enable a low-power dynamic logic gate, since the digital logic representation is instantaneously changed due to the characteristic of using the AC power source, And the operation of the logic circuit is not properly performed.

Patent Registration No. 10-0554826 (registered on February 16, 2006)

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to improve the integration degree of a chip by not using a capacitor and improve the current driving capability by operating one logic gate using two ADCL circuits, And an ADCL inverter improved in current driving ability, which can reduce abnormal operation, is provided.

In order to achieve the above object, the ADCL inverter improved the current driving capability according to the first embodiment of the present invention,

A first PMOS whose source terminal is connected to the cathode terminal of the first diode and whose gate terminal is connected to the first bias voltage input terminal and whose drain terminal is connected to the first bias voltage input terminal, 1 PMOS and having a gate terminal connected to the first bias voltage input terminal, an anode terminal connected to the source terminal of the first NMOS and a cathode terminal connected to the first AC power input terminal A first ADCL circuit portion including a second diode; And

A second PMOS having a source terminal connected to the cathode terminal of the third diode and a gate terminal connected to the second bias voltage input terminal, and a drain terminal connected to the second bias voltage input terminal, A second NMOS having a gate terminal connected to the second bias voltage input and an anode terminal connected to a source terminal of the second NMOS and a cathode terminal connected to the second AC power input terminal And a second ADCL circuit portion including a fourth diode.

An AC power source having a phase difference of 180 DEG is input to the first AC power input terminal and the second AC power input terminal, respectively.

The gate terminal of the first NMOS may be commonly connected to the gate terminal of the first PMOS and may be connected to the first bias voltage input terminal. The gate terminal of the second NMOS may be connected to the gate terminal of the second PMOS And may be connected to the second bias voltage input terminal.

Also, the common connection node N1 between the drain terminal of the first PMOS and the drain terminal of the first NMOS may be connected to the voltage output terminal Vout.

A common connection node N2 between the drain terminal of the second PMOS and the drain terminal of the second NMOS may be connected to the voltage output terminal Vout.

According to another aspect of the present invention, there is provided an ADCL inverter improved in current driving capability according to the second embodiment of the present invention,

A first PMOS whose source terminal is connected to the cathode terminal of the first diode and whose gate terminal is connected to the first bias voltage input terminal and whose drain terminal is connected to the first bias voltage input terminal, 1 PMOS, a gate terminal connected to the first bias voltage input terminal, a drain terminal connected to the source terminal of the first NMOS, and a source terminal connected to the first AC power input terminal A first ADCL circuit portion including a third NMOS that functions as a diode; And

A second PMOS whose source terminal is connected to the cathode terminal of the second diode and whose gate terminal is connected to the second bias voltage input terminal and whose drain terminal is connected to the second bias voltage input terminal, 2 PMOS, and a gate terminal connected to the second bias voltage input; a drain terminal connected to a source terminal of the second NMOS; and a source terminal connected to the second AC power input terminal And a second ADCL circuit portion including a fourth NMOS that functions as one diode.

An AC power source having a phase difference of 180 DEG is input to the first AC power input terminal and the second AC power input terminal, respectively.

The gate terminal of the first NMOS may be commonly connected to the gate terminal of the first PMOS and may be connected to the first bias voltage input terminal. The gate terminal of the second NMOS may be connected to the gate terminal of the second PMOS And may be connected to the second bias voltage input terminal.

Also, the common connection node N1 between the drain terminal of the first PMOS and the drain terminal of the first NMOS may be connected to the voltage output terminal Vout.

A common connection node N2 between the drain terminal of the second PMOS and the drain terminal of the second NMOS may be connected to the voltage output terminal Vout.

According to the present invention, since the capacitor is not used, it is possible to reduce the manufacturing cost by improving the integration degree of the chip, and by using two ADCL circuits to operate as one logic gate to improve the current driving capability, Abnormal operation can be reduced, thereby contributing to improvement of the quality of the semiconductor chip product.

1 is a diagram schematically showing a circuit configuration of an ADCL inverter which improves the current driving capability according to the first embodiment of the present invention.
2 is a diagram schematically showing a circuit configuration of an ADCL inverter improved in current driving capability according to a second embodiment of the present invention.
3 is a diagram schematically illustrating a concept of a practical design technique for improving the current driving ability of the ADCL circuit.
4 is a diagram showing a simulation result of an ADCL inverter according to the presence or absence of a load capacitor.
5 is a diagram showing simulation results of an ADCL inverter improved in current driving capability according to the present invention.
6 is a table comparing characteristics of an ADCL inverter improved in current driving capability and a conventional ADCL inverter according to the present invention.

The terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary terms and the inventor can properly define the concept of the term to describe its invention in the best way Should be construed in accordance with the principles and meanings and concepts consistent with the technical idea of the present invention.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise. Also, the terms " part, "" module, "and" device " Lt; / RTI >

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Before describing the embodiments of the present invention in full, the current driving capability improvement (improvement) sought in the present invention will be described first.

ADCL requires capacitors at the bottom of the unit ADCL circuit in order to improve current drive capability in digital circuit and system configuration. However, since the capacitance of the capacitor in the SoC (System on Chip) design is large, the chip area becomes considerably large when the load capacitor is applied to each unit circuit of ADCL. In other words, it means that the integration density of the chip is lowered because the number of circuits is limited in the ADCL-based digital circuit configuration in a limited chip area. Therefore, in order to increase the integration of the ADCL-based digital circuit in the area of the miniaturized / nanoized chip, the present invention proposes a practical design technique for removing the load capacitor and improving the current driving capability of the circuit.

3 is a diagram schematically illustrating a concept of a practical design technique for improving the current driving ability of the ADCL circuit.

Referring to FIG. 3, when one power supply and one ADCL unit circuit are formed, if the load capacitor is removed, the output drive of the ADCL circuit may not be as shown in FIG. 3A. This occurs only when the power supply input is in a low period. Therefore, if the output current and voltage can be generated even in a period where no output occurs as shown in FIG. 3B, the current driving capability of the ADCL will be improved.

Hereinafter, embodiments of the present invention will be described based on the above concept.

1 is a diagram schematically showing a circuit configuration of an ADCL inverter which improves the current driving capability according to the first embodiment of the present invention.

Referring to FIG. 1, an ADCL inverter 100 improved in current driving capability according to the first embodiment of the present invention includes a first ADCL circuit unit 110 and a second ADCL circuit unit 120. The first ADCL circuit unit 110 includes a first diode 111, a first PMOS transistor 112, a first NMOS transistor 113 and a second diode 114. The second ADCL circuit unit 120 includes a first diode 111, And includes a third diode 121, a second PMOS 122, a second NMOS 123, and a fourth diode 124. We will explain this configuration in more detail.

The first ADCL circuit unit 110 includes a first diode 111 having an anode terminal connected to the first AC power input terminal 102 and a source terminal connected to the cathode terminal of the first diode 111, A first PMOS 112 connected to the first bias voltage input terminal 104 and a drain terminal connected to a drain terminal of the first PMOS 112 and a gate terminal connected to the first bias voltage input terminal 104, 1 NMOS 113 and a second diode 114 having an anode terminal connected to the source terminal of the first NMOS 113 and a cathode terminal connected to the first AC power input terminal 102.

The first AC power input terminal 102 and the second AC power input terminal 101 are respectively supplied with AC power having a phase difference of 180 degrees with respect to each other. This is explained again later.

The gate terminal of the first NMOS 113 may be commonly connected to the gate terminal of the first PMOS 112 and may be connected to the first bias voltage input terminal 104. The common connection node N1 between the drain terminal of the first PMOS 112 and the drain terminal of the first NMOS 113 may be connected to the voltage output terminal 105. [

The second ADCL circuit unit 120 includes a third diode 121 having an anode terminal connected to the second AC power input terminal 101 and a source terminal connected to the cathode terminal of the third diode 121, A second PMOS 122 connected to the second bias voltage input terminal 103 and having a drain terminal connected to the drain terminal of the second PMOS 122 and a gate terminal connected to the second bias voltage input terminal 103; 2 NMOS 123 and a fourth diode 124 having an anode terminal connected to the source terminal of the second NMOS 123 and a cathode terminal connected to the second AC power input terminal 101.

The gate terminal of the second NMOS 123 may be commonly connected to the gate terminal of the second PMOS 122 and connected to the second bias voltage input terminal 103. A common connection node N2 between the drain terminal of the second PMOS 122 and the drain terminal of the second NMOS 123 may be connected to the voltage output terminal 105. [

In the ADCL inverter 100 in which the current driving capability is improved according to the first embodiment of the present invention having the above configuration, two inverter circuits, that is, the first ADCL circuit portion 110 and the second ADCL circuit portion 120, A first AC power source (not shown) that is input through respective AC power input terminals 101,

Figure 112016022081015-pat00001
And a second AC power source (
Figure 112016022081015-pat00002
) Are the same, and each output is composed of one output terminal 105. The AC power input through each of the first AC power input terminal 102 and the second AC power input terminal 101 has a phase difference of 180 degrees with respect to each other and even when the power is input to the ADCL inverter 100 and the current does not flow Current, thereby compensating for and improving the current driving capability. This can be redefined by a single ADCL inverter.

Each network of the first ADCL circuit unit 110 and the second ADCL circuit unit 120 can be roughly divided into a pull-up network and a pull-down network, Up network includes diodes 111 and 121 and PMOSs 112 and 122 for preventing reverse current and diodes 114 and 124 and NMOSs 113 and 123 for preventing reverse current in a pull-down network.

The first and second PMOSs 112 and 122 of the first and second ADCL circuit units 110 and 120 are turned on when the clock signal (bias voltage) is input through the bias voltage input terminals 103 and 104, and the power supply voltage input through the first and second AC power input terminals 101 and 102 is applied to the voltage output terminal 105. [ When the clock signal (bias voltage) is inputted at a high level through the bias voltage input terminals 103 and 104, the first and second NMOSs 113 and 123 of the first and second ADCL circuit units 110 and 120 are turned on The regenerative operation of the charge is performed.

2 is a diagram schematically showing a circuit configuration of an ADCL inverter improved in current driving capability according to a second embodiment of the present invention.

2, the ADCL inverter 200 improved the current driving capability according to the second embodiment of the present invention includes the first ADCL circuit unit 210 and the second ADCL circuit unit 220, as in the first embodiment described above, . The first ADCL circuit part 210 includes a first diode 211, a first PMOS 212, a first NMOS 213 and a third NMOS 214. The second ADCL circuit part 220 includes a first ADCL circuit part 210, And includes a second diode 221, a second PMOS 222, a second NMOS 223, and a fourth NMOS 224. We will explain this configuration in more detail.

The first ADCL circuit unit 210 includes a first diode 211 whose anode terminal is connected to the first AC power input terminal 202 and a source terminal connected to the cathode terminal of the first diode 211, A first PMOS transistor 212 having a drain terminal connected to the drain terminal of the first PMOS 212 and a gate terminal connected to the first bias voltage input terminal 204; 1 NMOS 213, a drain terminal connected to the source terminal of the first NMOS 213, a source terminal connected to the first AC power input terminal 202, and a third terminal connected to the first AC power input terminal 202, And an NMOS 214.

Here, the first AC power input terminal 202 and the second AC power input terminal 201 are respectively supplied with AC power having a phase difference of 180 degrees. Since this has been described above, it will be omitted here.

The gate terminal of the first NMOS 213 may be connected to the gate terminal of the first PMOS 212 and may be connected to the first bias voltage input terminal 204. A common connection node N1 between the drain terminal of the first PMOS 212 and the drain terminal of the first NMOS 213 may be connected to the voltage output terminal 205.

The second ADCL circuit unit 220 includes a second diode 221 having an anode terminal connected to a second AC power input terminal, a source terminal connected to the cathode terminal of the second diode 221, A second PMOS 222 connected to the input terminal 203 and a drain terminal connected to the drain terminal of the second PMOS 222 and a gate terminal connected to the second NMOS 222 connected to the second bias voltage input 203 And a fourth NMOS 224 having a drain terminal connected to the source terminal of the second NMOS 223 and a source terminal connected to the second AC power input terminal 201 and serving as a diode, ).

The gate terminal of the second NMOS 223 may be commonly connected to the gate terminal of the second PMOS 222 and connected to the second bias voltage input terminal 203. A common connection node N2 between the drain terminal of the second PMOS 222 and the drain terminal of the second NMOS 223 may be connected to the voltage output terminal 205.

The gate terminal of the third NMOS 214 may be commonly connected to the drain terminal of the third NMOS 214 and connected to the source terminal of the first NMOS 213. Similarly, the gate terminal of the fourth NMOS 224 may be commonly connected to the drain terminal of the fourth NMOS 224 and connected to the source terminal of the second NMOS 223.

4 is a diagram showing a simulation result of an ADCL inverter according to the presence or absence of a load capacitor.

4A is a simulation result of a conventional ADCL inverter to which a load capacitor is applied, and FIG. 4B is a simulation result of a conventional ADCL inverter in which a load capacitor is removed. It can be seen that when the load capacitor is removed during the pull-up network operation ((B)), the current driving capability is lower than that of the conventional ADCL inverter ((A)) using the load capacitor. As described above, in the SoC design, it is necessary to remove the load capacitor in order to apply the ADCL to the digital circuit. However, it can be confirmed that the current driving ability of the circuit is rather reduced when the load capacitor is removed. Therefore, the present invention proposes an ADCL inverter (the ADCL inverter according to the first and second embodiments of the present invention) as described above in order to complement (improve) the current driving capability while removing the capacitor.

5 is a diagram showing simulation results of an ADCL inverter improved in current driving capability according to the present invention.

Referring to FIG. 5, when the bias voltage V IN is applied to the first and second ADCL circuit units 110 and 120 so that the first and second PMOSs 112 and 122 are turned on, In a single ADCL inverter structure, current flows even in a section where no current flows. This makes it possible to compensate for an area where the current does not flow. When also compared with the output voltage (V OUT) and an output current (I OUT) output voltage (V OUT) and an output current (I OUT) in the (B) of Figure 4 at 5, ADCL inverter according to the invention It can be seen that the current driving capability is improved in the case where the capacitor is removed.

6 is a table comparing characteristics of an ADCL inverter improved in current driving capability and a conventional ADCL inverter according to the present invention.

Referring to FIG. 6, in the conventional ADCL inverter, the current driving capability is about 53.11 nW, but in the ADCL inverter according to the present invention, the current driving capability is increased by about 31 times to 1.63 ㎼. Also, assuming that the area of the ADCL inverter is 100% in a 0.18 탆 standard CMOS process in the SoC design, the ADCL inverter according to the present invention requires an area of about 5.4% which is reduced by 94.6%. These results suggest that maximization of practicality for using ADCL in the miniaturization and nanotechnology semiconductor market trends can be achieved.

As described above, the ADCL inverter improved the current driving capability according to the present invention can reduce the manufacturing cost by improving the integration degree of the chips by not using the capacitors, and it is possible to use the two ADCL circuits as one logic gate So that abnormal operation of the logic circuit can be reduced, thereby contributing to improvement of the quality of the semiconductor chip product.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but many variations and modifications may be made without departing from the spirit and scope of the invention. Be clear to the technician. Accordingly, the true scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of the same should be construed as being included in the scope of the present invention.

101, 201: a second AC power input terminal 102, 202: a first AC power input terminal
103, 203: second bias voltage input terminal
104, 204: first bias voltage input terminal 105, 205:
110, 210: first ADCL circuit section 120, 220: second ADCL circuit section
111, 211: first diode 112, 212: first PMOS
113, 213: first NMOS 114: second diode
121: third diode 122, 222: second PMOS
123, 223: second NMOS transistor 124: fourth diode
214: third NMOS 224: fourth NMOS

Claims (10)

A first PMOS whose source terminal is connected to the cathode terminal of the first diode and whose gate terminal is connected to the first bias voltage input terminal and whose drain terminal is connected to the first bias voltage input terminal, 1 PMOS and having a gate terminal connected to the first bias voltage input terminal, an anode terminal connected to the source terminal of the first NMOS and a cathode terminal connected to the first AC power input terminal A first ADCL circuit portion including a second diode; And
A second PMOS having a source terminal connected to the cathode terminal of the third diode and a gate terminal connected to the second bias voltage input terminal, and a drain terminal connected to the second bias voltage input terminal, A second NMOS having a gate terminal connected to the second bias voltage input and an anode terminal connected to a source terminal of the second NMOS and a cathode terminal connected to the second AC power input terminal And a second ADCL circuit portion including a fourth diode.
The method according to claim 1,
And an AC power source having a phase difference of 180 degrees from each other is input to the first AC power input terminal and the second AC power input terminal, respectively.
The method according to claim 1,
Wherein a gate terminal of the first NMOS is commonly connected to a gate terminal of the first PMOS and is connected to the first bias voltage input terminal and a gate terminal of the second NMOS is commonly connected to a gate terminal of the second PMOS, 2 bias voltage input terminal of the ADCL inverter.
The method according to claim 1,
And a common connection node (N1) between a drain terminal of the first PMOS and a drain terminal of the first NMOS is connected to a voltage output terminal (Vout).
The method according to claim 1,
And a common connection node (N2) between a drain terminal of the second PMOS and a drain terminal of the second NMOS is connected to a voltage output terminal (Vout). A first PMOS whose source terminal is connected to the cathode terminal of the first diode and whose gate terminal is connected to the first bias voltage input terminal and whose drain terminal is connected to the first bias voltage input terminal, 1 PMOS, a gate terminal connected to the first bias voltage input terminal, a drain terminal connected to the source terminal of the first NMOS, and a source terminal connected to the first AC power input terminal A first ADCL circuit portion including a third NMOS that functions as a diode; And
A second PMOS whose source terminal is connected to the cathode terminal of the second diode and whose gate terminal is connected to the second bias voltage input terminal and whose drain terminal is connected to the second bias voltage input terminal, 2 PMOS, and a gate terminal connected to the second bias voltage input; a drain terminal connected to a source terminal of the second NMOS; and a source terminal connected to the second AC power input terminal And a second ADCL circuit portion including a fourth NMOS that functions as a single diode.
The method according to claim 6,
And an AC power source having a phase difference of 180 degrees from each other is input to the first AC power input terminal and the second AC power input terminal, respectively.
The method according to claim 6,
Wherein a gate terminal of the first NMOS is commonly connected to a gate terminal of the first PMOS and is connected to the first bias voltage input terminal and a gate terminal of the second NMOS is commonly connected to a gate terminal of the second PMOS, 2 bias voltage input terminal of the ADCL inverter.
The method according to claim 6,
And a common connection node (N1) between a drain terminal of the first PMOS and a drain terminal of the first NMOS is connected to a voltage output terminal (Vout).
The method according to claim 6,
And a common connection node (N2) between a drain terminal of the second PMOS and a drain terminal of the second NMOS is connected to a voltage output terminal (Vout).
KR1020160027306A 2016-03-07 2016-03-07 ADCL(Adiabatic Dynamic CMOS Logic) inverter with enhanced current driving capability KR101740284B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009278433A (en) 2008-05-15 2009-11-26 Yasuhiro Takahashi Two-phase driven cmos adiabatic logic circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009278433A (en) 2008-05-15 2009-11-26 Yasuhiro Takahashi Two-phase driven cmos adiabatic logic circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Seung-Il Cho 외 2인, "Design of the ultra low-power dynchronizer using ADCL buffer for adiabatic logic," IEICE Electronics Express,Vol.9, No.20,1576-1585

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