KR101729146B1 - Neutral point clamped type multi-level inverter having no dead-time - Google Patents

Abstract

According to the present invention, there is provided an NPC type multi-level inverter comprising: a multi-level power supply unit to which at least one voltage source is connected; A first switching unit connected to both ends of the voltage source for interrupting a path of a forward current outputted from the voltage source; And a second switching unit connected to both ends of the voltage source and interrupting a path of a reverse current flowing to the voltage source. The first switching unit or the second switching unit selectively operates according to the direction of the output current, The circuit is not short-circuited.
According to the present invention, since the first switching unit and the second switching unit are connected to the branched line and the output current in the forward direction and the output current in the reverse direction flow in different paths, the circuit is not short-circuited at the moment of switching the output voltage, And has an NPC type inverter circuit configuration capable of operating without time.

Description

[0001] The present invention relates to an NPC type multi-level inverter having no dead time,

The present invention relates to a multi-level inverter of a NPC (Neutral Point Clamped) type, and more particularly to a multi-level inverter capable of switching an output voltage without dead time.

Figure 1 below shows a conceptual diagram of a multilevel inverter that generates an AC output voltage waveform from a series connected DC input power supply.

[Figure 1]

[Figure 1] is a conceptual diagram showing a phase of a 5-level inverter in which four voltage sources are connected in series as an example of a multi-level inverter. As shown in Figure 1, the multilevel inverter has a circuit configuration that can output one of several stages of DC input voltage (V1, V2, V3, V4, V5) to the output like a multiplexer used in signal processing . The SPMT switch (Single-Pole Multiple-Through Switch) changes the contact point in a predetermined cycle in a predetermined cycle and finally generates an output voltage of the AC waveform.

Several types of multi-level inverters conceptually expressed in [Figure 1] have been proposed depending on the circuit configuration method. N-level multilevel inverters with a common arbitrary N level have a Neutral Point Clamped (NPC) scheme, which was first proposed in the early 1990s, and thereafter various types of multi-level inverter configurations that have improved the disadvantages of the NPC scheme. T-type Neutral Point Clamped (MNPC), Mixed Voltage Neutral Point Clamped (ANPC), Advanced Neutral Point Clamped (ANPC), and Cascade.

The following [Figure 2] shows the NPC type multi-level inverter, which shows the half-bridge circuit configuration of the 5-level inverter.

[Figure 2]

2, the half-bridge 5-level inverter consists of 8 IGBT power semiconductor switches (Q1 ~ Q8) and 14 power semiconductor diodes (D1 ~ D14). The DC side power source, which is the input of the inverter, is connected to four DC power sources

), And the NPC multilevel inverter has four DC power sources (

) As shown in [Figure 1].

And the AC voltage waveform is synthesized.

Table 1 below shows the switching table of the 5-level NPC inverter shown in [Figure 2].

[Table 1]

In Table 1, a value of 0 indicates the off state of the IGBT switch, and a value of 1 indicates the on state of the IGBT switch. Looking at the switching logic in [Table 1], four IGBT switches always operate in the ON state. In this case, the Q1 switch operates complementarily with the Q5 switch, the Q2 switch operates complementarily with the Q6 switch, the Q3 switch operates complementarily with the Q7 switch, and the Q4 switch operates complementarily with the Q8 switch Is controlled.

For example, when the switches Q1, Q2, Q3 and Q4 are turned on and the switches Q5, Q6, Q7 and Q8 are turned off, the output point Po is connected to P1, and the output voltage Vo becomes V1. At this time,

Is greater than zero

Flows in the order of P1-Q1-Q2-Q3-Q4-Po-Load,

Is less than zero

Flows in the direction of Load-Po-D4-D3-D2-D1-P1.

When the Q2, Q3, Q4 and Q5 switches are turned on and the Q1, Q6, Q7 and Q8 switches are turned off, the output node Po is electrically connected to P2, and the output voltage Vo becomes V2. At this time,

Is greater than zero

Flows in the order of P2-D9-Q2-Q3-Q4-Po-Load,

Is less than zero

Flows in the direction of Load-Po-Q5-D12-P2.

On the same principle as in the above example, if the ON / OFF control of the switches Q1 to Q8 is controlled according to the switching table in [Table 1], the output voltage can be switched and the AC waveform can be synthesized. The moment when the output voltage is switched from V1 to V2 is as follows in terms of the switching control.

Referring to Table 1, when switching the output voltage from V1 to V2, the Q1 switch must be turned off and the Q5 switch must be turned on at the same time.

&Gt; 0 < / RTI &gt; through the path Q1-Q2-Q3-Q4 during the switching control

Is changed to flow through D9-Q2-Q3-Q4. if

&Lt; 0, it is determined that the current flowing through the path of D4-D3-D2-D1

Lt; RTI ID = 0.0 &gt; Q5-D12. &Lt; / RTI &gt; The commutation is the change in the current path.

Very careful attention must be paid to the safe operation of the inverter when applying a gating signal to turn on and off each IGBT switch in the commutation process. Theoretically, if the Q1 switch is turned on with the Q1 switch turned off at exactly the same time, there is no problem, but in practical cases, serious problems can occur.

If the Q1 switch is turned off a little longer, the Q5 switch may still be turned on while the Q5 switch is turned on. In this case, the DC power supply short-circuit occurs along the path from P1-Q1-Q2-Q3-Q4-Q5-D12-P2, and eventually inverter damage due to excessive current occurs.

If the Q2 switch is turned off and the Q6 switch is turned on at the same time to turn the output voltage from V2 to V3, the Q2 switch will still turn on when the Q2 switch is turned on . Then, a short circuit of the DC power source occurs along the path following P2-D9-Q2-Q3-Q4-Q5-Q6-D13-P3.

The solution to this problem is to control the switch to be turned on after a certain time interval that ensures that the IGBT turning off is completely off. That is, the turn-off IGBT is turned off at a predetermined time, but the turn-on of the IGBT to be turned on is delayed slightly. For example, when turning off the Q1 switch and turning on the Q5 switch at the same time in the above switching process in which the output voltage is switched from V1 to V2, the Q1 switch is turned off and the Q5 switch is turned on after a certain time.

The delay time when the turn-on time of the IGBT switch that is turned on during the turn-on and turn-off of the two IGBTs is slightly delayed is referred to as a dead time. Therefore, in the conventional inverter, the dead time is one of the matters that must be considered in the design of the gating signal generating circuit for on-off switching of the actual inverters.

During the dead time, the output voltage is not determined according to the switching table in [Table 1] but is determined according to the direction of the output current. For example, during the transition of the output voltage from V1 to V2, the output voltage during the dead time is V1 or V2 depending on the direction of the output current. In the process of converting the output voltage from V1 to V2, only the Q2, Q3 and Q4 switches are on during the dead time. At this time,

Is greater than 0 (positive direction), current flows in the direction of P2-D9-Q2-Q3-Q4-Po-Load,

Is smaller than 0 (called reverse direction), current flows in the direction of Po-Q5-D12-P2,

Is greater than 0, Vo = V1,

Is less than 0, Vo = V2.

In the operation of the inverter, the dead time is essential for the safe operation of the inverter. However, since the output voltage waveform of the inverter is distorted, the harmonics of the output voltage waveform are increased, the efficiency of the inverter is decreased, and the control performance is deteriorated.

In addition, the dead time has a problem of reducing the fundamental wave size of the output voltage waveform and lowering the utilization rate of the DC input voltage. When a high-voltage large-capacity system such as a multi-level inverter is constructed, a relatively long dead time is required for a low-voltage small-capacity inverter for safe operation. In this situation, it is desirable that the dead time of the inverter be as short as possible and ultimately it is best to remove it.

There are a number of prior art devices and methods for compensating the inverter output distortion caused by the dead time (Korean Patent Laid-Open No. 10-2013-0081353, etc.). However, the prior art to date has a limitation in not disclosing a control method or a circuit diagram that can ultimately eliminate dead time.

Korean Patent Publication No. 10-2014-0081353

The present invention provides a multi-level inverter having an NPC type multi-level inverter and a circuit diagram capable of operating without a dead time. In particular, the present invention aims to provide a multi-level inverter capable of stably switching the output voltage without dead time by controlling the semiconductor switch in consideration of the direction of the output current, without shorting the power supply when the output voltage is switched.

The present invention also provides a multi-level inverter having no dead time that can be extended to N-level (N = 2, 3, 4, ...) regardless of the number of phases or the number of voltage levels in the NPC type.

According to an aspect of the present invention, there is provided an NPC type multi-level inverter comprising: a multi-level power supply unit to which at least one voltage source is connected; A first switching unit connected to both ends of the voltage source for interrupting a path of a forward current output from the power supply unit; And a second switching unit connected to both ends of the voltage source for interrupting a path of a reverse current flowing into the power supply unit.

Preferably, in the multi-level inverter according to the present invention, the first switching unit or the second switching unit selectively operates according to the direction of the output current, so that the circuit is not short-circuited at the moment when the output voltage is switched.

Preferably, the output node to which the current of the multilevel inverter according to the present invention is output is formed in the first output line and the second output line that are branched so that the forward current and the reverse current may be output in different paths .

Preferably, the first switching unit according to the present invention may include a first terminal connected to one end of the voltage source, a second terminal connected to the other end of the voltage source, and a third terminal for outputting a forward current to the first output line. In this case, the first switching unit may include a first semiconductor switch provided on the first output line so that current is conducted from the first terminal to the third terminal. In addition, the first switching unit may further include a first diode for conducting a current from the second terminal to the third terminal.

Preferably, the second switching unit according to the present invention may include a first terminal through which a reverse current flows from the second output line, a second terminal connected to one end of the voltage source, and a third terminal connected to the other end of the voltage source. In this case, the second switching unit may include a second semiconductor switch provided on the second output line so that current is conducted from the first terminal to the third terminal. In addition, the second switching unit may further include a second diode for conducting a current from the first terminal to the second terminal.

Preferably, the multi-level inverter according to the present invention controls the semiconductor switch of the second switching unit to be off when the output current is positive and to turn off the semiconductor switch of the first switching unit when the output current is reverse And may further include a control unit.

Preferably, the multi-level inverter according to the present invention may further include an inductor unit for limiting a short circuit of the current output from the first switching unit or the second switching unit.

Preferably, the inductor part according to the present invention is connected to the output node of the first output line

A first inductor connected at one end to the first inductor; And the output node of the second output line

And a second inductor connected at one end to the first inductor.

Preferably, the multi-level inverter according to the present invention may further include a third inductor connected in series between the inductor unit and the load to remove harmonics of the output current supplied to the load.

According to the present invention, since the first switching unit and the second switching unit are connected to the branched line and the output current in the forward direction and the output current in the reverse direction flow in different paths, the NPC Type inverter circuit configuration.

In this case, if the control unit controls the semiconductor switches Q1 to Q8 in consideration of the direction of the output current, no interval is required in the process of switching the output voltage. Therefore, the multi-level inverter having this circuit configuration has an effect that it can be driven without a dead time.

Also, according to the present invention, it is possible to expand the circuit configuration of the first switching unit and the second switching unit irrespective of the number of the configuration or the number of voltage sources. Therefore, there is an advantage that it can be widely applied to an NPC type inverter of a high voltage and a large capacity.

Thus, since the NPC inverter according to the present invention does not have a dead time, the distortion of the output voltage waveform can be eliminated, the utilization ratio of the DC voltage can be increased, and the harmonic component of the output voltage waveform can be reduced. Further, according to the present invention, the linearity of the inverter is increased, the control performance and reliability are remarkably improved, and the life of the inverter can be expected to be improved.

FIG. 1A shows a circuit diagram of a multi-level inverter in a half bridge configuration according to an embodiment of the present invention, and FIG. 1B shows a circuit diagram of a multi-level inverter in a half bridge configuration in which the circuit diagram in FIG.
Fig. 2 shows an equivalent circuit when the output current of the multi-level inverter according to the embodiment of the present invention is forward.
3 shows an equivalent circuit when the output current of the multi-level inverter according to the embodiment of the present invention is in the reverse direction.
4 illustrates a half bridge configuration in which a multi-level inverter according to an embodiment of the present invention is extended to an arbitrary N-level inverter.
5 shows a three-phase circuit configuration of a 5-level inverter according to an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the exemplary embodiments. Like reference numerals in the drawings denote members performing substantially the same function.

The objects and effects of the present invention can be understood or clarified naturally by the following description, and the purpose and effect of the present invention are not limited by the following description. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

FIG. 1A shows a circuit diagram of a multi-level inverter 1 in a half bridge configuration according to an embodiment of the present invention, and FIG. 1B shows a circuit diagram of a multi-level inverter 1 in a half bridge configuration in which the circuit diagram in FIG. 1A and 1B, a multilevel inverter 1 includes a power supply unit 10, a first output line 11, a second output line 13, a first switching unit 30, a second switching unit 50, an inductor unit 70, and a control unit (not shown).

One or more voltage sources may be connected in series to the power supply unit 10. One or more input nodes P1 to P5 may be formed by connecting the first switching unit 30 or the second switching unit 50 to a plurality of voltage sources. In this specification, the nodes formed by the voltage source with the first switching unit 30 or the second switching unit 50 are referred to as input nodes P1 to P5.

In this embodiment, FIG. 1A shows a 5-level inverter having four DC voltage sources in the power supply unit 10. FIG. When there are 4 DC voltage sources, 5 input nodes (P1 ~ P5) are formed, and 5 levels of output voltage can be converted. FIG. 1A illustrates five levels of the power supply unit 10. The level and the input node of the inverter according to the number of voltage sources can be expanded.

The input node may be a P1 node to which the V1 voltage is applied, a P2 node to which the V2 voltage is applied, a P3 node to which the V3 voltage is applied, a P4 node to which the V4 voltage is applied, and a P5 node to which the V5 voltage is applied. Each DC voltage source provided in the power supply unit 10 has a voltage difference between the P1 node and the P5 node

/ RTI &gt;

The input nodes P1, P2, P3, P4, and P5 to which the power of five levels are input are connected to the output node (the first node N1) through the switching control of the first switching unit 30 or the second switching unit 50

or

). Accordingly, the multi-level inverter 1 can continuously output the DC voltage as the AC voltage waveform by continuously switching V1 or V2 or V3 or V4 or V5.

The output node of the multilevel inverter 1 according to the present embodiment

or

May be formed in the first output line 11 and the second output line 13, which are branched so that the forward current and the reverse current may be output in different paths, respectively.

In this specification, the terms forward and reverse are used to distinguish the direction in which current flows. In the forward direction,

Current flowing in direction (

). Reverse direction load

The current flowing in the direction of the power supply unit 10

).

Also, in this specification, the first output line (11)

Lt; RTI ID = 0.0 &gt;

And the second output line 13 is a line to which the output node

Lt; RTI ID = 0.0 &gt;

. A semiconductor switch of the first switching unit 30 or the second switching unit 50 may be provided on the first output line 11 and the second output line 13, and a specific connection relationship will be described later.

The first switching unit 30 is connected to both ends of the voltage source and can control the path of the forward current output from the voltage source. The first switching unit 30 includes a first terminal 31 connected to one end P1 of the voltage source and a second terminal 32 connected to the other end P2 of the voltage source and a first output line 11, And a third terminal 33 for outputting it.

In addition, the first switching unit 30 may include a semiconductor switch and a diode. In this embodiment, the semiconductor switch of the first switching unit 30 may be provided as an IGBT switch.

The first semiconductor switch Q1 may be provided on the first output line 11 so that current is conducted from the first terminal 31 to the third terminal 33. [ The first diode D2 may be provided to conduct current from the second terminal 32 to the third terminal 33. [ In this case, the first diode D2 is connected such that the anode is connected to the second terminal 32 and the cathode is connected to the third terminal 33. [

As shown in FIG. 1A, in the 5-level NPC inverter, four first switching units 30 are provided to form five input nodes P1, P2, P3, P4 and P5. The first switching unit 30 may be connected to the multilevel inverter 1 according to the level of the voltage source. The first switching unit 30 may be connected to the multilevel inverter 1 according to the level of the voltage source.

Referring to FIG. 1B, a plurality of the first switching units 30 and the second switching units 50 may be extended in a cascade connection manner. That is, the added first switching unit 30 'is extended to connect the first terminal 31' to the third terminal 33 of the first switching unit 30 described above. In the same principle, the added second switching unit 50 'may be extended to connect the third terminal 53' to the first terminal 51 of the second switching unit 50, which will be described later.

Also, in this specification, the ordinal expressions of the first and second numbers are used to distinguish a plurality of semiconductor switches and diodes. 1A and 1B, the first switching unit 30 is illustrated as an example of the first switching unit 30 connected to the P1 and P2 input nodes. However, the first switching unit 30 is connected to the first output line 11 by Q2 and Q3 , And the Q4 semiconductor switch can be understood as the first semiconductor switch Q1. In addition, D3, D4 and D8 can be understood as the first diode D2 on the same principle.

The second switching unit 50 is connected to both ends of the voltage source and can control the path of the current flowing in the reverse direction to the power supply unit 10. The second switching unit 50 includes a first terminal 51 to which a reverse current flows from the second output line 13, a second terminal 52 connected to one end P4 of the voltage source, And a third terminal 53 connected to the second terminal.

The second switching unit 50 may include a semiconductor switch and a diode. In this embodiment, the semiconductor switch of the second switching unit 30 may be provided as an IGBT switch.

The second semiconductor switch Q8 may be provided on the second output line 13 such that a current flows from the first terminal 51 toward the third terminal 53. [ And the second diode D7 may be provided to conduct current from the first terminal 51 to the second terminal 52. [ In this case, the second diode D7 is connected such that the anode is connected to the first terminal 51 and the cathode is connected to the second terminal 52.

For convenience of description, the second switching unit 50 connected to the input nodes P4 and P5 has been exemplarily described. The Q5, Q6 and Q7 semiconductor switches connected to the second output line 13 on the same principle 2 semiconductor switch Q8. In addition, D1, D5, and D6 can be understood as a second diode D7 on the same principle.

According to the present embodiment, the first switching unit 30 and the second switching unit 50 are provided on the branched output lines unlike the conventional NPC type inverters. In this case, the semiconductor switches Q1 to Q4 and the diodes D2, D3, D4 and D8 of the first switching unit 30 conduct the current output from the power supply unit 10 in the forward direction, The semiconductor switches Q5 to Q8 and the diodes D1, D5, D6 and D7 turn on the current flowing into the power supply unit 10. Accordingly, the multilevel inverter 1 according to the present embodiment outputs the positive output current (

) And the reverse output current (

Can flow in different paths. If the semiconductor switches Q1 to Q8 are appropriately controlled in this circuit configuration, no interval is required for switching the voltage, and the dead time can be eliminated. The switching table of the related control unit will be described later.

The inductor unit 70 is connected to the first output line 11 or the second output line 13,

or

) May be restricted. The inductor unit 70 can limit the short circuit current of the circuit that may occur in the commutation process. The circuit diagram according to the present embodiment may cause a short circuit in the course of switching the direction of the current. The inductor section 70 is connected to the output node (first output line)

) And the output node of the second output line (

) Of the inductor connected in series to prevent the short circuit of the circuit which may be generated in switching between the forward direction and the reverse direction of the output current.

The inductor unit 70 includes a first inductor

) And the second inductor

). The first inductor

) Is connected to an output node (&quot;

), And the second inductor (

) Of the second output line 13 is connected to the output node (

). &Lt; / RTI &gt;

The first inductor

) And the second inductor

Regardless of the level expansion of the power supply unit 10 or the first switching unit 30, the output node of the first output line 11

And the output node of the second output line 13

Respectively. Therefore, the inductor section 70 has a structure that can be connected to the multilevel inverter 1 regardless of the expansion of the circuit.

In the present embodiment, the multilevel inductor 1 includes an inductor unit 70 and a load (

) Connected in series between the load (

A third inductor for removing harmonics of an output current supplied to the first inductor

).

Although not shown in FIG. 1, the multilevel inverter 1 may include a control unit for controlling the first switching unit 30 and the second switching unit 50. In this circuit configuration, since the control unit operates the semiconductor switches Q1 to Q8 in consideration of the direction of the current and does not require characteristics in which two semiconductor switches must simultaneously perform complementary switching at the time of conversion of the output voltage, Switching is possible.

The control unit outputs the output current

The second semiconductor switches Q5 to Q8 are turned off and the output currents

The first semiconductor switches Q1 to Q4 can be controlled to be turned off. In the multilevel inverter 1 according to the present embodiment,

The first switching unit 30 or the second switching unit 50 is selectively operated so that the circuit is not short-circuited at the moment when the output voltage is switched.

That is,

Unlike the conventional NPC inverter switching table, the second semiconductor switches Q5 to Q8 are kept in the OFF state, and only the ON / OFF of the first semiconductor switches Q1 to Q4 is adjusted. On the other hand,

, The control unit keeps the first semiconductor switches Q1 to Q4 in the OFF state and adjusts only the ON / OFF of the second semiconductor switches Q5 to Q8. The control unit selectively controls the first switching unit 30 or the second switching unit 50 according to the current direction in this manner.

The switching table of the control unit is shown in Table 2 below. Hereinafter, the switching control of the controller and the switching of the output voltage without a dead time will be described in detail with reference to Table 2 below.

[Table 2]

The multi-level inverter 1 according to Fig.

) Can be interpreted as being divided into a forward direction and a reverse direction. Figure 2 shows the output current

) Is the forward direction.

2,

Is in the forward direction, the second semiconductor switches Q5 to Q8 are omitted because they have no meaning in interpretation.

end. Output Current (

) Is the forward direction.

> 0)

Referring to FIG. 2 and [Table 2], the output current

) Is a positive current having a positive value, the output node

The semiconductor switches Q5, Q6, Q7 and Q8 to all the gates connected to the reverse current

) Becomes zero. In this state, the output current

)

And

Is determined according to the switching state of the first semiconductor switches Q1 to Q4. The principle that the output voltage is switched by the switching control in the control unit is as follows.

2, when Q1, Q2, Q3, and Q4 are all turned on

Are supplied through Q1, Q2, Q3 and Q4,

Is V1. This is because the reverse voltage is applied to D2, D3, D4 and D8 by the turned on Q1, Q2, Q3 and Q4, and all the paths of D2, D3, D4 and D8 are blocked.

On the other hand, when Q1 is turned off and Q2, Q3 and Q4 are turned on,

Is supplied through D2 and Q2, Q3 and Q4

Is V2. This is because the reverse voltage is applied to D3, D4, and D8 by Q2, Q3, and Q4 that are turned on, and the paths of D3, D4, and D8 are cut off.

On the other hand, when Q1 and Q2 are turned off and both Q3 and Q4 are turned on,

Is supplied through D3 and Q3, Q4

Is V3. This is because a reverse voltage is applied to D4 and D8 by Q3 and Q4 which are turned on, and all the paths of D4 and D8 are cut off.

On the other hand, when Q1, Q2 and Q3 are turned off and Q4 is turned on,

Is supplied through D4 and Q4

Becomes V4. This is because, due to the turned-on Q4, a reverse voltage is applied to D8 and the path of D8 is cut off.

On the other hand, if both Q1, Q2, Q3 and Q4 are turned off,

Is supplied via D8

Becomes V5. This is because Q1, Q2, Q3 and Q4 are all turned off, so that only D8 provides the only path for supplying the output current.

The commutation process of For example, in order to commutate the output voltage from V1 to V2, the control unit applies a turn-on gating signal to Q1, Q2, Q3, and Q4 and applies a turn-off signal to the turn- Q3 and Q4 can be continuously applied with a turn-on signal.

When Q1 is turned off to convert the output voltage from V1 to V2, the current

Is commutated immediately to D2 and the output voltage is immediately changed from V1 to V2. That is, the output voltage of V1 or V2 is determined depending on whether the switch Q1 is turned on or off while the switches Q2, Q3 and Q4 are turned on, and no dead time is required in the process of switching between the two voltages.

Figure 3 shows the output current

) Is the reverse direction. 3,

The first semiconductor switches Q1 to Q4 connected to the first output line are omitted because they have no meaning in the interpretation.

I. Output Current (

) In the reverse direction (

<0)

Is a reverse current having a negative value, the output node

When Q1, Q2, Q3, and Q4 to all of the connected gates are turned off

Becomes zero. In this state, the output current

) Current

Is determined according to the switching state of the second semiconductor switches Q5 to Q8. The principle that the output voltage is switched by the switching control in the control unit is as follows.

3, when Q5, Q6, Q7, and Q8 are all turned on,

Is introduced through Q5, Q6, Q7 and Q8

Becomes V5. This is because a reverse voltage is applied to D1, D5, D6, and D7 by Q5, Q6, Q7, and Q8 that are turned on to block all paths of D1, D5, D6, and D7.

On the other hand, when the switch Q8 is turned off and the switches Q5, Q6 and Q7 are both turned on,

Flows through D7 and Q5, Q6 and Q7

Becomes V4. This is because the reverse voltage is applied to the diodes D1, D5 and D6 by the turned on Q5, Q6 and Q7, and the paths of D1, D5 and D6 are cut off.

On the other hand, when the switches Q7 and Q8 are turned off and the switches Q5 and Q6 are both turned on,

Flows through D6, Q5 and Q6

Is V3. This is because the reverse voltages are applied to the diodes D1 and D5 by the turned-on switches Q5 and Q6, and the paths of D1 and D5 are cut off.

On the other hand, when the switches Q6, Q7 and Q8 are turned off and the switch Q5 is turned on,

Is introduced through D5 and Q5,

Is V2. This is because the reverse voltage is applied to the diode D1 by the turned-on switch Q5, and the path of the diode D1 is cut off.

On the other hand, when the switches Q5, Q6, Q7 and Q8 are all turned off,

Lt; RTI ID = 0.0 &gt; D1, &lt; / RTI &gt;

Is V1. This means that Q5, Q6, Q7 and Q8 are all turned off,

Because it provides the only way in which it flows.

The commutation process of For example, in order to commutate the output voltage from V1 to V2, the control unit applies a turn-off gating signal to the switches Q5, Q6, Q7 and Q8 and applies a turn-on signal to only the instantaneous switch Q5, The turn-off signal may be continuously applied to the switches Q6, Q7 and Q8.

When the switch Q5 is turned on to convert the output voltage from V1 to V2, a reverse voltage is applied to the diode D1 at the same time as the switch Q5 is turned on so that the path of D1 is cut off and the current is commutated immediately to Q5, To V2 immediately. That is, the output voltage of V1 or V2 is determined depending on whether the switch Q5 is turned on or off while the switches Q6, Q7 and Q8 are turned off, and no dead time is required in the process of switching between the two voltages.

As described above, the switching state of the [Table 2]

Is forward (

> 0) Controls the switches Q5, Q6, Q7 and Q8 to be in the off state regardless of the output voltage,

Is in the reverse direction (

<0) It can be seen that the switches Q1, Q2, Q3, and Q4 are controlled to be in an off state regardless of the output voltage.

The multi-level inverter 1 according to the present embodiment has the forward output current

And the reverse output current

Flows in different paths, and there is no risk of short circuit because the path of output voltage switching is not overlapped. In addition, the control unit can switch the output voltage to V1 or V2 depending on whether the switch Q1 is on or off when the switch Q1 is on or off when the switch Q5 is on. According to the control method of the control unit, no dead time is required during the voltage switching process in the circuit configuration.

4 shows a half bridge configuration in which a multi-level inverter 1 according to an embodiment of the present invention is extended to an arbitrary N-level inverter. 5 shows a three-phase circuit configuration of the 5-level inverter 1 according to the embodiment of the present invention.

4, 2 (N-1) IGBT semiconductor switches and 2 (N-1) power semiconductor diodes are provided to constitute an N-level inverter having N-1 DC voltage sources connected to the power supply unit 10 . Accordingly, the first switching unit 30 and the second switching unit 50 of the multi-level inverter 1 have (N-1) additional cascade configurations.

The first inductor of the inductor unit 70

) And the second inductor

Are connected to only one of the first output line and the second output line, even if the level is extended. In this embodiment, the first inductor

) And the second inductor

) Can be designed to have the same value.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. will be. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by all changes or modifications derived from the scope of the appended claims and equivalents of the following claims.

1: Multi-level inverter 11: First output line
13: second output line 10:
30: first switching unit 31: first terminal of the first switching unit
32: second terminal 33 of the first switching unit: third terminal of the first switching unit
50: second switching unit 51: first terminal of the second switching unit
52: second terminal of the second switching unit 53: third terminal of the second switching unit
70: Inductor part

Claims (10)

In an NPC type multilevel inverter,
A multi-level power supply unit to which at least one voltage source is connected;
A first switching unit connected to both ends of the voltage source for interrupting a path of a forward current output from the power supply unit; And
And a second switching unit connected to both ends of the voltage source for interrupting a path of a reverse current flowing into the power supply unit,
The first switching unit or the second switching unit selectively operates according to the direction of the output current so that the circuit is not short-circuited when the continuously switched output voltage is switched,
A first output line and a second output line branched from each other are formed so that the forward current and the reverse current can be output in different paths, respectively, the first switching unit is connected on the first output line, And the second output line is connected to the second output line.
delete The method according to claim 1,
Wherein the first switching unit comprises:
A first terminal connected to one end of the voltage source, a second terminal connected to the other end of the voltage source, and a third terminal outputting a forward current in the first output line,
And a first semiconductor switch provided on the first output line so that current flows from the first terminal to the third terminal.
The method of claim 3,
Wherein the first switching unit comprises:
Further comprising a first diode for conducting a current from the second terminal to the third terminal.
The method according to claim 1,
Wherein the second switching unit comprises:
A second terminal connected to one end of the voltage source and a third terminal connected to the other end of the voltage source,
And a second semiconductor switch provided on the second output line so that current flows from the first terminal to the third terminal.
6. The method of claim 5,
Wherein the second switching unit comprises:
Further comprising a second diode for conducting a current from the first terminal to the second terminal.
The method according to claim 1,
Further comprising a control unit for controlling the semiconductor switch of the second switching unit to be off when the output current is positive and controlling the semiconductor switch of the first switching unit to be off when the output current is reverse. Level inverter.
The method according to claim 1,
Further comprising an inductor unit for limiting a short-circuit of a current output from the first switching unit or the second switching unit.
9. The method of claim 8,
The inductor unit includes:
The output node of the first output line

A first inductor connected at one end to the first inductor; And
The output node of the second output line

And a second inductor to which one end is connected.
9. The method of claim 8,
And a third inductor connected in series between the inductor unit and the load to remove harmonics of an output current supplied to the load.

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